Chapter Four

Multiprocessors and Components Interfacing

Multiprocessor Configuration.

Multiprocessor means a set of processors connected to execute

instructions simultaneously.

There are three basic multiprocessor configurations.

 Coprocessor configuration.
 Closely coupled configuration.
 Loosely coupled configuration.

Coprocessor Configuration:

A Coprocessor is a specially designed circuit on microprocessor chip

which can perform the same task very quickly, which the
microprocessor performs. It reduces the work load of the main
processor. The coprocessor shares the same memory, IO
system, bus, control logic and clock generator. The coprocessor
handles specialized tasks like mathematical calculations,
graphical display on screen, etc.

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 The 8086 can perform most of the operations but their instruction
set is not able to perform complex and/or floating point
mathematical operations, so in this case the microprocessor
requires the math coprocessor like Intel 8087 math coprocessor,
which can perform these operations easily and quickly.

The next figure shows the cooperation between the 8086 and the
math coprocessor 8087.
Clock Generator

Processor
8086
Bus control System bus
logic

Coprocessor Memory IO
8087 devices

Block Diagram of Coprocessor Configuration

The connection of the coprocessor and the host processor 8086:

The coprocessor and the host processor are connected via TEST,
RQ/GT and QS0 & QS1 signals.

The TEST signal is connected to BUSY pin of coprocessor and the

remaining 3 pins are connected to the coprocessor’s 3 pins of
the same name.

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 TEST signal takes care of the coprocessor’s activity, i.e. the
coprocessor is busy or idle.

The RT/GT is used for bus arbitration.

The coprocessor uses QS0 & QS1 to track the status of the queue of
the host processor.

Closely Coupled Configuration

A Closely Coupled is a specially designed system on which the

independent processor and the host microprocessor share the
same memory, I/O devices, system bus, control logic, and clock
generator. However, the independent processor fetches and
executes its own instructions and the host processor fetches and
executes its own instructions. The system bus is controlled by
the independent processor and the host processor
independently as shown in the following figure.
Clock Generator

Processor
8086
Bus control System bus
logic

Independent Memory IO
processor devices

Block Diagram of Closely Coupled Configuration

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The connection of the independent processor & the host processor:

Communication between the host and the independent processor is

done through memory space. None of the instructions are used
for communication, like WAIT, ESC, etc.

The host processor manages the memory and wakes up the

independent processor by sending commands to one of its
ports. Then the independent processor accesses the memory to
execute the task.

After completion of the task, it sends an acknowledgement to the

host processor by using the status signal or an interrupt request.

Loosely coupled configuration:

Loosely coupled configuration consists of the number of modules of

the microprocessor based systems, which are connected
through a common system bus. Each module consists of its own
clock generator, memory, I/O devices and is connected through
a local bus as shown in the next figure.

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Clock Generator

Processor
8086
Local bus System bus
control logic control logic

Local Local IO
memory devices

I/O System
System bus

Clock Generator

Processor
8086
Local bus System bus
control logic control logic

Local Local IO
memory devices

System bus

Memory System
Clock Generator

Processor
8086
Local bus System bus
control logic control logic

Local Local IO
memory devices

Block Diagram of Loosely Coupled Configuration

Advantages

Having more than one processor results in increased efficiency.

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Each processor has its own local bus to access the local memory or
I/O devices. This makes it easy to achieve parallel processing.

The system structure is flexible, i.e. the failure of one module doesn’t
affect the whole system failure; faulty module can be replaced
later.

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 Numeric data coprocessor 8087

Need for a numeric co-processor

The 8086 microprocessor is basically an integer processing unit and
works directly on a variety of integer data types. Many programs
used in engineering, science, business … etc need to perform
mathematical operations like logarithms of a number, square
root of a number, sine of an angle … etc. It may also be needed
to perform computations with very large numbers like 10+56, or
very small numbers like 10-67. There are no instructions in 8086
to directly find sine of an angle etc. Also 8086 can only perform
computations on 16 bit fixed point numbers, with a range of –
32768 to +32767. In other words, 8086 does not provide any
intrinsic support for operations on floating point numbers.
It is possible to perform any calculations using only 8086. But if the
speed becomes important, it is necessary to use the dedicated
Numeric co-processor Intel 8087, to speed up the matters. It
typically provides a 100 fold speed increase for floating point
operations. A numeric co-processor is also variously termed as
arithmetic co-processor, math co-processor, numeric processor
extension, numeric data processor, floating point processor etc

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The data types supported by 8087 are:

 Binary Integers.
 Packed decimal numbers.

 Real numbers.
 Temporary real format.

The representation of real number is as follows:

Short Real: A 32 bit number represented in floating point. The
number is decomposed in mantissa and exponent as shown.

0.10101101*21011
mantissa exponent
The exponent is represented on 8 bits from which the most
significant is the sign bit and it’s treated differently. The physical
length of the mantissa is 23 bits. The sign of the real number is
given by the most significant bit as shown in the following
figure.

Sign Exponent Mantissa

This floating point number representation always works with

normalized numbers, meaning that the mantissa’s first bit is

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 always 1, and thus this bit is never written being considered by
default. Thus the mantissa’s real size is 24 bits.
It is important for us to know the actual precision. The mantissa
represents 6-7 digits, while the exponent with its 8 bits raises
their number to the order of ~1038 (the exact number cannot be
determined because it depends on the mantissa). The highest
number is approximately of 1.7 *1038 and the lowest positive
real number in around 10-38.
Long Real: A 64 bit number represented in floating point. The number
is decomposed in mantissa and characteristic. The exponent is
represented on 11 bits from which the most significant is the
sign bit and it’s treated differently. The physical length of the
mantissa is 52 bits. The sign of the real number is given by the
most significant bit Mantissa, 1 bit considered as default, thus
the actual length of the mantissa is 53 bits and these 53 bits
represent approximately 16-17 decimal digits, which means; the
representation of the smallest number in very precise.
Temporary real numbers: An 80 bit number represented in floating
point format. The number is decomposed in mantissa and
for exponant
exponent. The exponent is represented on 15 bits from which
the most significant bit is the sign bit. The physical length of the
mantissa is 64 bits. for mantissa

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The most important features of 8087 numeric data processor are as
follows:
support all types of data
 It supports data of type integer, float, and real types ranging from
2-10 bytes.

 The processing speed is so high that it can calculate multiplication

of two 64-bits real numbers in ~27 µs and can also calculate
square-root in ~35 µs.

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Interfacing of coprocessor 8087 with 8086:

The math coprocessor 8087 is connected to 8086 in its maximum

mode, which means that; the 8086 pin mn/mx is grounded. In
this mode; all control signals are derived using a separate chip
called bus controller "8288".

8086 Bus Controller

S2 – S0 S2 – S0
0808 Clock
8288
RQ/GT RQ /GT
BHE/S7 BHE/S7
Math Coprocessor 8087
A19/S6 – A16/S3 A19 – A16
INTA
AD0 – AD15 AD0 – AD15
IORD
QS0 – QS1 QS0 – QS1
IOWR
Test Busy
Reset MRDC
Reset
Clock Clock MWTC

Ready Ready ALE

y

8284

Clock gen.

Ready

Reset

Clock

Crystal Oscillator.

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The signals S0, S1 and S2 are the status signals of microprocessor 8086
that provide the status of the operation which is used by the Bus
Controller 8087 to generate memory and I/O control signals as
shown in table (1).

S2 S1 S0 Ch Remarks
0 0 0 INTA cycle Unused by 8087
0 0 1 I/O read Unused by 8087
0 1 0 I/O write Unused by 8087
0 1 1 Halt Unused by 8087
1 0 0 Operation code fetch Unused by 8087
1 0 1 Memory read used by 8087
1 1 0 Memory write used by 8087
1 1 1 No bus cycle used by 8087

Table (1)

The signals RQ/GT1 & RQ/GT0 are the Request/Grant signals used by
the 8087 processors to gain control of the bus from the host
processor 8086 for operand transfers.
The busy pin of 8087 is connected to the test pin of 8086 to indicate
that the processor is busy or not to perform its internal
operations, the queue status lines QS0 and the QS1 are connected
to the corresponding pins of 8086 as shown in table 2.

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QS1 QS0 Instruction queue status
0 0 All six instruction queue registers are full (no operation)
0 1 The first instruction operation code in instruction queue is
being executed.
1 0 The instruction queue registers are empty (clear due to
branching operation).
1 1 An instruction operation code in instruction queue other
than the first one is being executed.
Table 2. The instruction queue status QS0 and QS1 output pins of
8086.

Synchronization or cooperation of coprocessor 8087 with the main

host processor 8086:

If the coprocessor 8087 is used with the 8086, then the program can
be written using the instruction set of the processor 8086 along
with the instruction set of the 8087. But the opcode fetch
operation is performed only by 8086 and the instruction code
fetched from memory is stored in the queue registers of 8086 as
well as 8087.

The cooperation of coprocessor 8087 with the main host processor

8086 is performed as follows:

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1 – The coprocessor 8087 will decode all instruction codes, but the
instruction given with "escape" is executed by the coprocessor
8087. Other instructions are decoded and executed by 8086 and
in this case the 8087 performs no operation. (The opcode of
escape is 11011).

2 – The processor 8086 will decode also all instruction codes, but it
executes the instruction given without "escape", when the
processor 8086 decodes any instruction of 8087 it performs two
operations:

i) If the 8087 instruction is performed internally (using the

internal registers), the 8086 performs no operation.

ii) If the 8087 instruction requires data transfer between 8087

and the memory, then the 8086 will start executing
corresponding machine cycle.

Data transfer between 8087 and 8086 cannot be done directly, but it
is performed through memory. The 8087 keeps track the queue
status and the machine cycle of 8086 by reading QS0 and QS1
also the reading status signals S0, S1 and S2.

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Data transfer between 8087 and memory:

When the host processor 8086 decodes any instruction of 8087 that
requires data transfer between the 8087 and the memory, the
8086 generates the following:

i) 20 – bit physical address.

ii) Read/write control signals (S0 – S2).

iii) BHE.

The above generated information is transferred by the

microprocessor 8086, but the data transfer is performed
between the memory and the coprocessor 8087. This data is
ignored by the 8086.

The above generated information also stored internally by the 8087

for further machine cycle.

Some instructions of 8087 require 32/64/80 – bit data transfer. In

such case, the first word is transferred between the 8087 and
memory as stated above and under the control of the host
processor 8086, then the coprocessor 8087 takes the control of
the system bus from 8086 using RQ/GT and the transfer of the
next words/bytes between the 8087 and memory is done

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 without 8086 intervention. During this time the host processor
8086 remains in a hold state.

In this case the coprocessor 8087 can communicate with memory but
not with IO ports.

Wait operations of 8087 and 8086:

There are two states in which the wait operation in the processor
8086 takes place:

i) If it is required that the 8086 should not execute the next

instruction until the coprocessor 8087 completes its current
instruction. When the coprocessor 8087 executes its instruction,
it outputs "busy" = 1, this signal is applied to the "test" pin of
the 8086, when the host processor 8086 checks the "test" pin, if
its value is 1, it enters a wait state, if its value is 0, it executes
the next instruction.

ii) If there is a series of 8087 instructions in the program; then the

8087 requires time to execute these instructions. But the 8086
will ignore this instruction. If it is required that the 8086 should
perform opcode fetch operation when the 8087 complete
execution instruction in instruction queue, then to keep the
8087 waiting 'wait' instruction is given in between the 8087
instruction.

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8087 Architecture

8087 Architecture is divided into two groups, i.e, Control Unit (CU) and
Numeric Extension Unit (NEU).

 The control unit: it handles all the communication between the

processor and the memory such as it receives and decodes
instructions, reads and writes memory operands, maintains
parallel queue, etc. All the coprocessor instructions are ESC
instructions, i.e., they start with ‘F’, the coprocessor only executes
the ESC instructions while other instructions are executed by the
microprocessor.

 The numeric extension unit: handles all the numeric processor

instructions like arithmetic, logical, transcendental, and data
transfer instructions. It has 8 register stacks, which holds the
operands for instructions and their results.

The architecture of 8187 coprocessor is as follows −

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The numeric data processor is a coprocessor which has been
designed to work under the control of the 8086 processor. It
offers additional numeric processing capabilities. It is available
in 5 MHz, 8 MHz and 10 MHz versions 8086 will perform the
opcode fetch cycles and identify the instructions for 8087.

Once the instruction is identified by 8086, it is allotted to 8087 for

further execution. 8086-8087 couplet implements instruction
level master-slave configuration. After the completion of the
8087 execution cycle, the results may be referred back to the
CPU. The 8087 instructions may lie interleaved in the 8086
program as if they belong to the 8086 instruction set. It is the

135
 task of 8086 to identify the 8087 instructions from the program,
send it to the 8087 for execution and get back the results.

All the 8087 instructions assembly mnemonics begins with “F” to

differentiate them from the 8086 integer instructions.

* For example; ADD / MUL /CMP  8086

FADD / FMUL / FCOM  8087

The binary encodings for all 8087 instructions begin with the bit
pattern 11011, decimal 27, sometimes referred to as "escape
codes".

Some instructions of the coprocessor 8087:

The coprocessor 8087 adds 68 new instructions to the instruction set

of the processor 8086, these instructions are fetched by the
8086 microprocessor, but executed by the coprocessor 8087.
These instructions are grouped into the following groups:

1. Data transfer instructions.

2. Constant data transfer instructions.
3. Arithmetic instructions.
4. Comparison instructions.
5. Transcendental instructions.

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 6. Processor control instructions.

When the microprocessor 8086 executes the ESC instruction, then it

passes over the opcode and passes the control of the local buses
to the 8087.

In the following section; only some of the data transfer and

arithmetic instructions are studied.

At first, we use; ST(0) to indicate the top element of the floating point
stack and ST(i) stands for the element number i of the floating
point stack and 1 ≤ i ≤ 7.

Data transfer instructions:

1 – Load instructions:

This set of instructions pushes the specified operand onto the stack.
The menumonics of the instructions is as follows:

menumonic Explanation
FLD Load floating point number to stack top
FILD Load integer to stack top
FBLD Load BCD code to stack top

Example:

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FLD ST(2) [ST (2)] Top of stack ST(0)

FLD Memory [memory] Top of stack ST(0)

2 – Store instructions:

These two instructions store the value in ST to the specified memory

location or register. The menumonics of the instructions is as
follows:

menumonic Explanation
FST Store the stack top to the destination operand
FIST Store the integer stack top to the destination
operand

Example:

FST ST(2) Store the content of stack top ST (0) to the stack pointer
register ST(2).

FIST ST(6) Convert the contents of ST(0) to integer and store it into
the stack pointer register ST (6).

3 – Constant data transfer instructions:

138
 menumonic Explanation
FLDZ Load zero into the the stack top ST (0).
FLD1 Load constant one into the the stack top.
FLDPI Load π = 3.14 into the the stack top.
FLDL2T Load Log2 of the stack top into the the stack top.
FSQRT Calculate the square root of stack top and load it

into the the stack top, ST (0) = √

FLDG Load Log10 into the the stack top.
FLDLN Load Loge (Ln) into the the stack top.

In case of no operand is specified in the instruction, the operand is

the value of ST (0).

4 – Exchange with stack top.

Exchange the specified register (destination) and the stack top. the
menumonic of the instruction is as follows:

menumonic Explanation
FXCH Exchange the stack top with the destination
operand

In case of no operand is specified in the instruction ST (0) and ST (1)

are exchanged.

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Example:

FXCH ST(6) ST(0) ST(6)

FXCH ST(0) ST(1)

Arithmetic instructions:

1 – Addition instructions:

Add the source to the destination and the sum in the destination. If
two register operands are specified, one must be ST (top of
stack).

If a memory operand is specified the sum must be in ST.

If no operands are specified ST (1) + ST (0) = ST (0).

The menumonic of the instruction is as follows:

menumonic Explanation
FADD Add the source to the destination and the sum
in the destination.

Example:

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FADD ST, ST(3) ST (0) = ST(3) + ST (0)

FADD ST(4), ST ST (4) = ST(0) + ST (4)

FADD ST (0) = ST (1) + ST (0)

FADD WORD PTR [BX] ST (0) = [BX] + ST (0)

2 – Subtraction instructions:

Subtract the source from the destination and the difference in the
destination, which means; destination – source = destination.

If two register operands are specified, one must be ST (top of stack).

If a memory operand is specified the sum must be in ST. If no

operands are specified ST (1) – ST (0) = ST (0).

The menumonic of the instruction is as follows:

menumonic Explanation
FSUB Subtract the source from the destination and the
difference in the destination.
FSUBR (subtract Subtract the destination from the source and the
reversed) difference in the destination.

Example:

141
FSUB ST, ST(3) ST (0) = ST(0) - ST (3)

FSUB ST(4), ST ST (4) = ST(4) - ST (0)

FSUB ST (0) = ST (1) - ST (0)

FSUB WORD PTR [BX] ST (0) = [BX] - ST (0)

FSUBR ST, ST(3) ST (0) = ST(3) - ST (0)

3 – Multiplication instruction:

Multiply the source by the destination and the product in the

destination, which means; source *destination = destination.

If two register operands are specified, one must be ST (top of stack).

If a memory operand is specified the product must be in ST. If no

operands are specified ST (1) * ST (0) = ST (0).

The menumonic of the instruction is as follows:

menumonic Explanation
FMUL Multiply the source from the destination and the
product in the destination.

Example:

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FMUL ST, ST(3) ST (0) = ST(0) * ST (3)

FMUL ST(4), ST ST (4) = ST(4) * ST (0)

FMUL ST (0) = ST (1) * ST (0)

FMUL WORD PTR [BX] ST (0) = [BX] * ST (0)

4 – Division instruction:

Divide the destination by the source and the quotient in the

destination, which means;

If two register operands are specified, one must be ST (top of stack).

If a memory operand is specified the quotient must be in ST. If no

operands are specified = ST (0).

The menumonic of the instruction is as follows:

menumonic Explanation
FDIV Divide the destination by the source and the
quotient in the destination.

Example:

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FDIV ST, ST(3) ST (0) =

FDIV ST(4), ST ST (4) =

FDIV ST (0) =

FDIV WORD PTR [BX] ST (0) =

The remaining set of instructions are not studied here, for more
information about the complete instruction set one can read
any of the microprocessor books used as a reference in this
lecture notes.

Programming examples for the cooperation between the host

microprocessor 8086 and the coprocessor 8087
The following are some programming examples to give the students
good ideas about cooperation between the host
microprocessor 8086 and the coprocessor 8087 to solve
floating point number problems.
Program 1:
Write an assembly language program to calculate the area of 20
different circles, the radius of each circle is stored in memory
starting from effective address EA = 2800H and store the result
in the memory starting from effective address EA = 2900H.

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Solution:
Instruction Explanation
MOV SI, 2800H Initialize the source index
MOV DI, 2900H Initialize the destination index
MOV CX, 0014H The number of circles = 20
Repeat FLD [SI] Load the value of the first radius
in ST (0)
FST ST(1) Store copy of ST(0) in ST (1)
FMUL ST(0)*ST(1) = ST(0) (radius)2
FST ST(1) Store (radius)2 in ST (1)
FLDPI Load π = 3.14 in ST (0)
FMUL ST(0)*ST(1) = ST(0) π*(radius)2
FST [DI] Store the area in the memory
INC SI The next circle
INC DI The next storing location of area
LOOP Repeat

Program 2:
Write an assembly language program to calculate the following
expression √ the values 'a' and 'b' are stored in
memory in effective addresses EA = 3800H and 38005H, then;
store the result in the memory in effective address EA = 2900H.
Solution:

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 Instruction Explanation
MOV SI, 3800H Location of the first number
MOV DI, 3805H Location of the second number
MOV AX, 2900H Location of the result
FLD [SI] Load the value of the first number 'a' in ST (0)
FMUL ST(0), ST(0) ST(0) = a2
FST ST(1) Store copy of ST(0) in ST (1) a2
FLD [DI] Load the value of the second number 'b' in ST (0)
FMUL ST(0), ST(0) ST(0) = b2
FADD ST(1) + ST(0) = ST(0) a2 + b2
FSQRT ST (0) = √
FST [AX] Store the result ST (0) in memory at a location
determined by AX.

146
 Chapter Five
Interfacing keyboard and memory with 8086

In this chapter, we will discuss input/output and memory interfacing

with 8086.
Interface: is the path for communication between two components.
Interfacing is of two types: I/O interfacing and memory
interfacing.
IO Interfacing:
There are various communication devices like the keyboard, mouse,
printer, etc. So, we need to interface the keyboard and other
devices with the microprocessor by using latches and buffers.
This type of interfacing is known as I/O interfacing. The block
diagram of Memory and I/O Interfacing is shown in the following
figure.
Data bus
Microprocessor

Address bus

Control bus

Memory Input / Output

Devices

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Memory Interfacing:
When we are executing any instruction, we need the microprocessor
to access the memory for reading instruction codes and the data
stored in the memory. For this, both the memory and the
microprocessor require some signals to read from and write to
registers.
The interfacing process includes some key factors to match with the
memory requirements and microprocessor signals. The
interfacing circuit should be designed in such a way that it
matches the memory signal requirements with the signals of the
microprocessor.
The connection of the microprocessor and the outside world:
There are two ways of connecting the microprocessor with the
outside world:
1 – Serial connection interface: In this type of connection, the
interface gets a single byte of data from the microprocessor and
sends it bit by bit to the other system serially and vice-a-versa.
2 – Parallel connection interface: In this type of connection, the
interface gets a byte of data from the microprocessor and sends
all bits of the data byte to the other systems simultaneously and
vice-a-versa.

148
In the next section; the communication and interfacing of keyboard
with the microprocessor 8086 using programmable
keyboard/display controller 8279 (PKDC) is studied.
Programmable Keyboard/display 8279
programmable keyboard/display controller 8279 (PKDC) is designed
to simultaneously drives the display of a system and interfaces a
keyboard with the microprocessor.
The PKDC 8279 first scans the keyboard and identifies if any key has
been pressed, and sends the code of the pressed key to the
microprocessor, it also performs the transmission of the data to
the display device. Both of these functions are performed by the
programmable keyboard/display controller 8279 (PKDC) in
repetitive fashion without involving the microprocessor.
OR 8279
Methods of interfacing the keyboard with the microprocessor:
The Keyboard can be interfaced either in the interrupt or the polled
mode.
In the Interrupt mode; the microprocessor is requested service only if
any key is pressed, otherwise the the microprocessor will
continue with its main task.

In the Polled mode; the microprocessor periodically reads an internal

flag of 8279 to check whether any key is pressed or not.

149
Operation of PKDC 8279:
The keyboard consists of maximum 64 keys, which are interfaced
with the the microprocessor by using the key-codes. These key-
codes are de-bounced and stored in an 8-byte first in first out
RAM (FIFO RAM) which can be accessed by the microprocessor.
If a FIFO contains a valid key entry, then the microprocessor is
interrupted in an interrupt mode else the microprocessor checks
the status in polling to read the entry.
Once the microprocessor reads a key entry, then FIFO RAM is
updated, and the key entry is pushed out of the FIFO RAM to
generate space for new entries.
The PKDC 8279 consists of the following function units:
1 – I/O Control and Data Buffer:
This unit controls the flow of data through the microprocessor. Its
data buffer interfaces the external bus of the system with the
internal bus of the microprocessor.
2 – Control and Timing Register and Timing Control:
This unit contains registers to store the the key-codes, display modes,
and other operations as programmed by the the
microprocessor.
The timing and control unit handles the timings for the operation of
the circuit.
3 – Scan counter:

151
It has two modes: encoded mode and decoded mode.
In the encoded mode: the counter provides the binary count that is
to be externally decoded to provide the scan lines for the
keyboard and display.
In the decoded scan mode: the counter internally decodes the least
significant 2 bits and provides a decoded 1 out of 4 scan.
4 – Return Buffers, Keyboard Debounce, and Control:
This unit first scans the key closure row-wise, if found then the
keyboard debounce unit debounces the key entry. In case, the
same key is detected, then the code of that key is directly
transferred to the sensor RAM along with SHIFT & CONTROL key
status.
5 – FIFO/Sensor RAM and Status Logic:
This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key
code of every pressed key is entered into the RAM in sequence.
The status logic generates an interrupt request after each FIFO
read operation untill the FIFO gets empty.
6 – Display Address Registers and Display RAM:
This unit consists of display address registers which holds the
addresses of the word currently read/written by the
microprocessor to/from the display RAM.
The internal structure of the programmable keyboard/display
controller 8279 (PKDC) is shown in the following figure.

151
Operational modes of 8279:
There are two modes of operation on 8279: input mode and output
mode.
Input mode:
This mode deals with the input from the keyboard. This mode is
further classified into 3 modes:
a. Scanned keyboard mode: In this mode, the key matrix can be
interfaced using either encoded or decoded scans. In the
encoded scan, an 8x8 keyboard or in the decoded scan, a 4x8

152
 keyboard can be interfaced. The code of key pressed with
SHIFT and CONTROL status is stored into the FIFO RAM.
b. Scanned sensor matrix: In this mode, a sensor array can be
interfaced with the microprocessor using either encoder or
decoder scans. In the encoder scan, 8x8 sensor matrix or with
decoder scan 4x8 sensor matrix can be interfaced.
c. Strobed input: In this mode, when the control line is set to 0,
the data on the return lines is stored in the FIFO byte by byte.
Output Mode:
This mode deals with display-related operations. It is classified into
two output modes:
Display Scan: This mode allows 8/16 character multiplexed displays
to be organized as dual 4-bit/single 8-bit display units.
Display Entry: This mode allows the data to be entered for display
either from the right side or left side.
In the next section; the transferring of data between IO devices and
the memory using Direct Memory Access 8257 is studied.
OR function of 8257
Direct Memory Access 8257
When the application is designed to transfer a large amount of data,
from input and output device to memory
it may be a waste of time of the microprocessor to transfer the
data from the source to the destination under its control,

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 because the speed of the peripheral devices is less than the
speed of the microprocessor.
The alternative way to transfer a large amount of data is to use a
separate unit to transfer the data and the microprocessor does
other useful work. This unit is called DMA which stands for
Direct Memory Access. It is a device to transfer the data directly
between IO device and memory without microprocessor
intervention. So it performs a high-speed data transfer between
memory and I/O device.
The DMA controller requests the microprocessor to hold its data bus,
address bus and control bus, so the device is free to transfer
data directly to/from the memory. The DMA data transfer is
initiated only after receiving HLDA signal from the
microprocessor.
DMA Operation.
Following is the sequence of operations performed by a DMA:
1- CPU issues the following to DMA:
a. device identification.
a.b. read/write.
Initially, when any device has to send data between the device
c. memory location for read or write.
and the
d. number of memory,
words. the device sends request (DRQ) to DMA
2- CPU executes programs normally.
controller.
3- when the transfar is done DMA interrupts CPU to informe that the transfer is done

b. The DMA controller sends Hold request (HRQ) to the

microprocessor and waits for the microprocessor to assert the
HLDA.

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c. The microprocessor tri-states all the data bus, address bus, and
control bus. The microprocessor leaves the control over bus and
acknowledges the HOLD request through HLDA signal.
d. Now the microprocessor is in HOLD state and the DMA
controller has to manage the operations over buses between
the microprocessor, memory, and I/O devices.
The features of 8257:
The DMA 8257 has the following features
1. The 8257 has four channels and so it can be used to provide
services to four I/O devices.
2. Each channel has 16-bit address and 14-bit counter so; it can
be independently programmed to transfer up to 64kb of data.
3. Each channel can be independently perform read transfer,
write transfer and verify transfer.
4. It generates MARK signal to the peripheral device that 128
bytes have been transferred.

The block diagram of the DMA 8257 is shown in the following figure

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