Arm Cortex
Microprocessors
Asif Zaman Rizve
Lecturer
Department of Electrical & Electronic Engineering
Rajshahi University of Engineering & Technology
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Introduction of ARM
• ARM processor design was initiated by Acorn Computers.
• The name was initially "Acorn RISC Machine" (ARM) and later changed to "Advanced
RISC Machines".
• The architecture is based on RISC (Reduced Instruction Set Computing).
• ARM designs the CPU cores but does not manufacture the processors.
• ARM licenses its CPU core designs to various companies for manufacturing and
integration into their devices.
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Introduction of ARM
• ARM Family includes a variety of 32-bit controllers.
• These processors are used in many commercial applications, including:
• Embedded systems
• Smartphones (e.g., Cortex-A series)
• Printers (e.g., Cortex-R series)
• Medical instruments (e.g., Cortex-M series)
• ARM processors are widely adopted for their low power consumption and high
efficiency in various industries.
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Development History of ARM
Development of ARM processors based on different fabrication sizes from 1995 to 2015:
• 180nm
• 130nm
• 90nm
• 65nm
• 40nm
• 28nm
• 20nm
• 14nm
• 10nm
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Difference Between Cortex-A, Cortex-R and Cortex-M
Features ARM Cortex-A ARM Cortex-R ARM Cortex-M
Real-time embedded Low-power embedded
Target Applications High-performance applications
applications systems
Processor Type Application Processor Real-time Processor Microcontroller (MCU)
High performance, complex
Core Features Real-time capabilities Low-cost, low-power
features
Clock Speed 1 GHz to 3 GHz 100 MHz to 500 MHz 32 MHz to 400 MHz
Instruction Set ARMv7-A, ARMv8-A ARMv7-R, ARMv8-R ARMv6-M, ARMv7-M
Operating System Linux, Android, Windows (RTOS), like FreeRTOS minimal RTOS
Cache L1, L2 (sometimes L3) Small caches no cache
Low-cost, low-power
Main Focus General-purpose computing Safety-critical applications
embedded solutions
Smartphones, Tablets, Laptops, Aerospace systems, Medical IoT devices, sensors,
Example Devices
Servers devices wearables
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Features of ARM7
• ARM7 has 34-bits for the MCU and ALU.
• ARM7 features a 32-bit Data Bus with aligned memory space.
• This means that in each machine cycle, 32-bits of data are transferred via the data bus, and aligned
addressing is used.
• All instructions in ARM7 are 32-bits in length.
• ARM7 has a 32-bit Address Bus, allowing it to interface with up to 4GB of memory
directly.
• ARM7 follows the Von Neumann Architecture:
• This means Data and Code share the same memory space (4GB memory is common for both).
• In the latest versions, ARM has switched to Harvard Architecture, where data and instructions are
stored in separate memory spaces for higher performance.
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• ARM7 has a three-stage pipelining process:
• Fetch: Instruction is fetched from memory.
• Decode: The instruction is decoded to understand what operation is required.
• Execute: The operation is executed.
• ARM7 has 37 registers of 32 bits.
• At a given time, 16 registers (R0-R15) are available for use.
• ARM7 follows a LOAD-STORE Architecture:
• For LOAD and STORE operations, separate instructions are used to move data between memory and registers.
• ARM7 has 7 operating modes:
• ARM7 supports 7 Interrupts:
• ARM7 supports 7 Addressing Modes:
• ARM7 data formats:
• 8-bit = Byte
• 16-bit = Half-Word
• 32-bit = Word
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RISC Design Philosophy
• RISC (Reduced Instruction Set Computer) design is mainly for microcontrollers.
• RISC works on a LOAD-STORE model: Separate instructions are needed for LOAD and
STORE operations (cannot do both in one).
• Most RISC instructions are register-based, leading to faster performance.
• All RISC instructions are of the same size, allowing more efficient parallel execution.
• All instructions operate on the same size of data, improving parallel execution.
• Fetch, decode, and execute times for most instructions are similar, making pipelining
more effective.
• Fewer addressing modes make the instruction set simpler to learn.
• RISC processors have more registers, as most instructions are register-based.
• Less power is consumed because most operations use registers, not memory.
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ARM7 Data Types
Data
Size Storing Condition Extended After Loading
Types
Byte 8 Bits Can be stored at any location • After loading Data from memory location,
16 16 Bits must be Aligned, Must data may have size of 8bits, 16bits or
Half Word 32bits
Bits begin at even address (0,2,4,..)
• But that data must be extended into
32 32 Bits must be Aligned, Must 32bits, as it must be copied into register
Word
Bits begin at multiple of 4 (0,4,8,.) and the size of register is of 32bits.
Unsigned number extension will be done inserting 0
For signed number:
Positive number: insert 0’s in the ahead of number for extending
Negative number: insert 1’s in the ahead of number for extending
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ARM7 Data Types
If Data is +7 = 0000 0111b then it will be extended as:
0000 0000 0000 0000 0000 0000 0000 0111b
If Data is -7 = 1111 1001b (2’s complement) then it will be extended as:
1111 1111 1111 1111 1111 1111 1111 1001b
In Binary representation, MSB shows the polarity of data (+ or -)
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ARM7 Architecture and Data Flow Model
The Data Flow Model describes how data moves through the ARM7 processor during
instruction execution. It focuses on three main activities:
• Execution of Instructions
• Reading Data from Memory
• Writing Data to Memory
Data Flow Steps in ARM7:
• Fetch the instruction.
• Decode the instruction to understand the operation.
• Execute the operation (either arithmetic, logic, or memory access).
• Memory Read/Write if required by the instruction.
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ARM7 Architecture
Memory Bank
Address Data
xxxxx opcode
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ARM7 Core Components
• Address BUS: 32-bits
• Data BUS: 32-bits
• ALU: 32-bits
• Registers: ARM7 has total 37 Registers of 32-bits. 16 general-purpose registers: R0 to R15
• R0–R12: General-purpose
• R13: Stack Pointer (SP)
• R14: Link Register (LR) (Used when executed CALL Instruction)
• R15: Program Counter (PC)
• CPSR (Current Program Status Register): Holds flags (like Zero, Carry, etc.) and mode bits.
• SPSR (Saved Program Status Register): Used in exception modes.
• Barrel Shifter: Enables fast shift and rotate operations before/after ALU operations. Efficient for multiplication,
division-like logic.
• MAC unit: The MAC unit is primarily used for operations that require multiplication followed by accumulation.
Result=(Operand1 × Operand2) + Accumulator
• Incrementor: Updating the Program Counter
• Sign Extender: Extends the sign bit (most significant bit) of a smaller value 13
How ARM7 will execute an instruction
LDR R1, =data_address
LDR R0, [R1]
LDR R3, =5
ADD R2, R0, R3
LDR R4, =result_address
STR R2, [R4]
Step 1: Load Data from Memory (LDR)
The Program Counter (PC) points to the instruction to load data
from memory.
Memory Address is computed by R1 (base address register).
Address Bus is used to communicate the memory address to the
Memory Unit.
The Data Bus reads 32-bits from memory and places it into R0.
Step 2: Perform Arithmetic Operation
The ALU performs the addition: R0 + R3.
The ALU calculates 10 + 5 = 15, which is stored in R2
Step 3: Store Data to Memory (STR)
The Address Bus takes the address from R4 (where to store the
result).
The Data Bus carries the value from R2 (15) to the Memory Unit.
The Memory stores the value at the address given by R4.
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Basic Assembly Syntax Example
AREA myCode, CODE, READONLY
ENTRY ; Entry point
start
MOV R0, #10 ; Load immediate value 10 into register R0
MOV R1, #5 ; Load immediate value 5 into register R1
ADD R2, R0, R1 ; Add R0 and R1, store result in R2 (R2 = 10 + 5)
B end ; Branch to the label "end"
end
STOP ; End of the program (halt execution)
END ; Marks the end of the program
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Basic Example of Memory Access
AREA myMem, CODE, READWRITE ; Define memory area for read-write operations
ENTRY ; Entry point
start
MOV R0, #1000 ; Load address 1000 into R0
LDR R1, [R0] ; Load data from memory at address in R0 into R1
ADD R1, R1, #5 ; Add 5 to the value in R1
STR R1, [R0] ;Store the new value in R1 back to the memory at address in R0
B end ; Branch to the end label
end
STOP ; End the program
END ; Marks the end of the program
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Thank You
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