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IO Pad Insertion

The document discusses adding I/O pads to a chip design at the gate-level netlist stage. It provides examples of adding input and output pads to a sample design module and connecting them to the internal signals. It also describes generating an .ioc file to specify the pad locations and types for power, I/O and corner pads before running placement and routing. Correctly connecting the I/O pads and specifying pad types and locations is important for accurate simulation and successful physical implementation of the chip design.

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Aparna Tiwari
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1K views7 pages

IO Pad Insertion

The document discusses adding I/O pads to a chip design at the gate-level netlist stage. It provides examples of adding input and output pads to a sample design module and connecting them to the internal signals. It also describes generating an .ioc file to specify the pad locations and types for power, I/O and corner pads before running placement and routing. Correctly connecting the I/O pads and specifying pad types and locations is important for accurate simulation and successful physical implementation of the chip design.

Uploaded by

Aparna Tiwari
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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I/O Pad Insertion for SOC Encounter

Meng Kai Hsu, Meng-Kai Hsu EDA Lab

Gate-Level Netlist
For a chip design the I/O pads should be added on the top design,

module.
I1 I2 M O1

Pad_I1 Pad_I2

CHIP I1 I2 M O1 Pad_O1

Gate-Level Netlist (Example)


module M (O1, I1, I2); output O1; input I1; input I2; endmodule; module CHIP (O1, I1, I2); // top module with I/O pads output O1; input I1, I2; wire i_I1, i_I2, i_O1; i i I1 i I2 i O1 M M (.O1(i_O1), .I1(i_I1), .I2(i_I2)); PDIDGZ Pad_I1 (.PAD(I1), .C(i_I1)); PDIDGZ P d i2 ( PAD(I2) .C(i_I2)); Pad_i2 (.PAD(I2), C(i I2)) PDO02CDG Pad_O1(.PAD(O1), .I(i_O1)); endmodule; Modified design (CHIP.v)
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module M (O1, I1, I2); output O1; t t O1 input I1; input I2; Endmodule; Original design (M.v)

Gate-Level Netlist (Notes)


Pads PDIDGZ and PDO02CDG are available types for input

and output pads, respectively, for tsmc18 process. There are a so ot e also other types of I/O pa s cou be use (please refer to o /O pads could e used (p ease e e tpz973.v) and for other libraries, different pads might be used (different names, of course). ( ) For accurate simulation, I/O pads should be also considered for timing delay assumptions. That is, tpz973.v should be g y p , p included for tsmc18 process.
E.g., for verilog simulation, you should use g g

ncverilog +access+r tsmc18.v tpz973.v CHIP.v

I/O Pad Assignment


You should write .ioc file according to your design before ioc

P&R. In .v file if no power pad information is included you may v file, included, add a new power pad by yourself.
VDD: PVDD1DGZ PVDD2DGZ // tsmc18 library PVDD1DGZ, VSS: PVSS1DGZ, PVSS2DGZ // tsmc18 library Note: there are two types of power pads: (1) power pads for the

core (design), (2) power pads for I/O pads


Corner pads p
PCORNERDG // tsmc18 library

For other pads (design inputs/outputs), you should arrange


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them by yourself.

I/O Pad Assignment (Example)


Pad_I1 Pad_I2 CHIP I1 O1 I2 M Pad_O1

Version: 1 Pad: CORNER1 NW PCORNERDG Pad: Pad_I1 N Pad: Pad_CoreVDD N PVDD1DGZ Pad: CORNER2 NE PCORNERDG Pad: Pad_I2 W Pad: PAD_CoreVSS W PVSS1DGZ Pad: CORNER3 Pad: Pad_O1 Pad: PAD_IOVDD Pad: P d CORNER4 Pad: PAD_IOVSS SW PCORNERDG S S PVDD2DGZ SE PCORNERDG E PVSS2DGZ

N
I1

CoreVDD

CORNER1 I2 CoreVSS

IOVSS

IOVDD D

O1

I/O Pad Assignment (Notes)


For correct P&R you should make sure that in the .v file P&R, v

(CHIP.v), I/O pads are correctly connected to your original design w t out pads. es g without pa s. For power and corner pads (which are not included in the .v file), pad types should be specified in the .ioc file. Pads are not necessarily uniformly distributed. (That is, we can have different numbers of pads in different directions) However, uniform assignment is suggested. You might use more than one set of power pads (E g (E.g., IOVDD1, IOVDD2, CoreVDD1, CoreVDD2). Different rearrangements will result in different placement placement, routing, timing, power, etc.

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