CMP Chemical mechanical polishing

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Table of Contents
What is CMP? ............................................................................................................................................... 1 Why we use it? ............................................................................................................................................. 2 Advantages and Disadvantage of CMP ....................................................................................................... 4 References ................................................................................................................................................... 5

Chemical Mechanical Polishing

What is it?
CMP, or chemical mechanical polishing, was developed in the late 1980s at least partially as a result of a secret IBM project at the time. Although initially mainly used in CMOS processes, CMP is now increasingly being utilized by MEMS process flows. We recently spoke withDr. Robert Rhoades, CTO of Entrepix, about thehistory of CMP, current trends as well as traditional and emerging CMP MEMS applications. In this comprehensive interview, Robert also provides his insights on the currentCMP cost trends and the emerging 3D stacking and TSV technologies. CMP stands for chemical mechanical polishing (or planarization in some references). The primary purpose of CMP is to differentially remove material (bulk or deposited films) from raised areas on a surface faster than adjacent low areas until the local topography or step height is polished flat. Most CMP applications are intended to achieve an ultraflat, ultrasmooth surface prior to the next process step. The basic CMP process involves holding a wafer or substrate on a rotating carrier and pressing it against a larger polymeric polishing pad held down on a very flat spinning table (or platen) while flooding the interface with a liquid slurry mixture of chemistry and suspended sub-micron abrasive particles. The process pressures, speeds and choice of pad and slurry are highly dependent on the materials, thicknesses, and final surface properties required for a particular step in the fabrication sequence. In the late-1980s to mid-1990s, roughly at the transition period to 0.35 m CMOS design rules, CMP emerged as the premier method for planarization of interlevel dielectric oxide layers, or ILD CMP. The topography resulting from lower levels of patterned films can create a very non-planar ILD surface, which creates severe difficulties for at least three subsequent process steps: photolithography, metal deposition and metal etch. The depth of focus at photolithography sets an upper limit on the amount of surface height variation within a stepper field that can be accommodated and still maintain crisp definition of features over the underlying topography. In order to print smaller feature sizes, topography had to be reduced. A second problem caused by oxide topography was poor sidewall step coverage at the next metal deposition. At design rules greater than 0.35 m, fabs used various process techniques to slope the sidewalls of vias and contacts sufficiently to get step coverage, but these tricks began failing as devices continued to shrink. In similar ways, metal etch was impacted by topography due to the amount of overetch required for complete removal of metal stringers at the bottom inside corners of features.

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SEM photos showing (left) cross section of a sloped-wall M1/M2 via made without CMP, (middle) developmental M1/M2 via in same device using 2 levels of oxide CMP and 1 level tungsten CMP, and (right) multi-level interconnects enabled CMP (image courtesy of Freescale Semiconductor).

Why we use CMP ?

Chemical Mechanical Planarization (CMP) is a process that can remove topography from silicon oxide, metal and polysilicon surfaces. It is the preferred planarization step utilized in deep sub-micron IC manufacturing. More recent scaling of transistor critical dimension has required the use of CMP for applications such as shallow trench isolation (STI) and trenched metal interconnection (Cu damascene). CMP has also been utilized for fabrication and assembly of Micro Electro-Mechanical System (MEMS). In principle, CMP is a process of smoothing and planning surfaces with the combination of chemical and mechanical forces. It can, in a way, be thought of as a hybrid of chemical etching and free abrasive polishing. Mechanical grinding alone may theoretically achieve planarization but the surface damage is high as compared to CMP. Chemistry alone, on the other hand, cannot attain planarization because most chemical reactions are isotropic. However, the removal and planarization mechanism is much more complicated than just considering chemical and mechanical effects separately. CMP makes use of the fact that high points on the wafer would be subjected to higher pressures from the pad as compared to lower points, hence, enhancing the removal rates there and achieving planarization. CMP is most widely utilized in back-end IC manufacturing. In these process technology and steps thin layers of metal and dielectric materials are used in the formation of the electrical interconnections between the active components of a circuit (e.g. transistors, as formed in the front-end processing). As shown in figure 1, the interconnect is manufactured by depositing thin films of materials, and selectively removing or changing the properties of these materials in certain areas. A new level of thin film is deposited on top of old films and the process is repeated many times until the interconnect is complete.

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The goal of the CMP process is to planarize step heights caused by the deposition of thin films over existing nonplanar features, so that further levels may be added onto a flat surface.Damascene process, as well as its upgraded generation dual-damascene, is the critical technology in the transition from aluminum to copper interconnects in semiconductor manufacturing.[3] There are two primary factors driving this transition: the lower resistivity and the increased electromigration resistance that copper offers relative to aluminum. Several new materials and processes are required in this change. In the copper interconnect fabrication process, a simpler dielectric etching replaces metal-etch as the critical step that defines the width spacing of the interconnect lines, while the burden of planarization shifts to the metal deposition and CMP steps. During the CMP of patterned copper wafers, two phenomena copper dishing and SiO2 erosion lead to deviations from the ideal case depicted in figure 2(a). Copper dishing and SiO2 erosion occur during the overpolish step (which is required to ensure complete copper removal across the entire wafer) and are defined schematically in figure 2(b). Copper dishing is defined as the difference in height between the center of the copper line i.e. the lowest point of the dish and the point where the SiO2 levels off i.e. the highest point of the SiO2. Copper dishing occurs because the polishing pad bends slightly into the recess to remove copper from within the recess. The SiO2 erosion is a thinning of the SiO2 layer resulting from the non-zero polish rate of SiO2 during over-polish step. The SiO2 erosion is defined as the difference in the SiO2 thickness before and after the polish step. Both copper dishing and SiO2 erosion are undesirable because they reduce the final thickness of the copper line; and copper dishing leads to non-planarity of the surface resulting in complications when adding multiple levels of metal.

Figure 1 Cross-section diagram of internal dielectric on top of metal line before and after CMP (the left and the middle charts) and application of Metal 2 and ILD 2 (the right chart)

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Figure 2 Left chart: (a) Schematic representation of copper dishing and SiO2 erosion; Right chart: (b) Profilometer trace of a 100m line exhibiting 305nm of dishing

Advantages and disadvantages of CMP

1. Advantages
CMP is a suitable process to achieve global planarization. Different materials can be planarized using CMP. This implies that a wide range of wafer surfaces may be planarized using CMP. A major advantage of using CMP is that multiple materials can be polished in the same cycle. Use of CMP helps in reducing severe topography, which facilitates the fabrication of IC components with tighter tolerances and design rules. CMP also provides an alternate method to etch metals. This helps in overcoming difficulties associated with etching some metals and alloys and also eliminates the need to plasma etch. More importantly, CMP is a subtractive process and helps in removing surface defects. No hazardous gases are used in CMP process unlike dry etching.

2. Disadvantages
One of the major limitations of the CMP process is that it is a relatively new technology for wafer planarization. Hence, there is not much control over the process variables. The introduction of a new technology implies introduction of new defects, which can affect the die yield. These defects may prove critical for features that are smaller than 0.25m in size. Since CMP is a relatively new technology, additional development is required to control the process and metrology. For example, at this point it is difficult to control the end point of the CMP process in order to achieve the desired thickness. The CMP process is also expensive due to high cost of equipment and the high maintenance cost from frequent replacement of parts.

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 References
Wikipedia http://en.wikipedia.org/wiki/Chemical-mechanical_planarization

Chemical Mechanical Planarization (Dr Wang Zhengfeng Dr Yin Ling Ng Sum Huan Teo Phaik Luan) http://maltiel-consulting.com/CMP-Chemical mechanical_planarization_maltiel_semiconductor.pdf

Chemical mechanical planarization- Study of conditioner abrasives.pdf

http://scholarcommons.usf.edu/cgi/viewcontent.cgi?article=1374&context=etd

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