0% found this document useful (0 votes)
384 views13 pages

555-Timer AStable and Monostable

The document summarizes the astable and monostable operations of a 555 timer integrated circuit. In astable mode, the 555 timer produces a continuous train of pulses with no external trigger. The pulse width is determined by the values of the timing resistor and capacitor. In monostable mode, the 555 timer produces a single pulse of defined width in response to an external trigger signal. The pulse width is determined by the RC time constant of the timing resistor and capacitor. The 555 timer uses internal comparators, a flip-flop, and a transistor switch to charge and discharge the timing capacitor and produce the output pulses in both modes of operation.

Uploaded by

enzuek
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
384 views13 pages

555-Timer AStable and Monostable

The document summarizes the astable and monostable operations of a 555 timer integrated circuit. In astable mode, the 555 timer produces a continuous train of pulses with no external trigger. The pulse width is determined by the values of the timing resistor and capacitor. In monostable mode, the 555 timer produces a single pulse of defined width in response to an external trigger signal. The pulse width is determined by the RC time constant of the timing resistor and capacitor. The 555 timer uses internal comparators, a flip-flop, and a transistor switch to charge and discharge the timing capacitor and produce the output pulses in both modes of operation.

Uploaded by

enzuek
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 13

555 Timer Monostable & Astable operations

Suchendranath Popuri

Internal Diagram of 555 timer

S. Popuri

VIT

Functions
The voltage divider has three equal 5K resistors. It divides the input voltage (Vcc) into three equal parts.

The two comparators are op-amps which compare the voltages at their inputs and saturate depending upon which is greater.
The flip-flop is a bi-stable device. It generates two values, a high value equal to Vcc and a low value equal to 0V. The transistor is being used as a switch, it connects pin 7 (discharge) to ground when it is closed

S. Popuri

VIT

Astable operation

S. Popuri

VIT

Astable Mode

S. Popuri

VIT

Astable Mode

S. Popuri

VIT

Steps
Assume output(Q) is initially 1 This means,Qbar=0 and transistor Q14 is OFF Capacitor C will charge towards Vcc through Ra and Rb When C voltage crosses Vcc/3,S=0.this however has NO effect on the output since S-0,R=0 maintains the previous state. But when C voltage crosses 2Vcc/3,output of upper comparator becomes 1,resetting the flip flop. Thus output(Q) becomes 0,Qbar =1 which turns ON Q14 Now,C has a path to discharge through Rb (through Q14)(current from Vcc also flows through Ra and Q14 to GND) C voltage decreases exponentially till it becomes just below Vcc/3.At this instant,Lower comparator is triggered and FF is set(S=1) Hence output(Q) becomes high again.Qbar becomes 0 which turns OFF Q14.Hence Capacitor cannot discharge,but starts charing towards Vcc through Ra and Rb. Cycle repeats
7

S. Popuri

VIT

Astable-Time period
Charging Interval: TH Discharging Interval: TL Period of Oscillation: TH RA TL RB C ln 2 RA RA 2RB C ln 2 1 2RB C ln 2 100%

RB C ln 2

1 Frequency of Oscillation: T TH Duty Cycle: d = 100% T

R A RB R A 2RB

S. Popuri

VIT

Monostable Operation

S. Popuri

VIT

Monostable mode

10

S. Popuri

VIT

Monostable mode

11

S. Popuri

VIT

Steps
Initially 555 is reset,Q=0, Qb=1.Hence output(Q)=0 Pin no.6 is almost at GND since Qb turns ON Transistor Q14 and drives it to saturation Trigger input(Pin no2) is held at some positive value > Vcc/3,say 2 V Hence S=0,R=0 and the circuit is stable at output logic 0(0 volts) When a negative trigger is applied at 2,S becomes logc 1.FF is set,i.e output(pin no3) goes high. Now,Qbar being 0 turns offf Transistor Q14 So,capacitor C,being connected to Vcc through R starts charging towards Vcc The moment capacitor voltage > 2Vcc/3,R becomes 1,resetting the FF.Hence output(Q) becomes 0. Qbar becomes 1 which quickly tutns ON the transistor and discharges the capacitor voltage Circuit stays in 0 untill a trigger comes again
12

S. Popuri

VIT

Monostable mode

The pulse width of time t, which is the time it takes to charge C to 2/3 of the supply voltage, is given by

t
13

RC ln(3) 1.1RC
S. Popuri

VIT

You might also like