VIT
UNIVERSITY
ECE 301 - VLSI System Design
(Fall 2011)
Structural Modeling
Prof.S.Sivanantham School of Electronics Engineering VIT University Vellore, Tamilnadu. India E-mail: ssivanantham@vit.ac.in
Objectives
After completing this chapter, you will be able to: Describe what is the structural modeling Describe how to instantiate gate primitives Describe D ib how h to t model d l a design d i in i gate t primitives i iti Describe inertial and transport delays Describe how to specify delays in gates Describe hazards and their effects in gate networks
Slides are adopted from Digital System Designs and Practices Using Verilog HDL and FPGAs , John Wiley ECE301 VLSI System Design FALL 2011 S.Sivanantham
Components of Verilog Module
ECE301 VLSI System Design
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Structural Modeling
Structural style: Modeled as a set of interconnected components. Modules/UDPs - Modules/UDPs may or may not be synthesized. - A gate-level module is usually synthesizable. Gate primitives: There are 12 gate primitives. - Gate primitives are synthesizable. Switch primitives: There are 16 switch primitives. - They are usually used to model a new logic gate circuit at switch level. - They are not synthesizable, synthesizable in general. general
ECE301 VLSI System Design FALL 2011 S.Sivanantham
Gate Primitives
and/or gates have h one scalar l output and d multiple l i l scalar l inputs i are used to realize the basic logic operations include and or xor nand nor xnor buf/not gates have one scalar input and one or multiple scalar outputs are used to realize the not operation, are used to buffer the output of an and/or gate, gate are used as controlled buffers include buf not bufif0 notif0 bufif1 notif1
ECE301 VLSI System Design FALL 2011 S.Sivanantham
and/nand Gates
i1 i2
out
i1 i2
out
and 0 1 x z
i2 0 0 0 0 0 1 0 1 x x x 0 x x x z 0 x x x
nand 0 1 x z
i2 0 1 1 1 1 1 1 0 x x x 1 x x x z 1 x x x
i1
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or/nor Gates
i1 i2
out
i1 i2
out
or 0 1 x z
i2 0 0 1 x x 1 1 1 1 1 x x 1 x x z x 1 x x
nor 0 1 x z
i2 0 1 0 x x 1 0 0 0 0 x x 0 x x z x 0 x x
i1
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xor/xnor Gates
i1 i2
out
i1 i2
out
xor 0 1 x z
i2 0 0 1 x x 1 1 0 x x x x x x x z x x x x
xnor 0 1 x z
i2 0 1 0 x x 1 0 1 x x x x x x x z x x x x
i1 1
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buf/not Gates
in in 0 1 x z out 0 1 x x
out
in in 0 1 x z out 1 0 x x
out
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bufif0/notif0 Gates
in ctrl ctrl 1 x z z z z L H x x
out
in ctrl ctrl 1 x z z z z H L x x
out
bufif0 0 1 x z
0 0 1 x x
z L H x x
notif0 0 1 x z
0 1 0 x x
z H L x x
in n
Note that: L represents 0 or z and H represents 1 or z.
ECE301 VLSI System Design FALL 2011 S.Sivanantham
in n
bufif1/notif1 Gates
in ctrl ctrl 1 x 0 1 x x L H x x
out
in ctrl ctrl 1 x 1 0 x x H L x x
out
bufif1 0 1 x z
0 z z z z
z L H x x
notif1 0 1 x z
0 z z z z
z H L x x
in
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Instantiation of Basic Gates
To instantiate and/or gates
gatename [instance_name](output, input1, input2, ..., inputn);
instance_name is optional.
module basic_gates (x, y, z, f) ; input x, y, z; output f ; wire a, b, c; // internal nets // Structural modeling using basic gates. nor g1 (b, x, y); not g2 2 (a, ( x); ) and g3 (c, a, z); nor g4 (f, b, c); endmodule
x y z
g1 g2 a g3
b g4 c f
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Array of Instances
Array instantiations may be a synthesizer dependent! Suggestion: you had better to check this feature before using the synthesizer.
wire [3:0] out, in1, in2; // basic array instantiations of nand gate. nand n_gate[3:0] (out, in1, in2); // this is equivalent to the following: nand n_gate0 (out[0], in1[0], in2[0]); nand n_g gate1 (out[1], ( [ ], in1[1], [ ], in2[1]); [ ]); nand n_gate2 (out[2], in1[2], in2[2]); nand n_gate3 (out[3], in1[3], in2[3]);
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An Example --- A 1-Bit 1 Bit Full Adder
module full_adder_structural(x, y, c_in, s, c_out); // I/O p port declarations input x, y, c_in; output s, c_out; wire s1, c1, c2, c3; // Structural modeling of the 1-bit 1 bit full adder. adder xor xor_s1(s1, x, y); // compute sum. xor xor_s2(s, s1, c_in); and and_c1(c1, x, y); // compute carry out. and and_c2(c2, x, c_in); x y and and_c3(c3, y, c_in); c_in or or_cout(c_out, c1, c2, c3); endmodule
s1 s c1 c2 c3
c_out
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An Example --- A 4-to-1 4 to 1 Multiplexer
i0 y0 i1 y1 out i2 y2
module mux4_to_1_structural (i0, i1, i2, i3, s1, s0, out); i3 input i0, i1, i2, i3, s1, s0; output out; wire s1n, s0n; // Internal wire declarations wire y0, y1, y2, y3; s1 // Gate instantiations not (s1n, s1); // Create s1n and s0n signals. not (s0n, s0); and (y0, i0, s1n, s0n); // 3-input and gates instantiated and d (y1, ( 1 i1 i1, s1n, 1 s0); 0) and (y2, i2, s1, s0n); and (y3, i3, s1, s0); or ( (out, ,y y0, ,y y1, ,y y2, ,y y3); ); // 4-input p or g gate instantiated endmodule
ECE301 VLSI System Design FALL 2011
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An Example --- A 9-Bit 9 Bit Parity Generator
x[0] x[1] x[2] x[3] x[4] x[5] x[6] x[7] x[8]
c g d i e h f op ep
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An Example --- A 9-Bit 9 Bit Parity Generator
module p parity y_g gen_9b_structural(x, ( , ep, p, op); p); // I/O port declarations input [8:0] x; output ep, op; wire ire c, c d, d e, e f, f g, g h, h j; xor xor_11(c, x[0], x[1]); // first level xor xor_12(d, x[2], x[3]); xor xor_13(e, x[4], x[5]); xor xor_14(f, x[6], x[7]); xor xor_21(g, c, d); // second level xor xor_22(h, e, f); xor xor_31(i, xor 31(i g, g h); // third level xor xor_ep(ep, i, x[8]); // fourth level xnor xnor_op(op, i, x[8]); endmodule
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Applications of Tristate Buffers
To instantiate tristate buffers
buf_name[instance_name](output, input, control);
The instance_name is optional.
// Data selector 2-to-1 mux module two_to_one_mux_tristate (x, y, s, f); input x, x y, y s; output f; // internal declaration tri f; // data selector body bufif0 b1 (f, x, s); // enable if s = 0 bufif1 b2 (f, y, s); // enable if s = 1 endmodule
x f y S
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wand/triand and wor/trior
triand/ wand 0 1 x z
0 0 0 0 0
1 0 1 x 1
x 0 x x x
z 0 1 x z
trior/ wor 0 1 x z
0 0 1 x 0
1 1 1 1 1
x x 1 x x
z 0 1 x z
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Wired AND Gates
module open_drain (w, x, y, z, f); i t w, x, y, z; input output f; wand f; // internal declaration // wired AND logic gate nand n1 (f, w, x); nand n2 (f, y, z); endmodule
y
w x f y z f = ( wx )' ( yz )'
ECE301 VLSI System Design FALL 2011 S.Sivanantham
VDD
RL
f
w Q2n Q1n Q2n Q1n
Representing Hierarchy
fulladd n_sum U1 halfadd U2 halfadd n carry1 n_carry1 n_carry2 U3 carry
Create hierarchy by Instantiating module(s) Connecting module ports to local port, net or variable
a b
sum
Y You must d declare l most local l l cin objects before you use them
module fulladd (input a, b, cin, output sum, carry); wire n_sum, n_carry1, n_carry2; halfadd U1(.a(a), .b(b), .sum(n_sum), .carry(n_carry1)); halfadd U2(.a(n_sum), .b(cin), .sum(sum), .carry(n y _carry2)); y or U3(carry, n_carry2, n_carry1); endmodule
Built-in OR primitive
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Connecting Hierarchy Ordered Port Connection
Map local port, net or variable to instance port by position in the order the ports are declared
With this syntax you can very easily make a mistake!
fulladd instance
a b sum U1 halfadd b carry a n_sum n_carry1
module fulladd (input a, b, cin, output sum, carry); wire n_sum, n_carry1, n_carry2; halfadd U1(a, b, n_sum, n_carry1); h lf dd U2(n_sum, halfadd U2( cin, i sum, n_carry2); 2) or U3(carry, n_carry2, n_carry1); wire n_carry1 of module endmodule fulladd mapped to output carry of instance U1 of module halfadd module halfadd (a, b, sum, carry); input a, b; output sum, carry; assign g sum = a ^ b; assign carry = a & b; endmodule ECE301 VLSI System Design FALL 2011 a b
module
sum halfadd carry
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Inertial and Transport Delay Models
Inertial delay model The signal events do not persist long enough will not be propagated to the output. It is used to model gate delays. delays It is the default delay model for HDL (Verilog HDL and VHDL). Transport delay model Any signal events will be propagated to the output. It is used to model net (i.e. wires) delays. The default delay of a net is zero.
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The Effects of Inertial Delays
x y
f
y
10 12 14 16 18 20
2 b
10 12 14 16 18 20
wire a; and #4 (b, x, y); // Inertial delay and #4 (a, x, y); not #1 (f, a);
Inertial delay
2 a 2 f 2
10 12 14 16 18 20
10 12 14 16 18 20
10 12 14 16 18 20
ECE301 VLSI System Design
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The Effects of Transport and Inertial Delays
x y
f
x 2 y 2 4 6 8 10 12 14 16 18 20 4 6 8 10 12 14 16 18 20
wire #2 a; // Transport delay and #4 (b, x, y); // Inertial delay and #4 (a, x, y); not #1 (f, (f a);
Inertial delay Transport delay
b 2 a 2 f 2 4 6 8 10 12 14 16 18 20 4 6 8 10 12 14 16 18 20 4 6 8 10 12 14 16 18 20
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Gate Delay Specifications
Gate Delay Specifications Specify propagation delay only:
gatename #(prop_delay) [instance_name](output, in_1, in_2,);
Specify both rise and fall times:
gatename #(t_rise, t_fall) [instance_name](output, in_1, in_2,);
Specify rise, fall, and turn-off times:
gatename #(t_rise, t_fall, t_off) [instance_name](output, in_1, in_2,); Delay specifier: min:typ:max
ECE301 VLSI System Design
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Gate Delays Specifications
// Only specify one delay and #(5) a1 (b, x, y); // Only specify one delay using min:typ:max not #(10:12:15) n1 (a, x); // Specify two delays using min:typ:max and #(10:12:15, 12:15:20) a2 (c, a, z); // Specify three delays using min:typ:max or #(10:12:15, 12:15:20, 12:13:16) o2 (f, b, c);
ECE301 VLSI System Design
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Hazards and Their Effects
A hazard is an unwanted short-width output signal when the i inputs to a combinational bi i l circuit i i changes. h These unwanted signals are generated when different paths from input to output have different propagation delays. Static hazard Dynamic hazard
1 0 1 0 1 0
0 1 0 1 1 0 1 0
(a) static-1 hazard
(b)static-0 hazard
(c) dynamic hazard
ECE301 VLSI System Design
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A Static Hazard Example
x y c z a f b
module hazard_static (x, y, z, f); input x, y, z; output f; // internal declaration wire a, b, c; // internal net // logic circuit body and #5 a1 (a, (a x, x y); not #5 n1 (c, x); and #5 a2 (b, c, z); or #5 o2 (f, b, a); endmodule
ECE301 VLSI System Design
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t pd t pd
t pd t pd d
a b f
t pd t pd t pd
t pd
t pd t pd
t pd
Hazard
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A Dynamic Hazard Example
x 3 2 y w z 1 e a c f b d
x=y=z=1 w a b c d e f
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A Dynamic Hazard Example
// dynamic hazard example module hazard_dynamic(w, x, y, z, f); input w, x, y, z; output f; // internal declaration wire a, b, c, d, e; // internal net // logic circuit body nand #5 nand1 (b, x, w); not #5 n1 (a, w); nand #5 nand2 (c, a, y); nand #5 nand3 (d, b, c); nand #5 nand4 (e, w, z); nand #5 nand5 (f, d, e); endmodule
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A Dynamic Hazard Example
`timescale 1ns / 1ns module hazard_dynamic_tb; reg w, x, y, z; //Internal // l signals i l declarations: d l i wire f; // Unit Under Test port map hazard_dynamic y UUT ( .w(w),.x(x),.y(y),.z(z),.f(f)); initial begin w = 1'b0; 1'b0 x = 1'b0 1'b0; y = 1'b0 1'b0; z = 1'b0 1'b0; #5 x = 1'b1; y = 1'b1; z = 1'b1; #30 w = 1'b1; #20 w = 1'b0; #190 $finish; // terminate the simulation end initial $monitor($realtime "ns $monitor($realtime,, ns %h %h %h %h %h ",w,x,y,z,f); w x y z f); endmodule
ECE301 VLSI System Design FALL 2011 S.Sivanantham
