DM74LS00 Quad 2-Input NAND Gate

August 1986 Revised March 2000

DM74LS00 Quad 2-Input NAND Gate

General Description
This device contains four independent gates each of which performs the logic NAND function.

Ordering Code:
Order Number DM74LS00M DM74LS00SJ DM74LS00N Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Y = AB Inputs A L L H H
H = HIGH Logic Level L = LOW Logic Level

Output B L H L H Y H H H L

2000 Fairchild Semiconductor Corporation

DS006439

www.fairchildsemi.com

DM74LS00

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICCH ICCL Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current with Outputs HIGH Supply Current with Outputs LOW Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max, VIL = Max VCC = Min, IOL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max VCC = Max 20 0.8 2.4 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 0.36 100 1.6 4.4 mA A mA mA mA mA Min Typ (Note 2) Max 1.5 Units V V

Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics
at VCC = 5V and TA = 25C RL = 2 k Symbol tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Parameter CL = 15 pF Min 3 3 Max 10 10 CL = 50 pF Min 4 4 Max 15 15 ns ns Units

www.fairchildsemi.com

DM74LS00

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

www.fairchildsemi.com

DM74LS00

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

www.fairchildsemi.com

DM74LS00 Quad 2-Input NAND Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

www.fairchildsemi.com

DM74LS02 Quad 2-Input NOR Gate

May 1986 Revised March 2000

DM74LS02 Quad 2-Input NOR Gate

General Description
This device contains four independent gates each of which performs the logic NOR function.

Ordering Code:
Order Number DM74LS02M DM74LS02SJ DM74LS02N Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Y= A+B Inputs A L L H H
H = HIGH Logic Level L = LOW Logic Level

Output B L H L H Y H L L L

2000 Fairchild Semiconductor Corporation

DS006441

www.fairchildsemi.com

DM74LS02

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICCH ICCL Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current with Outputs HIGH Supply Current with Outputs LOW Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max, VIL = Max VCC = Min, IOL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max VCC = Max 20 1.6 2.8 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 0.40 100 3.2 5.4 mA A mA mA mA mA Min Typ (Note 2) Max 1.5 Units V V

Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics
at VCC = 5V and TA = 25C RL = 2 k Symbol Parameter CL = 15 pF Min tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Max 13 10 CL = 50 pF Min Max 18 15 ns ns Units

www.fairchildsemi.com

DM74LS02

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

www.fairchildsemi.com

DM74LS02

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

www.fairchildsemi.com

DM74LS02 Quad 2-Input NOR Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

www.fairchildsemi.com

DM74LS08 Quad 2-Input AND Gates

August 1986 Revised March 2000

DM74LS08 Quad 2-Input AND Gates

General Description
This device contains four independent gates each of which performs the logic AND function.

Ordering Code:
Order Number DM74LS08M DM74LS08SJ DM74LS08N Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Y = AB Inputs A L L H H
H = HIGH Logic Level L = LOW Logic Level

Output B L H L H Y L L L H

2000 Fairchild Semiconductor Corporation

DS006347

www.fairchildsemi.com

DM74LS08

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICCH ICCL Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current with Outputs HIGH Supply Current with Outputs LOW Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max, VIH = Min VCC = Min, IOL = Max, VIL = Max IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max VCC = Max 20 2.4 4.4 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 0.36 100 4.8 8.8 mA A mA mA mA mA Min Typ (Note 2) Max 1.5 Units V V

Switching Characteristics
at VCC = 5V and TA = 25C RL = 2 k Symbol Parameter CL = 15 pF Min tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output
Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

CL = 50 pF Min 6 5 Max 18 18

Units

Max 13 11

4 3

ns ns

www.fairchildsemi.com

DM74LS08

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

www.fairchildsemi.com

DM74LS08

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

www.fairchildsemi.com

DM74LS08 Quad 2-Input AND Gates

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

www.fairchildsemi.com

DM74LS10 Triple 3-Input NAND Gate

August 1986 Revised March 2000

DM74LS10 Triple 3-Input NAND Gate

General Description
This device contains three independent gates each of which performs the logic NAND function.

Ordering Code:
Order Number DM74LS10M DM74LS10N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Y = ABC Inputs A X X L H B X L X H C L X X H Output Y H H H L

H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level

2000 Fairchild Semiconductor Corporation

DS006349

www.fairchildsemi.com

DM74LS10

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICCH ICCL Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current with Outputs High Supply Current with Outputs Low Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max, VIL = Max VCC = Min, IOL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max VCC = Max 20 0.6 1.8 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 0.36 100 1.2 3.3 mA A mA mA mA mA Min Typ (Note 2) Max 1.5 Units V V

Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics
at VCC = 5V and TA = 25C RL = 2 k Symbol tPLH tPHL Parameter Min Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output 3 3 CL = 15 pF Max 10 10 Min 4 4 CL = 50 pF Max 15 15 ns ns Units

www.fairchildsemi.com

DM74LS10

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

www.fairchildsemi.com

DM74LS10 Triple 3-Input NAND Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 4 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

DM74LS11 Triple 3-Input AND Gate

August 1986 Revised March 2000

DM74LS11 Triple 3-Input AND Gate

General Description
This device contains three independent gates each of which performs the logic AND function.

Ordering Code:
Order Number DM74LS11M DM74LS11N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Y = ABC Inputs A X X L H B X L X H C L X X H Output Y L L L H

H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level

2000 Fairchild Semiconductor Corporation

DS006350

www.fairchildsemi.com

DM74LS11

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICCH ICCL Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current with Outputs HIGH Supply Current with Outputs LOW Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIH = Min VCC = Min, IOL = Max VIL = Max IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max VCC = Max 20 1.8 3.3 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 0.36 100 3.6 6.6 mA A mA mA mA mA Min Typ (Note 2) Max 1.5 Units V V

Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics
at VCC = 5V and TA = 25C RL = 2 k Symbol Parameter Min tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output 4 3 CL = 15 pF Max 13 11 Min 6 5 CL = 50 pF Max 18 18 ns ns Units

www.fairchildsemi.com

DM74LS11

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

www.fairchildsemi.com

DM74LS11 Triple 3-Input AND Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 4 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

DM74LS20 Dual 4-Input NAND Gate

June 1986 Revised March 2000

DM74LS20 Dual 4-Input NAND Gate

General Description
This device contains two independent gates each of which performs the logic NAND function.

Ordering Code:
Order Number DM74LS20M DM74LS20N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Y = ABCD Inputs A X X X L H B X X L X H C X L X X H D L X X X H Output Y H H H H L

H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level

2000 Fairchild Semiconductor Corporation

DS006355

www.fairchildsemi.com

DM74LS20

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICCH ICCL Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current with Outputs HIGH Supply Current with Outputs LOW Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max, VIL = Max VCC = Min, IOL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max VCC = Max 20 0.4 1.2 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 0.36 100 0.8 2.2 mA A mA mA mA mA Min Typ (Note 2) Max 1.5 Units V V

Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics
at VCC = 5V and TA = 25C RL = 2 k Symbol tPLH tPHL Parameter Min Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output 3 3 CL = 15 pF Max 10 10 Min 4 4 CL = 50 pF Max 15 15 ns ns Units

www.fairchildsemi.com

DM74LS20

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

www.fairchildsemi.com

DM74LS20 Dual 4-Input NAND Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 4 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

DM74LS32 Quad 2-Input OR Gate

June 1986 Revised March 2000

DM74LS32 Quad 2-Input OR Gate

General Description
This device contains four independent gates each of which performs the logic OR function.

Ordering Code:
Order Number DM74LS32M DM74LS32SJ DM74LS32N Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Y=A+B Inputs A L L H H
H = HIGH Logic Level L = LOW Logic Level

Output B L H L H Y L H H H

2000 Fairchild Semiconductor Corporation

DS006361

www.fairchildsemi.com

DM74LS32

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICCH ICCL Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current with Outputs HIGH Supply Current with Outputs LOW Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIH = Min VCC = Min, IOL = Max VIL = Max IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max VCC = Max 20 3.1 4.9 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 0.36 100 6.2 9.8 mA A mA mA mA mA Min Typ (Note 2) Max 1.5 Units V V

Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics
at VCC = 5V and TA = 25C RL = 2 k Symbol tPLH tPHL Parameter Min Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output 3 3 CL = 15 pF Max 11 11 Min 4 4 CL = 50 pF Max 15 15 ns ns Units

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DM74LS32

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

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DM74LS32

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

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DM74LS32 Quad 2-Input OR Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs

October 1988 Revised March 2000

DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs

General Description
The DM74LS47 accepts four lines of BCD (8421) input data, generates their complements internally and decodes the data with seven AND/OR gates having open-collector outputs to drive indicator segments directly. Each segment output is guaranteed to sink 24 mA in the ON (LOW) state and withstand 15V in the OFF (HIGH) state with a maximum leakage current of 250 A. Auxiliary inputs provided blanking, lamp test and cascadable zero-suppression functions.

Features
s Open-collector outputs s Drive indicator segments directly s Cascadable zero-suppression capability s Lamp test input

Ordering Code:
Order Number DM74LS47M DM74LS47N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Logic Symbol

Connection Diagram

VCC = Pin 16 GND = Pin 8

Pin Descriptions
Pin Names A0A3 RBI LT BI/RBO a g BCD Inputs Ripple Blanking Input (Active LOW) Lamp Test Input (Active LOW) Blanking Input (Active LOW) or Ripple Blanking Output (Active LOW) Segment Outputs (Active LOW) (Note 1)
Note 1: OCOpen Collector

Description

2000 Fairchild Semiconductor Corporation

DS009817

www.fairchildsemi.com

DM74LS47

Truth Table
Decimal or Function 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT LT H H H H H H H H H H H H H H H H X H L RBI H X X X X X X X X X X X X X X X X L X A3 L L L L L L L L H H H H H H H H X L X Inputs A2 L L L L H H H H L L L L H H H H X L X A1 L L H H L L H H L L H H L L H H X L X A0 L H L H L H L H L H L H L H L H X L X BI/RBO H H H H H H H H H H H H H H H H L L H a L H L L H L H L L L H H H L H H H H L b L L L L L H H L L L H H L H H H H H L c L L H L L L L L L L H L H H H H H H L Outputs d L H L L H L L H L H L L H L L H H H L e L H L H H H L H L H L H H H L H H H L f L H H H L L L H L L H H L L L H H H L g H H L L L L L H L L L L L L L H H H L (Note 3) (Note 4) (Note 5) (Note 2) (Note 2) Note

Note 2: BI/RBO is wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO). The blanking out (BI) must be open or held at a HIGH level when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blanking or a decimal 0 is not desired. X = input may be HIGH or LOW. Note 3: When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a HIGH level regardless of the state of any other input condition. Note 4: When ripple-blanking input (RBI) and inputs A0, A1, A2 and A3 are LOW level, with the lamp test input at HIGH level, all segment outputs go to a HIGH level and the ripple-blanking output (RBO) goes to a LOW level (response condition). Note 5: When the blanking input/ripple-blanking output (BI/RBO) is OPEN or held at a HIGH level, and a LOW level is applied to lamp test input, all segment outputs go to a LOW level.

Functional Description
The DM74LS47 decodes the input data in the pattern indicated in the Truth Table and the segment identification illustration. If the input data is decimal zero, a LOW signal applied to the RBI blanks the display and causes a multidigit display. For example, by grounding the RBI of the highest order decoder and connecting its BI/RBO to RBI of the next lowest order decoder, etc., leading zeros will be suppressed. Similarly, by grounding RBI of the lowest order decoder and connecting its BI/RBO to RBI of the next highest order decoder, etc., trailing zeros will be suppressed. Leading and trailing zeros can be suppressed simultaneously by using external gates, i.e.: by driving RBI of a intermediate decoder from an OR gate whose inputs are BI/RBO of the next highest and lowest order decoders. BI/ RBO also serves as an unconditional blanking input. The internal NAND gate that generates the RBO signal has a resistive pull-up, as opposed to a totem pole, and thus BI/ RBO can be forced LOW by external means, using wiredcollector logic. A LOW signal thus applied to BI/RBO turns off all segment outputs. This blanking feature can be used to control display intensity by varying the duty cycle of the blanking signal. A LOW signal applied to LT turns on all segment outputs, provided that BI/RBO is not forced LOW.

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DM74LS47

Logic Diagram

Numerical DesignationsResultant Displays

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DM74LS47

Absolute Maximum Ratings(Note 6)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 6: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current a g @ 15V = VOH (Note 7) HIGH Level Output Current BI /RBO LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 250 50 24 70 Nom 5 Max 5.25 Units V V V A A mA C

Note 7: OFF-State at ag.

Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH IOFF VOL Parameter Input Clamp Voltage HIGH Level Output Voltage Output HIGH Current Segment Outputs LOW Level Output Voltage Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max, VIL = Max, BI /RBO VCC = 5.5V, VO = 15V a g VCC = Min, IOL = Max, VIH = Min, a g IOL = 3.2 mA, BI /RBO IOL = 12 mA, a g IOL = 1.6 mA, BI /RBO II IIH IIL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current
Note 8: All typicals are at VCC = 5V, TA = 25C. Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Min

Typ (Note 8)

Max 1.5

Units V V

2.7

3.4 250 0.35 0.5 0.5 0.25 0.4 0.4 100 20 0.4

VCC = Max, VI = 7V VCC = Max, VI = 10V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 9), IOS at BI/RBO VCC = Max 0.3

A A mA mA mA

2.0 13

Switching Characteristics
at VCC = +5.0V, TA = +25C RL = 665 Symbol Parameter Conditions Min tPLH tPHL tPLH tPHL Propagation Delay An to a g Propagation Delay RBI to a g (Note 10) CL = 15 pF Max 100 100 100 100 ns ns Units

Note 10: LT = HIGH, A0A3 = LOW

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DM74LS47

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

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DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

DM74LS48 BCD to 7-Segment Decoder

January 1992

DM74LS48 BCD to 7-Segment Decoder

General Description
The LS48 translates four lines of BCD (8421) input data into the 7-segment numeral code and provides seven corresponding outputs having pull-up resistors as opposed to totem pole pull-ups These outputs can serve as logic signals with a HIGH output corresponding to a lighted lamp segment or can provide a 1 3 mA base current to npn lamp driver transistors Auxiliary inputs provide lamp test blanking and cascadable zero-suppression functions The LS48 decodes the input data in the pattern indicated in the Truth Table and the segment identification illustration

Connection Diagram
Dual-In-Line Package

TL F 10172 1

Order Number DM74LS48M or DM74LS48N See NS Package Number M16A or N16E

C1995 National Semiconductor Corporation

TL F 10172

RRD-B30M105 Printed in U S A

Absolute Maximum Ratings (Note)

Supply Voltage Input Voltage Operating Free Air Temperature Range DM74LS Storage Temperature Range 7V 7V 0 C to a 70 C
b 65 C to a 150 C

Note The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics table are not guaranteed at the absolute maximum ratings The Recommended Operating Conditions table will define the conditions for actual device operation

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Free Air Operating Temperature 0 4 75 2 08
b 50

DM74LS48 Nom 5 Max 5 25

Units V V V mA mA C

60 70

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol VI VOH IOFF VOL Parameter Input Clamp Voltage High Level Output Voltage Output High Current Segment Outputs Low Level Output Voltage Conditions VCC e Min II e b18 mA VCC Min IOH e Max VIL e Max VCC e Min VO e 0 85V VCC e Min IOL e Max VIH e Min IOL e 2 0 mA VCC e Min II IIH IIL IOS ICCH Input Current Input Voltage Max VCC e Max VI e 7V VCC e Max VI e 2 7V VCC e Max VI e 0 4V VCC e Max VO e 0V at BI RBO (Note 2) VCC e Max VIN e 4 5V
b0 3

Min

Typ (Note 1)

Max
b1 5

Units V V mA

24
b1 3

05 04 01 20
b0 4 b2

mA mA mA mA mA

High Level Input Current Low Level Input Current Short Circuit Output Current Supply Current

38

Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second

Switching Characteristics at VCC e 5V and TA e 25 C

Symbol tPLH tPHL tPLH tPHL
Note LT e HIGH A0 A3 e HIGH

Parameter Min Propagation Delay Time An to ag Propagation Delay Time RBI to af

CL e 15 pF Max 100 100 100 100

Units

ns ns

Numerical Designations

Resultant Displays

TL F 10172 4

Truth Table
Decimal Or Function 0 (Note 1) 1 (Note 1) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI (Note 2) RBI (Note 3) LT (Note 4) Inputs LT H H H H H H H H H H H H H H H H X H L RBI H X X X X X X X X X X X X X X X X L X A3 L L L L L L L L H H H H H H H H X L X A2 L L L L H H H H L L L L H H H H X L X A1 L L H H L L H H L L H H L L H H X L X A0 L H L H L H L H L H L H L H L H X L X BI RBO H H H H H H H H H H H H H H H H L L H a H L H H L H L H H H L L L H L L L L H b H H H H H L L H H H L L H L L L L L H c H H L H H H H H H H L H L L L L L L H Outputs d H L H H L H H L H L H H L H H L L L H e H L H L L L H L H L H L L L H L L L H f H L L L H H H L H H L L H H H L L L H g L L H H H H H L H H H H H H H L L L H

Note 1 BI RBO is wired-AND logic serving as blanking input (BI) and or ripple-blanking output (RBO) The blanking out (BI) must be open or held at a HIGH level when output functions 0 through 15 are desired and ripple-blanking input (RBI) must be open or at a HIGH level if blanking of a decimal 0 is not desired X e input may be HIGH or LOW Note 2 When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a LOW level regardless of the state of any other input condition Note 3 When ripple-blanking input (RBI) and inputs A0 A1 A2 and A3 are at LOW level with the lamp test input at HIGH level all segment outputs go to a LOW level and the ripple-blanking output (RBO) goes to a LOW level (response condition) Note 4 When the blanking input ripple-blanking output (BI RBO) is open or held at a HIGH level and a LOW level is applied to lamp test input all segment outputs go to a HIGH level

Logic Symbol

TL F 10172 2

VCC e Pin 16 GND e Pin 8

Logic Diagram

TL F 10172 3

Physical Dimensions inches (millimeters)

16-Lead Small Outline Molded Package (M) Order Number DM74LS48M NS Package Number M16A

DM74LS48 BCD to 7-Segment Decoder

Physical Dimensions inches (millimeters) (Continued)

16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS48N NS Package Number N16E

LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user
National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018

2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness

National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80

National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960

National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408

National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

August 1986 Revised March 2000

DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
General Description
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. The data on the J and K inputs is allowed to change while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated. A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs.

Ordering Code:
Order Number DM74LS73AM DM74LS73AN Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Inputs CLR L H H H H H CLK X H J X L H L H X K X L L H H X Q0 Q L Q0 H L Toggle Q0 Outputs Q H Q0 L H

H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level = Negative going edge of pulse. Q0 = The output logic level before the indicated input conditions were established. Toggle = Each output changes to the complement of its previous level on each falling edge of the clock pulse.

2000 Fairchild Semiconductor Corporation

DS006372

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DM74LS73A

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL fCLK fCLK tW Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 2) tW Pulse Width (Note 3) tSU tSU tH tH TA Clock HIGH Preset LOW Clear LOW Clock HIGH Preset LOW Clear LOW Setup Time (Note 2)(Note 4) Setup Time (Note 3)(Note 4) Hold Time (Note 2)(Note 4) Hold Time (Note 3)(Note 4) Free Air Operating Temperature 0 0 20 25 25 25 30 30 20 25 0 5 0 70 ns ns ns ns C ns ns Parameter Min 4.75 2 0.8 0.4 8 30 25 Nom 5 Max 5.25 Units V V V mA mA MHz MHz

Note 2: CL = 15 pF, R L = 2 k, TA = 25C and VCC = 5V. Note 3: CL = 50 pF, R L = 2 k, TA = 25C and VCC = 5V. Note 4: The symbol () indicates the falling edge of the clock pulse is used for reference.

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DM74LS73A

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II Input Current @ Max Input Voltage IIH HIGH Level Input Current IIL LOW Level Input Current IOS ICC Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max VI = 7V VCC = Max VI = 2.7V VCC = Max VI = 0.4V VCC = Max (Note 6) VCC = Max (Note 7) J, K Clear Clock J, K Clear Clock J, K Clear Clock 20 4 2.7 3.4 0.35 0.25 0.5 0.4 0.1 0.3 0.4 20 60 80 0.4 0.8 0.8 100 6 mA mA mA A mA Min Typ (Note 5) Max 1.5 Units V V

Note 5: All typicals are at VCC = 5V, TA = 25C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where shorting the outputs to ground may cause the outputs to change logic state, an equivalent test may be performed where VO = 2.125V with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment. Note 7: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock is grounded.

Switching Characteristics
at VCC = 5V and TA = 25C From (Input) Symbol Parameter To (Output) CL = 15 pF Min fMAX tPHL tPLH tPLH tPHL Maximum Clock Frequency Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Clear to Q Clear to Q Clock to Q or Q Clock to Q or Q 30 20 20 20 20 Max 25 28 24 24 28 RL = 2 k CL = 50 pF Min Max MHz ns ns ns ns Units

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DM74LS73A

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

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DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs

August 1986 Revised March 2000

DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

Ordering Code:
Order Number DM74LS74AM DM74LS85ASJ DM74LS74AN Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Inputs PR L H L H H H CLR H L L H H H CLK X X X L D X X X H L X Q H L H L Q0 Outputs Q L H L H Q0

H (Note 1) H (Note 1)

H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level = Positive-going Transition Q0 = The output logic level of Q before the indicated input conditions were established. Note 1: This configuration is nonstable; that is, it will not persist when either the preset and/or clear inputs return to their inactive (HIGH) level.

2000 Fairchild Semiconductor Corporation

DS006373

www.fairchildsemi.com

DM74LS74A

Absolute Maximum Ratings(Note 2)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL fCLK fCLK tW Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 3) Clock Frequency (Note 4) Pulse Width (Note 3) tW Pulse Width (Note 4) tSU tSU tH TA Setup Time (Note 3)(Note 5) Setup Time (Note 4)(Note 5) Hold Time (Note 5)(Note 6) Free Air Operating Temperature Clock HIGH Preset LOW Clear LOW Clock HIGH Preset LOW Clear LOW 0 0 18 15 15 25 20 20 20 25 0 0 70 ns ns ns C ns ns Parameter Min 4.75 2 0.8 0.4 8 25 20 Nom 5 Max 5.25 Units V V V mA mA MHz MHz

Note 3: CL = 15 pF, R L = 2 k, TA = 25C, and VCC = 5V. Note 4: CL = 50 pF, R L = 2 k, TA = 25C, and VCC = 5V. Note 5: The symbol () indicates the rising edge of the clock pulse is used for reference. Note 6: TA = 25C and V CC = 5V.

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DM74LS74A

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II Input Current @ Max Input Voltage Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max VI = 7V Data Clock Preset Clear IIH HIGH Level Input Current VCC = Max VI = 2.7V Data Clock Clear Preset IIL LOW Level Input Current VCC = Max VI = 0.4V Data Clock Preset Clear IOS ICC Short Circuit Output Current Supply Current VCC = Max (Note 8) VCC = Max (Note 9) 20 4 2.7 3.4 0.35 0.25 0.5 0.4 0.1 0.1 0.2 0.2 20 20 40 40 0.4 0.4 0.8 0.8 100 8 mA mA mA A mA Min Typ (Note 7) Max 1.5 Units V V

Note 7: All typicals are at VCC = 5V, TA = 25C. Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO = 2.125V with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment. Note 9: With all outputs OPEN, ICC is measured with CLOCK grounded after setting the Q and Q outputs HIGH in turn.

Switching Characteristics
at VCC = 5V and TA = 25C From (Input) Symbol Parameter To (Output) CL = 15 pF Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Clock to Q or Q 25 25 Max RL = 2 k CL = 50 pF Min 20 35 Max MHz ns Units

Clock to Q or Q Preset to Q

30 25

35 35

ns ns

Preset to Q

30

35

ns

Clear to Q Clear to Q

25 30

35 35

ns ns

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DM74LS74A

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

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DM74LS74A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

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DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

SN74LS76A Dual JK Flip-Flop with Set and Clear

The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions.
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LOW POWER SCHOTTKY

MODE SELECT TRUTH TABLE

OPERATING MODE Set Reset (Clear) *Undetermined Toggle Load 0 (Reset) Load 1 (Set) Hold * INPUTS SD L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l OUTPUTS Q H L H q L H q Q L H H q H L q

16 1

Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously.

PLASTIC N SUFFIX CASE 648

H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Immaterial l, h (q) = Lower case letters indicate the state of the referenced input i, h (q) = (or output) one setup time prior to the HIGHtoLOW clock transition
16 1

SOIC D SUFFIX CASE 751B

GUARANTEED OPERATING RANGES

Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 0.4 8.0 Unit V C mA mA

ORDERING INFORMATION
Device SN74LS76AN SN74LS76AD Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel

Semiconductor Components Industries, LLC, 1999

December, 1999 Rev. 6

Publication Order Number: SN74LS76A/D

SN74LS76A
LOGIC DIAGRAM
2 Q Q 16 1 4 CLEAR (CD) J SET (SD) K K CP J C Q D 3 VCC = PIN 5 GND = PIN 13 CLOCK (CP) 14 SD Q 15 12 6 9 K CP J C Q D 8 10

LOGIC SYMBOL
7 SD Q 11

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 0.65 3.5 0.25 VOL O Output LOW Voltage 0.35 J, K Clear Clock IIH Input HIGH Current J, K Clear Clock Input LOW Current Short Circuit Current (Note 1) Power Supply Current J, K Clear, Clock 20 0.1 0.3 0.4 0.4 0.8 100 6.0 mA VCC = MAX, VIN = 7.0 V 0.5 20 60 80 V A IOL = 8.0 mA 0.4 Min 2.0 0.8 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V

IIL IOS ICC

mA mA mA

VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)

Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Clock Clear Clock, Clear, Set to Output 15 20 ns Min 30 Typ 45 15 20 Max Unit MHz ns VCC = 5.0 50V CL = 15 pF F Test Conditions

AC SETUP REQUIREMENTS (TA = 25C)

Limits Symbol tW tW ts th Parameter Clock Pulse Width High Clear Set Pulse Width Setup Time Hold Time Min 20 25 20 0 Typ Max Unit ns ns ns ns VCC = 5 5.0 0V Test Conditions

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2

SN74LS76A
PACKAGE DIMENSIONS

N SUFFIX PLASTIC PACKAGE CASE 64808 ISSUE R

A
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01

B
1 8

F S

T H G D
16 PL

SEATING PLANE

J T A
M

0.25 (0.010)

D SUFFIX PLASTIC SOIC PACKAGE CASE 751B05 ISSUE J

A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019

16

B
1 8

8 PL

0.25 (0.010)

G F

K C T
SEATING PLANE

X 45 _

M D
16 PL M

0.25 (0.010)

T B

DIM A B C D F G J K M P R

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3

SN74LS76A

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

North America Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 3036752175 or 8003443860 Toll Free USA/Canada Fax: 3036752176 or 8003443867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 8002829855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor European Support German Phone: (+1) 3033087140 (MF 2:30pm to 5:00pm Munich Time) Email: ONlitgerman@hibbertco.com French Phone: (+1) 3033087141 (MF 2:30pm to 5:00pm Toulouse Time) Email: ONlitfrench@hibbertco.com English Phone: (+1) 3033087142 (MF 1:30pm to 5:00pm UK Time) Email: ONlit@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor Asia Support Phone: 3036752121 (TueFri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong 80044223781 Email: ONlitasia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4321 NishiGotanda, Shinagawaku, Tokyo, Japan 1418549 Phone: 81354878345 Email: r14153@onsemi.com Fax Response Line: 3036752167 8003443810 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.

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SN74LS76A/D

DM74LS83A 4-Bit Binary Adder with Fast Carry

August 1986 Revised March 2000

DM74LS83A 4-Bit Binary Adder with Fast Carry

General Description
These full adders perform the addition of two 4-bit binary numbers. The sum () outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. These adders feature full internal look ahead across all four bits. This provides the system designer with partial lookahead performance at the economy and reduced package count of a ripple-carry implementation. The adder logic, including the carry, is implemented in its true form meaning that the end-around carry can be accomplished without the need for logic or level inversion.

Features
s Full-carry look-ahead across the four bits s Systems achieve partial look-ahead performance with the economy of ripple carry s Typical add times Two 8-bit words 25 ns Two 16-bit words 45 ns s Typical power dissipation per 4-bit adder 95 mW

Ordering Code:
Order Number DM74LS83AN Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagram

2000 Fairchild Semiconductor Corporation

DS006378

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DM74LS83A

Truth Table

H = HIGH Level, L = LOW Level Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs 1 and 2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs 3, 4, and C4.

Logic Diagram

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DM74LS83A

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICC1 ICC2 Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max VI = 7V VCC = Max VI = 2.7V VCC = Max VI = 0.4V VCC = Max (Note 3) VCC = Max (Note 4) VCC = Max (Note 5) A or B C0 A or B C0 A or B C0 20 19 22 2.7 3.4 0.35 0.25 0.5 0.4 0.2 0.1 40 20 0.8 0.4 100 34 39 mA A mA mA mA mA Min Typ (Note 2) Max 1.5 Units V V

Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC1 is measured with all outputs open, all B inputs LOW and all other inputs at 4.5V, or all inputs at 4.5V. Note 5: ICC2 is measured with all outputs OPEN and all inputs grounded.

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DM74LS83A

Switching Characteristics
at VCC = 5V and TA = 25C From (Input) Symbol Parameter To (Output) CL = 15 pF Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output C0 to 1 or 2 C0 to 1 or 2 C0 to 3 C0 to 3 C0 to 4 C0 to 4 Ai, Bi to i Ai, Bi to i C0 to C4 C0 to C4 Ai, Bi to C4 Ai, Bi to C4 Max 24 24 24 24 24 24 24 24 17 17 17 17 RL = 2 k CL = 50 pF Min Max 28 30 28 30 28 30 28 30 24 25 24 26 ns ns ns ns ns ns ns ns ns ns ns ns Units

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DM74LS83A 4-Bit Binary Adder with Fast Carry

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

www.fairchildsemi.com

DM74LS85 4-Bit Magnitude Comparator

August 1986 Revised March 2000

DM74LS85 4-Bit Magnitude Comparator

General Description
These 4-bit magnitude comparators perform comparison of straight binary or BCD codes. Three fully-decoded decisions about two, 4-bit words (A, B) are made and are externally available at three outputs. These devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A > B, A < B, and A = B outputs of a stage handling less-significant bits are connected to the corresponding inputs of the next stage handling more-significant bits. The stage handling the leastsignificant bits must have a high-level voltage applied to the A = B input. The cascading path is implemented with only a two-gate-level delay to reduce overall comparison times for long words.

Features
s Typical power dissipation 52 mW s Typical delay (4-bit words) 24 ns

Ordering Code:
Order Number DM74LS85M DM74LS85N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

2000 Fairchild Semiconductor Corporation

DS006379

www.fairchildsemi.com

DM74LS85

Function Table
Comparing Inputs A3, B3 A3 > B3 A3 < B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A3 = B3 A2, B2 X X A2 > B2 A2 < B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A2 = B2 A1, B1 X X X X A1 > B1 A1 < B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A0, B0 X X X X X X A0 > B0 A0 < B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 A>B X X X X X X X X H L L X H L Cascading Inputs A<B X X X X X X X X L H L X H L A=B X X X X X X X X L L H H L L A>B H L H L H L H L H L L L L H A<B L H L H L H L H L H L L L H A=B L L L L L L L L L L H H L L Outputs

H = HIGH Level, L = LOW Level, X = Dont Care

Logic Diagram

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DM74LS85

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II Input Current @ Max Input Voltage IIH HIGH Level Input Current IIL LOW Level Input Current IOS ICC Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max VI = 7V VCC = Max VI = 2.7V VCC = Max VI = 0.4V VCC = Max (Note 3) VCC = Max (Note 4) A<B A>B Others A<B A>B Others A<B A>B Others 20 10 2.7 3.4 0.35 0.25 0.5 0.4 0.1 0.1 0.3 20 20 60 0.4 0.4 1.2 100 20 mA mA mA A mA Min Typ (Note 2) Max 1.5 Units V V

Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC is measured with all outputs OPEN, A = B grounded and all other inputs at 4.5V.

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DM74LS85

Switching Characteristics
at VCC = 5V and TA = 25C From Symbol Parameter Input To Output A < B, A>B A=B tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Any A or B Data Input A < B, A>B A=B A < B or A = B A < B or A = B A=B A=B A > B or A = B A > B or A = B A>B A>B A=B A=B A<B A<B Number of Gate Levels CL = 15 pF Min tPLH Propagation Delay Time LOW-to-HIGH Level Output Any A or B Data Input 3 4 3 4 1 1 2 2 1 1 Max 36 40 30 30 22 17 20 17 22 17 RL = 2 k CL = 50 pF Min Max 42 40 40 40 26 26 25 26 26 26 ns ns ns ns ns ns ns ns Units

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DM74LS85

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

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DM74LS85 4-Bit Magnitude Comparator

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

DM74LS86 Quad 2-Input Exclusive-OR Gate

August 1986 Revised March 2000

DM74LS86 Quad 2-Input Exclusive-OR Gate

General Description
This device contains four independent gates each of which performs the logic exclusive-OR function.

Ordering Code:
Order Number DM74LS86M DM74LS86SJ DM74LS86N Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Y = A B = A B + AB Inputs A L L H H
H = HIGH Logic Level L = LOW Logic Level

Output B L H L H Y L H H L

2000 Fairchild Semiconductor Corporation

DS006380

www.fairchildsemi.com

DM74LS86

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICCH ICCL Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current with Outputs HIGH Supply Current with Outputs LOW Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max, VIL = Max, VIH = Min VCC = Min, IOL = Max, VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max (Note 4) VCC = Max (Note 5) 20 6.1 9 2.7 3.4 0.35 0.25 0.5 0.4 0.2 40 0.6 100 10 15 mA A mA mA mA mA Min Typ (Note 2) Max 1.5 Units V V

Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICCH is measured with all outputs OPEN, one input at each gate at 4.5V, and the other inputs grounded. Note 5: ICCL is measured with all outputs OPEN and all inputs grounded.

Switching Characteristics
at VCC = 5V and TA = 25C RL = 2 k Symbol Parameter Conditions CL = 15 pF Min tPLH tPHL tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Other Input High Other Input Low Max 18 17 10 12 CL = 50 pF Min Max 23 21 15 15 ns ns ns ns Units

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DM74LS86

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

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DM74LS86

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

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DM74LS86 Quad 2-Input Exclusive-OR Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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DM74LS90 Decade and Binary Counters

August 1986 Revised March 2000

DM74LS90 Decade and Binary Counters

General Description
Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five for the DM74LS90. All of these counters have a gated zero reset and the DM74LS90 also has gated set-to-nine inputs for use in BCD nines complement applications. To use their maximum count length (decade or four bit binary), the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the DM74LS90 counters by connecting the QD output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA.

Features
s Typical power dissipation 45 mW s Count frequency 42 MHz

Ordering Code:
Order Number DM74LS90M DM74LS90N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Reset/Count Truth Table

Reset Inputs R0(1) H H X X L L X R0(2) H H X L X X L R9(1) L X H X L X L R9(2) X L H L X L X QD L L H Output QC L L L QB L L L QA L L H

COUNT COUNT COUNT COUNT

2000 Fairchild Semiconductor Corporation

DS006381

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DM74LS90

Function Tables
BCD Count Sequence (Note 1) Count QD 0 1 2 3 4 5 6 7 8 9 L L L L L L L L H H QC L L L L H H H H L L Output QB L L H H L L H H L L QA L H L H L H L H L H

Logic Diagram

Bi-Quinary (5-2) (Note 2) Count QA 0 1 2 3 4 5 6 7 8 9

H = HIGH Level L = LOW Level X = Dont Care Note 1: Output QA is connected to input B for BCD count. Note 2: Output QD is connected to input A for bi-quinary count. Note 3: Output QA is connected to input B. The J and K inputs shown without connection are for reference only and are functionally at a high level.

Output QD L L L L H L L L L H QC L L H H L L L H H L QB L H L H L L H L H L L L L L L H H H H H

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DM74LS90

Absolute Maximum Ratings(Note 4)

Supply Voltage Input Voltage (Reset) Input Voltage (A or B) Operating Free Air Temperature Range Storage Temperature Range 7V 7V 5.5V 0C to +70C 65C to +150C
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics table are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL fCLK fCLK tW Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 5) Clock Frequency (Note 6) Pulse Width (Note 5) A to QA B to QB A to QA B to QB A B Reset tW Pulse Width (Note 6) A B Reset tREL tREL TA Reset Release Time (Note 5) Reset Release Time (Note 6) Free Air Operating Temperature 0 0 0 0 15 30 15 25 50 25 25 35 0 70 ns ns C ns ns Parameter Min 4.75 2 0.8 0.4 8 32 16 20 10 MHz Nom 5 Max 5.25 Units V V V mA mA MHz

Note 5: CL = 15 pF, RL = 2 k, TA = 25C and VCC = 5V. Note 6: CL = 50 pF, RL = 2 k, TA = 25C and VCC = 5V.

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II Input Current @ Max Input Voltage IIH HIGH Level Input Current IIL LOW Level Input Current IOS ICC Short Circuit Output Current Supply Current VCC = Max (Note 9) VCC = Max (Note 7) VCC = Max, VI = 0.4V Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max VI = 5.5V VCC = Max, VI = 2.7V Reset A B Reset A B Reset A B 20 9 (Note 8) 2.7 3.4 Min Typ (Note 7) Max 1.5 Units V V

0.35 0.25

0.5 0.4 0.1 0.2 0.4 20 40 80 0.4 2.4 3.2 100 15

mA

mA mA mA

Note 7: All typicals are at VCC = 5V, TA = 25C.

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DM74LS90

Electrical Characteristics

(Continued)

Note 8: QA outputs are tested at IOL = Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability. Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 10: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.

Switching Characteristics at VCC = 5V and TA = 25C

From (Input) Symbol Parameter To (Output) A to QA B to QB A to QA A to QA A to QD A to QD B to QB B to QB B to QC B to QC B to QD B to QD SET-9 to QA, QD SET-9 to QB, QC SET-0 to Any Q CL = 15 pF Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Level Output 32 16 16 18 48 50 16 21 32 35 32 35 30 40 40 Max RL = 2 k CL = 50 pF Min 20 10 20 24 52 60 23 30 37 44 36 44 35 48 52 Max MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Units

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DM74LS90

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

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DM74LS90 Decade and Binary Counters

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER

The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock inputs. Each section can be used separately or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Master Set (Preset 9).

SN54/74LS90 SN54/74LS92 SN54/74LS93

DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER

LOW POWER SCHOTTKY

Low Power Consumption . . . Typically 45 mW High Count Rates . . . Typically 42 MHz Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
Binary Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES LOADING (Note a) HIGH CP0 CP1 CP1 MR1, MR2 MS1, MS2 Q0 Q1, Q2, Q3 Clock (Active LOW going edge) Input to 2 Section Clock (Active LOW going edge) Input to 5 Section (LS90), 6 Section (LS92) Clock (Active LOW going edge) Input to 8 Section (LS93) Master Reset (Clear) Inputs Master Set (Preset-9, LS90) Inputs Output from 2 Section (Notes b & c) Outputs from 5 (LS90), 6 (LS92), 8 (LS93) Sections (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. LOW 1.5 U.L.
14 14 1

J SUFFIX CERAMIC CASE 632-08

N SUFFIX PLASTIC CASE 646-06

1

2.0 U.L. 1.0 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L.

14 1

D SUFFIX SOIC CASE 751A-02

ORDERING INFORMATION
SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC

NOTES: a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74) b. Temperature Ranges. c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device. d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.

LOGIC SYMBOL LS90

6 7 1 2 MS CP0 CP1 MR Q0 Q1 Q2 Q3 1 2 2 3 12 9 8 11 VCC = PIN 5 GND = PIN 10 NC = PINS 4, 13 14 1 CP0 CP1 MR Q0 Q1 Q2 Q3 1 2 6 7 12 11 9 8 VCC = PIN 5 GND = PIN 10 NC = PINS 2, 3, 4, 13 14 1 CP0 CP1 MR Q0 Q1 Q2 Q3 1 2 2 3 12 9 8 11 VCC = PIN 5 GND = PIN 10 NC = PIN 4, 6, 7, 13

LS92

LS93

14 1

FAST AND LS TTL DATA 5-90

SN54/74LS90 SN54/74LS92 SN54/74LS93

LOGIC DIAGRAM LS90
MS1 MS2
6 7

CONNECTION DIAGRAM DIP (TOP VIEW)

CP1 1 14 CP0 13 NC 12 Q0 11 Q3 10 GND 9 Q1 8 Q2

14

S J DQ CP KC Q D

S J DQ CP KC Q D

S J DQ CP KC Q D

S R DQ CP SC Q D

MR1 2 MR2 3 NC 4 VCC 5 MS1 6

CP0

CP1 MR1 MR2

2 12 3 9 8 11

MS2 7 Q3

Q0

Q1

Q2 = PIN NUMBERS VCC = PIN 5 GND = PIN 10

NC = NO INTERNAL CONNECTION
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

LOGIC DIAGRAM LS92

CONNECTION DIAGRAM DIP (TOP VIEW)

CP1 1 14 CP0 13 NC 12 Q0 11 Q1 10 GND 9 Q2 8 Q3

CP0

14

NC 2 NC 3 NC 4 VCC 5 MR1 6

CP KC Q D
1

CP KC Q D

CP KC Q D

CP KC Q D

CP1
6

MR1 MR2

12 7

11

MR2 7 Q3

Q0

Q1

Q2

NC = NO INTERNAL CONNECTION = PIN NUMBERS VCC = PIN 5 GND = PIN 10

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

LOGIC DIAGRAM LS93

CONNECTION DIAGRAM DIP (TOP VIEW)

CP1 1 14 CP0 13 NC 12 Q0 11 Q3 10 GND 9 Q1 8 Q2

CP0

14

J CP

J CP

J CP

J CP

MR1 2 MR2 3 NC 4 VCC 5 NC 6

KC Q D
1

KC Q D

KC Q D

KC Q D

CP1 MR1 MR2

2 12 3 9 8 11

Q0

Q1

Q2

Q3 = PIN NUMBERS VCC = PIN 5 GND = PIN 10

NC 7

NC = NO INTERNAL CONNECTION
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

FAST AND LS TTL DATA 5-91

SN54/74LS90 SN54/74LS92 SN54/74LS93

FUNCTIONAL DESCRIPTION The LS90, LS92, and LS93 are 4-bit ripple type Decade, Divide-By-Twelve, and Binary Counters respectively. Each device consists of four master/slave flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight (LS93) section. Each section has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW clock transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. The Q0 output of each device is designed and specified to drive the rated fan-out plus the CP1 input of the device. A gated AND asynchronous Master Reset (MR1 MR2) is provided on all counters which overrides and clocks and resets (clears) all the flip-flops. A gated AND asynchronous Master Set (MS1 MS2) is provided on the LS90 which overrides the clocks and the MR inputs and sets the outputs to nine (HLLH). Since the output from the divide-by-two section is not internally connected to the succeeding stages, the devices may be operated in various counting modes. LS90 A. BCD Decade (8421) Counter The CP1 input must be externally connected to the Q0 output. The CP0 input receives the incoming count and a BCD count sequence is produced. B. Symmetrical Bi-quinary Divide-By-Ten Counter The Q3 output must be externally connected to the CP0 input. The input count is then applied to the CP1 input and a divide-byten square wave is obtained at output Q0. C. Divide-By-Two and Divide-By-Five Counter No external interconnections are required. The first flip-flop is used as a binary element for the divide-by-two function (CP 0 as the input and Q0 as the output). The CP1 input is used to obtain binary divide-by-five operation at the Q3 output. LS92 A. Modulo 12, Divide-By-Twelve Counter The CP1 input must be externally connected to the Q0 output. The CP0 input receives the incoming count and Q3 produces a symmetrical divide-by-twelve square wave output. B. Divide-By-Two and Divide-By-Six Counter No external interconnections are required. The first flip-flop is used as a binary element for the divide-by-two function. The CP1 input is used to obtain divide-by-three operation at the Q1 and Q2 outputs and divide-by-six operation at the Q3 output. LS93 A. 4-Bit Ripple Counter The output Q0 must be externally connected to input CP1. The input count pulses are applied to input CP0. Simultaneous divisions of 2, 4, 8, and 16 are performed at the Q0, Q1, Q2, and Q3 outputs as shown in the truth table. B. 3-Bit Ripple Counter The input count pulses are applied to input CP1. Simultaneous frequency divisions of 2, 4, and 8 are available at the Q1, Q2, and Q3 outputs. Independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter.

FAST AND LS TTL DATA 5-92

SN54/74LS90 SN54/74LS92 SN54/74LS93

LS90 MODE SELECTION
RESET / SET INPUTS MR1 MR2 MS1 MS2 H H X L X L X H H X X L X L L X H L X X L X L H X L L X Q0 L L H OUTPUTS Q1 Q2 Q3 L L H

LS92 AND LS93 MODE SELECTION

RESET INPUTS MR1 MR2 H L H L H H L L Q0 L OUTPUTS Q1 Q2 Q3 L

L L L L L L Count Count Count Count

L L Count Count Count

H = HIGH Voltage Level L = LOW Voltage Level X = Dont Care

H = HIGH Voltage Level L = LOW Voltage Level X = Dont Care

LS90 BCD COUNT SEQUENCE

OUTPUT COUNT 0 1 2 3 4 5 6 7 8 9 Q0 L H L H L H L H L H Q1 L L H H L L H H L L Q2 L L L L H H H H L L Q3 L L L L L L L L H H

LS92 TRUTH TABLE

OUTPUT COUNT 0 1 2 3 4 5 6 7 8 9 10 11 Q0 L H L H L H L H L H L H Q1 L L H H L L L L H H L L Q2 L L L L H H L L L L H H Q3 L L L L L L H H H H H H

LS93 TRUTH TABLE

OUTPUT COUNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Q0 L H L H L H L H L H L H L H L H Q1 L L H H L L H H L L H H L L H H Q2 L L L L H H H H L L L L H H H H Q3 L L L L L L L L H H H H H H H H

NOTE: Output Q0 is connected to Input CP1 for BCD count.

NOTE: Output Q0 is connected to Input CP1.

NOTE: Output Q0 is connected to Input CP1.

FAST AND LS TTL DATA 5-93

SN54/74LS90 SN54/74LS92 SN54/74LS93

GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 0.4 4.0 8.0 Unit V C mA mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current MS, MR CP0 CP1 (LS90, LS92) CP1 (LS93) Short Circuit Current (Note 1) Power Supply Current 20 0.4 2.4 3.2 1.6 100 15 0.35 0.5 20 IIH V A mA 2.7 3.5 0.25 0.4 V V 2.5 0.65 3.5 0.8 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V

IIL

mA

VCC = MAX, VIN = 0.4 V

IOS ICC

mA mA

VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA 5-94

SN54/74LS90 SN54/74LS92 SN54/74LS93

AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V, CL = 15 pF)
Limits LS90 Symbol fMAX fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter CP0 Input Clock Frequency CP1 Input Clock Frequency Propagation Delay, CP0 Input to Q0 Output CP0 Input to Q3 Output CP1 Input to Q1 Output CP1 Input to Q2 Output CP1 Input to Q3 Output MS Input to Q0 and Q3 Outputs MS Input to Q1 and Q2 Outputs MR Input to Any Output Min 32 16 10 12 32 34 10 14 21 23 21 23 20 26 26 16 18 48 50 16 21 32 35 32 35 30 40 40 26 40 26 40 Typ Max Min 32 16 10 12 32 34 10 14 10 14 21 23 16 18 48 50 16 21 16 21 32 35 LS92 Typ Max Min 32 16 10 12 46 46 10 14 21 23 34 34 16 18 70 70 16 21 32 35 51 51 LS93 Typ Max Unit MHz MHz ns ns ns ns ns ns ns ns

AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)

Limits LS90 Symbol tW tW tW tW trec Parameter CP0 Pulse Width CP1 Pulse Width MS Pulse Width MR Pulse Width Recovery Time MR to CP Min 15 30 15 15 25 15 25 15 25 Max Min 15 30 LS92 Max Min 15 30 LS93 Max Unit ns ns ns ns ns

RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from HIGH-to-LOW in order to recognize and transfer HIGH data to the Q outputs

AC WAVEFORMS
*CP 1.3 V tPHL Q 1.3 V 1.3 V tW 1.3 V tPLH 1.3 V

Figure 1
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.

MR & MS

1.3 V tW

1.3 V trec 1.3 V

MS

1.3 V tW

1.3 V trec 1.3 V

CP tPHL Q 1.3 V

CP Q0 Q3 (LS90) tPLH 1.3 V

Figure 2

Figure 3

FAST AND LS TTL DATA 5-95

SN54/74LS95B 4-BIT SHIFT REGISTER

The SN54/74LS95B is a 4-Bit Shift Register with serial and parallel synchronous operating modes. The serial shift right and parallel load are activated by separate clock inputs which are selected by a mode control input. The data is transferred from the serial or parallel D inputs to the Q outputs synchronous with the HIGH to LOW transition of the appropriate clock input. The LS95B is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.

4-BIT SHIFT REGISTER

LOW POWER SCHOTTKY

Synchronous, Expandable Shift Right Synchronous Shift Left Capability Synchronous Parallel Load Separate Shift and Load Clock Inputs Input Clamp Diodes Limit High Speed Termination Effects
14 1

J SUFFIX CERAMIC CASE 632-08

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC 14 Q0 13 Q1 12 Q2 11 Q3 10 CP1 9 CP2 8
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

14 1

N SUFFIX PLASTIC CASE 646-06

VCC = PIN 14 GND = PIN 7 1 DS 2 P0 3 P1 4 P2 5 P3 6 S 7 GND

14 1

D SUFFIX SOIC CASE 751A-02

PIN NAMES

LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L.

ORDERING INFORMATION
SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC

S DS P0 P3 CP1 CP2 Q0 Q3

Mode Control Input Serial Data Input Parallel Data Inputs Serial Clock (Active LOW Going Edge) Input Parallel Clock (Active LOW Going Edge) Input Parallel Outputs (Note b)

0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L.

NOTES: a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.

GUARANTEED OPERATING RANGES

Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 0.4 4.0 8.0 Unit V C mA mA

FAST AND LS TTL DATA 5-171

SN54/74LS95B
LOGIC DIAGRAM
P0 S DS
6 1 2

P1
3

P2
4

P3
5

CP1 CP2

S VCC = PIN 14 GND = PIN 7 = PIN NUMBERS

Q
13

Q
12

Q
11

Q
10

Q0

Q1

Q2

Q3

FUNCTIONAL DESCRIPTION The LS95B is a 4-Bit Shift Register with serial and parallel synchronous operating modes. It has a Serial (DS) and four Parallel (P 0 P3) Data inputs and four Parallel Data outputs (Q0 Q3). The serial or parallel mode of operation is controlled by a Mode Control input (S) and two Clock Inputs (CP1) and (CP2). The serial (right-shift) or parallel data transfers occur synchronous with the HIGH to LOW transition of the selected clock input. When the Mode Control input (S) is HIGH, CP2 is enabled. A HIGH to LOW transition on enabled CP2 transfers parallel data from the P0 P3 inputs to the Q0 Q3 outputs. When the Mode Control input (S) is LOW, CP1 is enabled. A HIGH to LOW transition on enabled CP1 transfers the data from Serial input (DS) to Q0 and shifts the data in Q0 to Q1, Q1 to Q2, and Q2 to Q3 respectively (right-shift). A left-shift is accomplished by externally connecting Q3 to P2, Q2 to P1, and Q1 to P0, and operating the LS95B in the parallel mode (S = HIGH). For normal operation, S should only change states when both Clock inputs are LOW. However, changing S from LOW to HIGH while CP2 is HIGH, or changing S from HIGH to LOW while CP1 is HIGH and CP2 is LOW will not cause any changes on the register outputs.

MODE SELECT TRUTH TABLE

INPUTS OPERATING MODE S Shift Parallel Load L L H X L L H H L L H H L L L L H H H H CP1 CP2 X X DS I h X X X X X X X X X Pn X X Pn X X X X X X X X Q0 L H P0 Q1 q0 q0 P1 Q2 q1 q1 P2 Q3 q2 q2 P3 OUTPUTS

Mode Change

No Change No Change No Change Undetermined Undetermined No Change Undetermined No Change

L = LOW Voltage Level H = HIGH Voltage Level X = Dont Care I = LOW Voltage Level one set-up time prior to the HIGH to LOW clock transition. h = HIGH Voltage Level one set-up time prior to the HIGH to LOW clock transition. Pn = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the Pn = HIGH to LOW clock transition.

FAST AND LS TTL DATA 5-172

SN54/74LS95B
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input HIGH Current Short Circuit Current (Note 1) Power Supply Current 20 0.4 100 21 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 0.65 3.5 0.8 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)

Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency CP to Output 21 32 ns Min 25 Typ 36 18 27 Max Unit MHz ns VCC = 5.0 V CL = 15 pF Test Conditions

AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)

Limits Symbol tW ts th ts th CP Pulse Width Data Setup Time Data Hold Time Mode Control Setup Time Mode Control Hold Time Parameter Min 20 20 20 20 20 Typ Max Unit ns ns ns ns ns VCC = 5.0 V Test Conditions

FAST AND LS TTL DATA 5-173

SN54/74LS95B
DESCRIPTION OF TERMS SETUP TIME(ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from HIGH to LOW in order to be recognized and transferred to the outputs. HOLD TIME (th) is defined as the minimum time following the clock transition from HIGH to LOW that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from HIGH to LOW and still be recognized.

AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.

1.3 V

1.3 V

1.3 V

1.3 V

th(L) ts(L) ts(H)

th(H)

CP1 or CP2

1.3 V

1.3 V tW l/fmax

1.3 V

*The Data Input is (DS for CP1) or (Pn for CP2).

tPHL

tPLH

1.3 V

1.3 V

Figure 1

(H

L ONLY)

(L

H ONLY)

(L

H ONLY)

1.3 V

1.3 V

STABLE

ts(H)

ts(L) th(L) ts(L)

ts(H) th(LORH)

CP1

1.3 V

1.3 V

1.3 V

1.3 V

tW

ts(L)

ts(H) th(H) 1.3 V 1.3 V 1.3 V 1.3 V

CP2

tW

Figure 2

FAST AND LS TTL DATA 5-174

Case 751A-02 D Suffix 14-Pin Plastic SO-14 -A14 8

NOTES: 1. DIMENSIONS A" AND B" ARE DATUMS AND T" IS A DATUM SURFACE. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. 4. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 6. 751A01 IS OBSOLETE, NEW STANDARD 751A02.

-B1 7

P
7 PL

0.25 (0.010)

C
SEATING PLANE

R X 45

D 14 PL
0.25 (0.010)
M

K
T B
S

DIM A B C D F G J K M P R

MILLIMETERS MIN MAX

8.55 3.80 1.35 0.35 0.40 8.75 4.00 1.75 0.49 1.25

INCHES MIN MAX

0.337 0.150 0.054 0.014 0.016 0.344 0.157 0.068 0.019 0.049

1.27 BSC 0.19 0.10 0 5.80 0.25 0.25 0.25 7 6.20 0.50

0.050 BSC 0.008 0.004 0 0.229 0.010 0.009 0.009 7 0.244 0.019

Case 632-08 J Suffix 14-Pin Ceramic Dual In-Line -A14 8

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH.

-B1 7

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. 5. 63201 THRU 07 OBSOLETE, NEW STANDARD

63208.

-TSEATING PLANE

K F D 14 PL
0.25 (0.010)
M

G
T A
S

N J 14 PL

0.25 (0.010)

DIM A B C D F G J K L M N

MILLIMETERS MIN MAX

19.05 6.23 3.94 0.39 1.40 19.94 7.11 5.08 0.50 1.65

INCHES MIN MAX

0.750 0.245 0.155 0.015 0.055 0.785 0.280 0.200 0.020 0.065

2.54 BSC 0.21 3.18 0.38 4.31

0.100 BSC 0.008 0.125 0.015 0.170

7.62 BSC 0 0.51

15 1.01

0.300 BSC 0 0.020

15 0.040

Case 646-06 N Suffix 14-Pin Plastic

NOTES: 1. LEADS WITHIN 0.13 mm (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION.

14

B
1 7

2.

DIMENSION L" TO CENTER OF LEADS WHEN FORMED PARALLEL.

3.

DIMENSION B" DOES NOT INCLUDE MOLD FLASH.

4. 5.

ROUNDED CORNERS OPTIONAL. 64605 OBSOLETE, NEW STANDARD 64606.

A F C N H G D
SEATING PLANE

NOTE 4

J K M

DIM A B C D F G H J K L M N

MILLIMETERS MIN MAX

18.16 6.10 3.69 0.38 1.02 19.56 6.60 4.69 0.53 1.78

INCHES MIN MAX

0.715 0.240 0.145 0.015 0.040 0.770 0.260 0.185 0.021 0.070

2.54 BSC 1.32 0.20 2.92 2.41 0.38 3.43

0.100 BSC 0.052 0.008 0.115 0.095 0.015 0.135

7.62 BSC 0

10

0.300 BSC 0

10

0.39

1.01

0.015

0.039

FAST AND LS TTL DATA 5-175

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

FAST AND LS TTL DATA 5-176

DM74LS138 DM74LS139 Decoder/Demultiplexer

August 1986 Revised March 2000

DM74LS138 DM74LS139 Decoder/Demultiplexer

General Description
These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The DM74LS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The DM74LS139 comprises two separate two-line-to-fourline decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design.

Features
s Designed specifically for high speed: Memory decoders Data transmission systems s DM74LS138 3-to-8-line decoders incorporates 3 enable inputs to simplify cascading and/or data reception s DM74LS139 contains two fully independent 2-to-4-line decoders/demultiplexers s Schottky clamped for high performance s Typical propagation delay (3 levels of logic) DM74LS138 DM74LS139 DM74LS138 DM74LS139 21 ns 21 ns 32 mW 34 mW

s Typical power dissipation

Ordering Code:
Order Number DM74LS138M DM74LS138SJ DM74LS138N DM74LS139M DM74LS139SJ DM74LS139N Package Number M16A M16D N16E M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

2000 Fairchild Semiconductor Corporation

DS006391

www.fairchildsemi.com

DM74LS138 DM74LS139

Connection Diagrams
DM74LS138 DM74LS139

Function Tables
DM74LS138 Inputs Enable X L H H H H H H H H H X L L L L L L L L Select X X X X X X L L L L L H L H L L H H H L L H L H H H L H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H Outputs Inputs Enable G H L L L L H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L
H = HIGH Level L = LOW Level X = Dont Care Note 1: G2 = G2A + G2B

DM74LS139 Outputs Y0 H L H H H Y1 H H L H H Y2 H H H L H Y3 H H H H L

Select B X L L H H A X L H L H

G1 G2 (Note 1) C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7 H H H H H L H H H H H H H H H H L H H H

Logic Diagrams
DM74LS138 DM74LS139

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DM74LS138 DM74LS139

Absolute Maximum Ratings(Note 2)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

DM74LS138 Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

DM74LS138 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOS ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max, VIL = Max, VIH = Min VCC = Min, IOL = Max, VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 4) VCC = Max (Note 5) 20 6.3 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 0.36 100 10 Min Typ (Note 3) Max 1.5 Units V V V mA A mA mA mA

Note 3: All typicals are at VCC = 5V, TA = 25C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 5: ICC is measured with all outputs enabled and OPEN.

DM74LS138 Switching Characteristics

at VCC = 5V and TA = 25C From (Input) Symbol Parameter To (Output) Levels of Delay CL = 15 pF Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Select to Output Select to Output Select to Output Select to Output Enable to Output Enable to Output Enable to Output Enable to Output 2 2 3 3 2 2 3 3 Max 18 27 18 27 18 24 18 28 RL = 2 k CL = 50 pF Min Max 27 40 27 40 27 40 27 40 ns ns ns ns ns ns ns ns Units

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DM74LS138 DM74LS139

DM74LS139 Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

DM74LS139 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max, VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 7) VCC = Max (Note 8) 20 6.8 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 0.36 100 11 mA A mA mA mA Min Typ (Note 6) Max 1.5 Units V V

Note 6: All typicals are at VCC = 5V, TA = 25C. Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 8: ICC is measured with all outputs enabled and OPEN.

DM74LS139 Switching Characteristics

at VCC = 5V and TA = 25C From (Input) Symbol Parameter To (Output) CL = 15 pF Min tPLH tPHL tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Select to Output Select to Output Enable to Output Enable to Output Max 18 27 18 24 RL = 2 k CL = 50 pF Min Max 27 40 27 40 ns ns ns ns Units

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DM74LS138 DM74LS139

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

www.fairchildsemi.com

DM74LS138 DM74LS139

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

www.fairchildsemi.com

DM74LS138 DM74LS139 Decoder/Demultiplexer

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

www.fairchildsemi.com

DM74LS138 DM74LS139 Decoder/Demultiplexer

August 1986 Revised March 2000

DM74LS138 DM74LS139 Decoder/Demultiplexer

General Description
These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The DM74LS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The DM74LS139 comprises two separate two-line-to-fourline decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design.

Features
s Designed specifically for high speed: Memory decoders Data transmission systems s DM74LS138 3-to-8-line decoders incorporates 3 enable inputs to simplify cascading and/or data reception s DM74LS139 contains two fully independent 2-to-4-line decoders/demultiplexers s Schottky clamped for high performance s Typical propagation delay (3 levels of logic) DM74LS138 DM74LS139 DM74LS138 DM74LS139 21 ns 21 ns 32 mW 34 mW

s Typical power dissipation

Ordering Code:
Order Number DM74LS138M DM74LS138SJ DM74LS138N DM74LS139M DM74LS139SJ DM74LS139N Package Number M16A M16D N16E M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

2000 Fairchild Semiconductor Corporation

DS006391

www.fairchildsemi.com

DM74LS138 DM74LS139

Connection Diagrams
DM74LS138 DM74LS139

Function Tables
DM74LS138 Inputs Enable X L H H H H H H H H H X L L L L L L L L Select X X X X X X L L L L L H L H L L H H H L L H L H H H L H H H H H L H H H H H H H H H H L H H H H H H H H H H L H H H H H Outputs Inputs Enable G H L L L L H H H H H H H L H H H H H H H H H H L H H H H H H H H H H L
H = HIGH Level L = LOW Level X = Dont Care Note 1: G2 = G2A + G2B

DM74LS139 Outputs Y0 H L H H H Y1 H H L H H Y2 H H H L H Y3 H H H H L

Select B X L L H H A X L H L H

G1 G2 (Note 1) C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7 H H H H H L H H H H H H H H H H L H H H

Logic Diagrams
DM74LS138 DM74LS139

www.fairchildsemi.com

DM74LS138 DM74LS139

Absolute Maximum Ratings(Note 2)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

DM74LS138 Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

DM74LS138 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOS ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max, VIL = Max, VIH = Min VCC = Min, IOL = Max, VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 4) VCC = Max (Note 5) 20 6.3 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 0.36 100 10 Min Typ (Note 3) Max 1.5 Units V V V mA A mA mA mA

Note 3: All typicals are at VCC = 5V, TA = 25C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 5: ICC is measured with all outputs enabled and OPEN.

DM74LS138 Switching Characteristics

at VCC = 5V and TA = 25C From (Input) Symbol Parameter To (Output) Levels of Delay CL = 15 pF Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Select to Output Select to Output Select to Output Select to Output Enable to Output Enable to Output Enable to Output Enable to Output 2 2 3 3 2 2 3 3 Max 18 27 18 27 18 24 18 28 RL = 2 k CL = 50 pF Min Max 27 40 27 40 27 40 27 40 ns ns ns ns ns ns ns ns Units

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DM74LS138 DM74LS139

DM74LS139 Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

DM74LS139 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max, VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 7) VCC = Max (Note 8) 20 6.8 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 0.36 100 11 mA A mA mA mA Min Typ (Note 6) Max 1.5 Units V V

Note 6: All typicals are at VCC = 5V, TA = 25C. Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 8: ICC is measured with all outputs enabled and OPEN.

DM74LS139 Switching Characteristics

at VCC = 5V and TA = 25C From (Input) Symbol Parameter To (Output) CL = 15 pF Min tPLH tPHL tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Select to Output Select to Output Enable to Output Enable to Output Max 18 27 18 24 RL = 2 k CL = 50 pF Min Max 27 40 27 40 ns ns ns ns Units

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DM74LS138 DM74LS139

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

www.fairchildsemi.com

DM74LS138 DM74LS139

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

www.fairchildsemi.com

DM74LS138 DM74LS139 Decoder/Demultiplexer

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

www.fairchildsemi.com

10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS

The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are active at the low logic level. The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a high logic level. The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By providing cascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allowed without needing external circuitry. The SN54 / 74LS748 is a proprietary Motorola part incorporating a built-in deglitcher network which minimizes glitches on the GS output. The glitch occurs on the negative going transition of the EI input when data inputs 0 7 are at logical ones. The only dc parameter differences between the LS148 and the LS748 are that (1) Pin 10 (input 0) has a fan-in of 2 on the LS748 versus a fan-in of 1 on the LS148; (2) Pins 1, 2, 3, 4, 11, 12 and 13 (inputs 1, 2, 3, 4, 5, 6, 7) have a fan-in of 3 on the LS748 versus a fan-in of 2 on the LS148. The only ac difference is that tPHL from EI to EO is changed from 40 to 45 ns. SN54 / 74LS147 (TOP VIEW)
OUTPUT VCC 16 NC 15 D 14 D 4 5 1 4 2 5 6 3 6 7 4 7 8 5 8 C 6 C B 7 B 8 GND 3 13 3 INPUTS 2 12 2 1 11 1 9 10 9 A OUTPUT A 9

SN54/74LS147 SN54/74LS148 SN54/74LS748

10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS

LOW POWER SCHOTTKY

J SUFFIX CERAMIC CASE 620-09

16 1

16 1

N SUFFIX PLASTIC CASE 648-08

16 1

D SUFFIX SOIC CASE 751B-03

ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

INPUTS

OUTPUTS

SN54 / 74LS148 SN54 / 74LS748 (TOP VIEW)

OUTPUTS VCC 16 EO 15 EO 4 5 1 4 2 5 6 3 6 INPUTS 7 4 7 EI 5 E1 A2 6 A2 GS 14 GS 3 13 3 INPUTS 2 12 2 1 11 1 0 10 0 A0 A1 7 A1 8 GND OUTPUT A0 9

OUTPUTS

FAST AND LS TTL DATA 5-245

SN54/74LS147 SN54/74LS148 SN54/74LS748

SN54 / 74LS148 SN54 / 74LS748 FUNCTION TABLE
OUTPUTS 6 H X X X L H H H H H 7 H X X L H H H H H H 8 H X L H H H H H H H 9 H L H H H H H H H H D H L L H H H H H H H C H H H L L L L H H H B H H H L L H H L L H A H L H L H L H L H L EI H L L L L L L L L L 0 X H X X X X X X X L 1 X H X X X X X X L H INPUTS 2 X H X X X X X L H H 3 X H X X X X L H H H 4 X H X X X L H H H H 5 X H X X L H H H H H 6 X H X L H H H H H H 7 X H L H H H H H H H A2 H H L L L L H H H H OUTPUTS A1 H H L L H H L L H H A0 H H L H L H L H L H GS H H L L L L L L L L EO H L H H H H H H H H

SN54 / 74LS147 FUNCTION TABLE

INPUTS 1 H X X X X X X X X L 2 H X X X X X X X L H 3 H X X X X X X L H H 4 H X X X X X L H H H 5 H X X X X L H H H H

H = HIGH Logic Level, L = LOW Logic Level, X = Irrelevant

FUNCTIONAL BLOCK DIAGRAMS

(11) 0

(10) (15) EO

(12) 2 (9) A 1

(11)

(14) GS

(13) 3 2

(12) (8) A0

(1) 4 (7) 5 (2) 3

(13)

B 4

(1)

(3) 6 5

(2)

(7) A1

(4)

(6) C

(3) 6

(5) 7

(4)

(6) A2

(10)

(14)

(5) EI

SN54 / 74LS147

SN54 / 74LS148

FAST AND LS TTL DATA 5-246

SN54/74LS147 SN54/74LS148 SN54/74LS748

FUNCTIONAL BLOCK DIAGRAMS (continued)

G31

(10) 0

G13

(15) EO

(11) 1 G2 (12) 2 G3 (13) 3 G4 4 (1) G5 (2) 5 G6 (3) G7 (4) 7 G8 (5) EI G1 G28 G12 G11 G23 G10 G18 G9 G29

(14) GS

(9) A0

(7)

A1

(6) A2

SN54 / 74LS748

FAST AND LS TTL DATA 5-247

SN54/74LS147 SN54/74LS148 SN54/74LS748

GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 0.4 4.0 8.0 Unit V C mA mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current All Others Input 0 (LS748) Inputs 1 7 (LS148) Inputs 1 7 (LS748) All Others Input 0 (LS748) Inputs 1 7 (LS148) Inputs 1 7 (LS748) Input LOW Current All Others Input 0 (LS748) Inputs 1 7 (LS148) Inputs 1 7 (LS748) Short Circuit Current (Note 1) Power Supply Current Output HIGH Output LOW 20 0.35 0.5 20 40 40 60 0.1 0.2 0.2 0.3 0.4 0.8 0.8 1.2 100 17 20 V 2.7 3.5 0.25 0.4 V V 2.5 0.65 3.5 0.8 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V

IIH

mA

VCC = MAX, VIN = 7.0 V

IIL

mA

VCC = MAX, VIN = 0.4 V

IOS ICCH ICCL

mA mA mA

VCC = MAX VCC = MAX, All Inputs = 4.5 V VCC = MAX, Inputs 7 & E1 = GND All Other Inputs = 4.5 V

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA 5-248

SN54/74LS147 SN54/74LS148 SN54/74LS748

AC CHARACTERISTICS (VCC = 5.0 V, TA = 25C) SN54 / 74LS147

Symbol tPLH tPHL tPLH tPHL Any Any From (Input) Any To (Output) Any Limits Waveform In-phase output Out-of-phase output Min Typ 12 12 21 15 Max 18 ns 18 33 ns 23 CL = 15 pF, RL = 2.0 k Unit Test Conditions

SN54 / 74LS148 SN54 / 74LS748

Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL EI EO EI GS EI A0, A1, or A2 0 thru 7 GS 0 thru 7 EO 1 thru 7 A0, A1, or A2 From (Input) 1 thru 7 To (Output) A0, A1, or A2 Limits Waveform In-phase output Out-of-phase output Out-of-phase output In-phase output In-phase output In-phase output In-phase output Min Typ 14 15 20 16 7.0 25 35 9.0 16 12 12 14 12 28 30 Max 18 ns 25 36 ns 29 18 ns 40 55 ns 21 25 ns 25 17 ns 36 21 40 45 ns (LS148) (LS748) CL = 15 pF, RL = 2.0 k Unit Test Conditions

FAST AND LS TTL DATA 5-249

-A-

Case 751B-03 D Suffix 16-Pin Plastic SO-16

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751B01 IS OBSOLETE, NEW STANDARD 751B03.

16

-B1 8

P
8 PL

0.25 (0.010)

R X 45 G -TD 16 PL
0.25 (0.010)
M

C
SEATING PLANE

K
T B
S

DIM A B C D F G J K M P R

MILLIMETERS MIN MAX

9.80 3.80 1.35 0.35 0.40 10.00 4.00 1.75 0.49 1.25

INCHES MIN MAX

0.386 0.150 0.054 0.014 0.016 0.393 0.157 0.068 0.019 0.049

1.27 BSC 0.19 0.10 0 5.80 0.25 0.25 0.25 7 6.20 0.50

0.050 BSC 0.008 0.004 0 0.229 0.010 0.009 0.009 7 0.244 0.019

Case 648-08 N Suffix 16-Pin Plastic -A16 9

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B" DOES NOT INCLUDE MOLD FLASH. 5. 6. ROUNDED CORNERS OPTIONAL. 64801 THRU 07 OBSOLETE, NEW STANDARD 64808.

B
1 8

F S

C -TK
SEATING PLANE

H G D 16 PL
0.25 (0.010)
M

DIM A B C D F G H J K L M S

MILLIMETERS MIN MAX

18.80 6.35 3.69 0.39 1.02 19.55 6.85 4.44 0.53 1.77

INCHES MIN MAX

0.740 0.250 0.145 0.015 0.040 0.770 0.270 0.175 0.021 0.070

2.54 BSC 1.27 BSC 0.21 2.80 7.50 0 0.38 3.30 7.74 10

0.100 BSC 0.050 BSC 0.008 0.110 0.295 0 0.015 0.130 0.305 10

0.51

1.01

0.020

0.040

-A16 9

Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH.

-B1 8

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

5. 62001 THRU 08 OBSOLETE, NEW STANDARD 62009.

-TSEATING PLANE

K E F D 16 PL
0.25 (0.010)
M

N G
T A
S

M J 16 PL
0.25 (0.010)
M

DIM A B C D E F G J K L M N

MILLIMETERS MIN MAX

19.05 6.10 0.39 19.55 7.36 4.19 0.53

INCHES MIN MAX

0.750 0.240 0.015 0.770 0.290 0.165 0.021

1.27 BSC 1.40 1.77

0.050 BSC 0.055 0.070

2.54 BSC 0.23 0.27 5.08

0.100 BSC 0.009 0.011 0.200

7.62 BSC 0

15

0.300 BSC 0

15

0.39

0.88

0.015

0.035

FAST AND LS TTL DATA 5-250

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

FAST AND LS TTL DATA 5-251

DM74LS151 1-of-8 Line Data Selector/Multiplexer

August 1986 Revised March 2000

DM74LS151 1-of-8 Line Data Selector/Multiplexer

General Description
This data selector/multiplexer contains full on-chip decoding to select the desired data source. The DM74LS151 selects one-of-eight data sources. The DM74LS151 has a strobe input which must be at a low logic level to enable these devices. A high level at the strobe forces the W output HIGH, and the Y output LOW. The DM74LS151 features complementary W and Y outputs.

Features
s Select one-of-eight data lines s Performs parallel-to-serial conversion s Permits multiplexing from N lines to one line s Also for use as Boolean function generator s Typical average propagation delay time data input to W output 12.5 ns s Typical power dissipation 30 mW

Ordering Code:
Order Number DM74LS151M DM74LS151SJ DM74LS151N Package Number M16A M16D N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Truth Table
Inputs Select C X L L L L H H H H B X L L H H L L H H A X L H L H L H L H Strobe S H L L L L L L L L Outputs Y L D0 D1 D2 D3 D4 D5 D6 D7 W H D0 D1 D2 D3 D4 D5 D6 D7

H = HIGH Level L = LOW Level X = Don't Care D0, D1...D7 = the level of the respective D input

2000 Fairchild Semiconductor Corporation

DS006392

www.fairchildsemi.com

DM74LS151

Logic Diagrams

See Address Buffers

Address Buffers

www.fairchildsemi.com

DM74LS151

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max (Note 4) 20 6 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 0.4 100 10 mA A mA mA mA Min Typ (Note 2) Max 1.5 Units V V

Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC is measured with all outputs OPEN, strobe and data select inputs at 4.5V, and all other inputs OPEN.

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DM74LS151

Switching Characteristics
at VCC = 5V and TA = 25C From (Input) Symbol Parameter To (output) Select (4 Levels) to Y Select (4 Levels) to Y Select (3 Levels) to W Select (3 Levels) to W Strobe to Y Strobe to Y Strobe to W Strobe to W D0 thru D7 to Y D0 thru D7 to Y D0 thru D7 to W D0 thru D7 to W CL = 15 pF Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Max 43 30 23 32 42 32 24 30 32 26 21 20 RL = 2 k CL = 50 pF Min Max 46 36 25 40 44 40 27 36 35 33 25 27 ns ns ns ns ns ns ns ns ns ns ns ns Units

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DM74LS151

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

www.fairchildsemi.com

DM74LS151

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

www.fairchildsemi.com

DM74LS151 1-of-8 Line Data Selector/Multiplexer

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

www.fairchildsemi.com

DM74LS153 Dual 1-of-4 Line Data Selectors/Multiplexers

August 1986 Revised March 2000

DM74LS153 Dual 1-of-4 Line Data Selectors/Multiplexers

General Description
Each of these data selectors/multiplexers contains inverters and drivers to supply fully complementary, on-chip, binary decoding data selection to the AND-OR-invert gates. Separate strobe inputs are provided for each of the two four-line sections.

Features
s Permits multiplexing from N lines to 1 line s Performs at parallel-to-serial conversion s Strobe (enable) line provided for cascading (N lines to n lines) s High fan-out, low impedance, totem pole outputs s Typical average propagation delay times From data From strobe From select 14 ns 19 ns 22 ns

s Typical power dissipation 31 mW

Ordering Code:
Order Number DM74LS153M DM74LS153N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Function Table
Select Inputs B X L L L L H H H H A X L L H H L L H H C0 X L H X X X X X X Data Inputs C1 X X X L H X X X X C2 X X X X X L H X X C3 X X X X X X X L H Strobe G H L L L L L L L L Output Y L L H L H L H L H

Select inputs A and B are common to both sections. H = HIGH Level L = LOW Level X = Don't Care

2000 Fairchild Semiconductor Corporation

DS006393

www.fairchildsemi.com

DM74LS153

Logic Diagram

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DM74LS153

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150 C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max (Note 4) 20 6.2 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 0.36 100 10 mA A mA mA mA Min Typ (Note 2) Max 1.5 Units V V

Note 2: All typicals are at VCC = 5V, TA = 25 C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC is measured with all outputs OPEN and all other inputs GROUNDED.

Switching Characteristics
at VCC = 5V and TA = 25C From (Input) Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output to (Output) CL = 15 pF Min Data to Y Data to Y Select to Y Select to Y Strobe to Y Strobe to Y Max 15 26 29 38 24 32 RL = 2 k CL = 50 pF Min Max 20 35 35 45 30 40 ns ns ns ns ns ns Units

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DM74LS153

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

www.fairchildsemi.com

DM74LS153 Dual 1-of-4 Line Data Selectors/Multiplexers

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

www.fairchildsemi.com

DM74LS154 4-Line to 16-Line Decoder/Demultiplexer

August 1986 Revised March 2000

DM74LS154 4-Line to 16-Line Decoder/Demultiplexer

General Description
Each of these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G1 and G2, are LOW. The demultiplexing function is performed by using the 4 input lines to address the output line, passing data from one of the strobe inputs with the other strobe input LOW. When either strobe input is HIGH, all outputs are HIGH. These demultiplexers are ideally suited for implementing high-performance memory decoders. All inputs are buffered and input clamping diodes are provided to minimize transmission-line effects and thereby simplify system design.

Features
s Decodes 4 binary-coded inputs into one of 16 mutually exclusive outputs s Performs the demultiplexing function by distributing data from one input line to any one of 16 outputs s Input clamping diodes simplify system design s High fan-out, low-impedance, totem-pole outputs s Typical propagation delay 3 levels of logic Strobe 23 ns 19 ns

s Typical power dissipation 45 mW

Ordering Code:
Order Number DM74LS154WM DM74LS154N Package Number M24B N24A Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Logic Diagram

2000 Fairchild Semiconductor Corporation

DS006394

www.fairchildsemi.com

DM74LS154

Function Table
Inputs G1 L L L L L L L L L L L L L L L L L H H G2 L L L L L L L L L L L L L L L L H L H D L L L L L L L L H H H H H H H H X X X C L L L L H H H H L L L L H H H H X X X B L L H H L L H H L L H H L L H H X X X A L H L H L H L H L H L H L H L H X X X 0 L H H H H H H H H H H H H H H H H H H 1 H L H H H H H H H H H H H H H H H H H 2 H H L H H H H H H H H H H H H H H H H 3 H H H L H H H H H H H H H H H H H H H 4 H H H H L H H H H H H H H H H H H H H 5 H H H H H L H H H H H H H H H H H H H 6 H H H H H H L H H H H H H H H H H H H 7 H H H H H H H L H H H H H H H H H H H Outputs 8 H H H H H H H H L H H H H H H H H H H 9 H H H H H H H H H L H H H H H H H H H 10 H H H H H H H H H H L H H H H H H H H 11 H H H H H H H H H H H L H H H H H H H 12 H H H H H H H H H H H H L H H H H H H 13 H H H H H H H H H H H H H L H H H H H 14 H H H H H H H H H H H H H H L H H H H 15 H H H H H H H H H H H H H H H L H H H

H = HIGH Level L = Low Level X = Dont Care

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DM74LS154

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 0.4 8 70 Nom 5 Max 5.25 Units V V V mA mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max (Note 4) 20 9 2.7 3.4 0.25 0.35 0.25 0.4 0.5 0.4 0.1 20 0.4 100 14 mA A mA mA mA V Min Typ (Note 2) Max 1.5 Units V V

Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC is measured with all outputs OPEN and all inputs GROUNDED.

Switching Characteristics
at VCC = 5V and TA = 25C From (Input) Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output To (Output) CL = 15 pF Min Data to Output Data to Output Strobe to Output Strobe to Output Max 30 30 20 25 RL = 2 k CL = 50 pF Min Max 35 35 25 35 ns ns ns ns Units

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DM74LS154

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B

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DM74LS154 4-Line to 16-Line Decoder/Demultiplexer

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Package Number N24A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

www.fairchildsemi.com

DM74LS266 Quad 2-Input Exclusive-NOR Gate

March 1989 Revised March 2000

DM74LS266 Quad 2-Input Exclusive-NOR Gate with Open-Collector Outputs

General Description
This device contains four independent gates each of which performs the logic exclusive-NOR function. Outputs are open collector.

Ordering Code:
Order Number DM74LS266M DM74LS266N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Truth Table
Inputs A L L H H
H = HIGH Voltage Level L = LOW Voltage Level

Outputs B L H L H Y H L L H

2000 Fairchild Semiconductor Corporation

DS010182

www.fairchildsemi.com

DM74LS266

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C 65C to +150C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics table are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol VCC VIH VIL VOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 5.5 8 70 Nom 5 Max 5.25 Units V V V V mA C

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI ICEX VOL Parameter Input Clamp Voltage HIGH Level Output Current LOW Level Output Voltage II IIH IIL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, VO = 5.5V, VIL = Max VCC = Min, IOL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max 20 Min Typ (Note 2) Max 1.5 100 0.5 0.4 0.2 40 0.8 100 13 mA A mA mA mA Units V A

Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteristics
VCC = 5V, TA = 25C RL = 2 k Symbol Parameter Min tPLH tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output CL = 15 pF Max 23 23 ns ns Units

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DM74LS266

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

www.fairchildsemi.com

DM74LS266 Quad 2-Input Exclusive-NOR Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 4 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

DM74LS373 DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

April 1986 Revised March 2000

DM74LS373 DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
General Description
These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the DM74LS373 are transparent Dtype latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74LS374 are edge-triggered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.

Features
s Choice of 8 latches or 8 D-type flip-flops in a single package s 3-STATE bus-driving outputs s Full parallel-access for loading s Buffered control inputs s P-N-P inputs reduce D-C loading on data lines

Ordering Code:
Order Number DM74LS373WM DM74LS373SJ DM74LS373N DM74LS374WM DM74LS374SJ IDM29901NC Package Number M20B M20D N20A M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

2000 Fairchild Semiconductor Corporation

DS006431

www.fairchildsemi.com

DM74LS373 DM74LS374

Connection Diagrams
DM74LS373 DM74LS374

Function Tables
DM74LS373 Output Control L L L H
H = HIGH Level (Steady State)

DM74LS374 D H L X X Output H L Q0 Z
X = Dont Care

Enable G H H L X

Output Control L L L H

Clock L X

D H L X X

Output H L Q0 Z

L = LOW Level (Steady State)

Z = High Impedance State

= Transition from LOW-to-HIGH level

Q0 = The level of the output before steady-state input conditions were established.

Logic Diagrams
DM74LS373 Transparent Latches DM74LS374 Positive-Edge-Triggered Flip-Flops

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DM74LS373 DM74LS374

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Storage Temperature Range Operating Free Air Temperature Range 7V 7V 65C to +150C 0C to +70C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

DM74LS373 Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL tW tSU tH TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Pulse Width (Note 3) Enable HIGH Enable LOW 15 15 5 20 0 70 Parameter Min 4.75 2 0.8 2.6 24 Nom 5 Max 5.25 Units V V V mA mA ns ns ns C

Data Setup Time (Note 2) (Note 3) Data Hold Time (Note 2) (Note 3) Free Air Operating Temperature

Note 2: The symbol () indicates the falling edge of the clock pulse is used for reference. Note 3: TA = 25C and VCC = 5V.

DM74LS373 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOZH IOZL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Off-State Output Current with HIGH Level Output Voltage Applied Off-State Output Current with LOW Level Output Voltage Applied Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 12 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max, VO = 2.7V VIH = Min, VIL = Max VCC = Max, VO = 0.4V VIH = Min, VIL = Max VCC = Max (Note 5) VCC = Max, OC = 4.5V, Dn, Enable = GND
Note 4: All typicals are at VCC = 5V, TA = 25C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Min

Typ (Note 4)

Max 1.5

Units V V

2.4

3.1

0.35

0.5 0.4 0.1 20 0.4 20 20

V mA A mA A A mA mA

50 24

225 40

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DM74LS373 DM74LS374

DM74LS373 Switching Characteristics

at VCC = 5V and TA = 25C RL = 667 Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output (Note 6) Output Disable Time from LOW Level Output (Note 6)
Note 6: CL = 5 pF.

From (Input) To (Output) Data to Q Data to Q Enable to Q Enable to Q Output Control to Any Q Output Control to Any Q Output Control to Any Q Output Control to Any Q

CL = 45 pF Min Max 18 18 30 30 28 36 20 25

CL = 150 pF Min Max 26 27 38 36 36 50

Units

ns ns ns ns ns ns ns ns

DM74LS374 Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL tW tSU tH TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Pulse Width (Note 8) Clock HIGH Clock LOW 15 15 20 1 0 70 Parameter Min 4.75 2 0.8 2.6 24 Nom 5 Max 5.25 Units V V V mA mA ns ns ns C

Data Setup Time (Note 7) (Note 8) Data Hold Time (Note 7) (Note 8) Free Air Operating Temperature

Note 7: The symbol () indicates the rising edge of the clock pulse is used for reference. Note 8: TA = 25C and V CC = 5V.

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DM74LS373 DM74LS374

DM74LS374 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOZH IOZL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Off-State Output Current with HIGH Level Output Voltage Applied Off-State Output Current with LOW Level Output Voltage Applied Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 12 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max, VO = 2.7V VIH = Min, VIL = Max VCC = Max, VO = 0.4V VIH = Min, VIL = Max VCC = Max (Note 10) VCC = Max, Dn = GND, OC = 4.5V 50 27 2.4 3.1 0.35 0.25 0.5 0.4 0.1 20 0.4 20 20 225 45 mA A mA A A mA mA Min Typ (Note 9) Max 1.5 Units V V

Note 9: All typicals are at VCC = 5V, TA = 25C. Note 10: Not more than one output should be shorted at a time, and the duration should not exceed one second.

DM74LS374 Switching Characteristics

at VCC = 5V and TA = 25C RL = 667 Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output (Note 11) Output Disable Time from LOW Level Output (Note 11)
Note 11: CL = 5 pF.

Parameter

CL = 45 pF Min 35 28 28 28 28 20 25 Max

CL = 150 pF Min 20 32 38 44 44 Max

Units MHz ns ns ns ns ns ns

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DM74LS373 DM74LS374

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B

www.fairchildsemi.com

DM74LS373 DM74LS374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D

www.fairchildsemi.com

DM74LS373 DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

DM74LS373 DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

April 1986 Revised March 2000

DM74LS373 DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
General Description
These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the DM74LS373 are transparent Dtype latches meaning that while the enable (G) is HIGH the Q outputs will follow the data (D) inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74LS374 are edge-triggered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.

Features
s Choice of 8 latches or 8 D-type flip-flops in a single package s 3-STATE bus-driving outputs s Full parallel-access for loading s Buffered control inputs s P-N-P inputs reduce D-C loading on data lines

Ordering Code:
Order Number DM74LS373WM DM74LS373SJ DM74LS373N DM74LS374WM DM74LS374SJ IDM29901NC Package Number M20B M20D N20A M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

2000 Fairchild Semiconductor Corporation

DS006431

www.fairchildsemi.com

DM74LS373 DM74LS374

Connection Diagrams
DM74LS373 DM74LS374

Function Tables
DM74LS373 Output Control L L L H
H = HIGH Level (Steady State)

DM74LS374 D H L X X Output H L Q0 Z
X = Dont Care

Enable G H H L X

Output Control L L L H

Clock L X

D H L X X

Output H L Q0 Z

L = LOW Level (Steady State)

Z = High Impedance State

= Transition from LOW-to-HIGH level

Q0 = The level of the output before steady-state input conditions were established.

Logic Diagrams
DM74LS373 Transparent Latches DM74LS374 Positive-Edge-Triggered Flip-Flops

www.fairchildsemi.com

DM74LS373 DM74LS374

Absolute Maximum Ratings(Note 1)

Supply Voltage Input Voltage Storage Temperature Range Operating Free Air Temperature Range 7V 7V 65C to +150C 0C to +70C
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation.

DM74LS373 Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL tW tSU tH TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Pulse Width (Note 3) Enable HIGH Enable LOW 15 15 5 20 0 70 Parameter Min 4.75 2 0.8 2.6 24 Nom 5 Max 5.25 Units V V V mA mA ns ns ns C

Data Setup Time (Note 2) (Note 3) Data Hold Time (Note 2) (Note 3) Free Air Operating Temperature

Note 2: The symbol () indicates the falling edge of the clock pulse is used for reference. Note 3: TA = 25C and VCC = 5V.

DM74LS373 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOZH IOZL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Off-State Output Current with HIGH Level Output Voltage Applied Off-State Output Current with LOW Level Output Voltage Applied Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 12 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max, VO = 2.7V VIH = Min, VIL = Max VCC = Max, VO = 0.4V VIH = Min, VIL = Max VCC = Max (Note 5) VCC = Max, OC = 4.5V, Dn, Enable = GND
Note 4: All typicals are at VCC = 5V, TA = 25C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Min

Typ (Note 4)

Max 1.5

Units V V

2.4

3.1

0.35

0.5 0.4 0.1 20 0.4 20 20

V mA A mA A A mA mA

50 24

225 40

www.fairchildsemi.com

DM74LS373 DM74LS374

DM74LS373 Switching Characteristics

at VCC = 5V and TA = 25C RL = 667 Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output (Note 6) Output Disable Time from LOW Level Output (Note 6)
Note 6: CL = 5 pF.

From (Input) To (Output) Data to Q Data to Q Enable to Q Enable to Q Output Control to Any Q Output Control to Any Q Output Control to Any Q Output Control to Any Q

CL = 45 pF Min Max 18 18 30 30 28 36 20 25

CL = 150 pF Min Max 26 27 38 36 36 50

Units

ns ns ns ns ns ns ns ns

DM74LS374 Recommended Operating Conditions

Symbol VCC VIH VIL IOH IOL tW tSU tH TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Pulse Width (Note 8) Clock HIGH Clock LOW 15 15 20 1 0 70 Parameter Min 4.75 2 0.8 2.6 24 Nom 5 Max 5.25 Units V V V mA mA ns ns ns C

Data Setup Time (Note 7) (Note 8) Data Hold Time (Note 7) (Note 8) Free Air Operating Temperature

Note 7: The symbol () indicates the rising edge of the clock pulse is used for reference. Note 8: TA = 25C and V CC = 5V.

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DM74LS373 DM74LS374

DM74LS374 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOZH IOZL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Off-State Output Current with HIGH Level Output Voltage Applied Off-State Output Current with LOW Level Output Voltage Applied Short Circuit Output Current Supply Current Conditions VCC = Min, II = 18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 12 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max, VO = 2.7V VIH = Min, VIL = Max VCC = Max, VO = 0.4V VIH = Min, VIL = Max VCC = Max (Note 10) VCC = Max, Dn = GND, OC = 4.5V 50 27 2.4 3.1 0.35 0.25 0.5 0.4 0.1 20 0.4 20 20 225 45 mA A mA A A mA mA Min Typ (Note 9) Max 1.5 Units V V

Note 9: All typicals are at VCC = 5V, TA = 25C. Note 10: Not more than one output should be shorted at a time, and the duration should not exceed one second.

DM74LS374 Switching Characteristics

at VCC = 5V and TA = 25C RL = 667 Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Output Enable Time to HIGH Level Output Output Enable Time to LOW Level Output Output Disable Time from HIGH Level Output (Note 11) Output Disable Time from LOW Level Output (Note 11)
Note 11: CL = 5 pF.

Parameter

CL = 45 pF Min 35 28 28 28 28 20 25 Max

CL = 150 pF Min 20 32 38 44 44 Max

Units MHz ns ns ns ns ns ns

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DM74LS373 DM74LS374

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B

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DM74LS373 DM74LS374

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D

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DM74LS373 DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com