INTEGRATED CIRCUITS

AN170
NE555 and NE556 applications

1988 Dec


 
 
Philips Semiconductors Application note

NE555 and NE556 applications AN170

INTRODUCTION oscillator, only one additional resistor is necessary. By proper

In mid 1972, Philips Semiconductors introduced the 555 timer, a selection of external components, oscillating frequencies from one
unique functional building block that has enjoyed unprecedented cycle per half hour to 500kHz can be realized. Duty cycles can be
popularity. The timer’s success can be attributed to several inherent adjusted from less than one percent to 99 percent over the
characteristics foremost of which are versatility, stability and low frequency spectrum. Voltage control of timing and oscillation
cost. There can be no doubt that the 555 timer has altered the functions is also available.
course of the electronics industry with an impact not unlike that of
the IC operational amplifier. Timer Circuitry
The timer is comprised of five distinct circuits: two voltage
The simplicity of the timer, in conjunction with its ability to produce comparators; a resistive voltage divider reference; a bistable
long time delays in a variety of applications, has lured many flip-flop; a discharge transistor; and an output stage that is the
designers from mechanical timers, op amps, and various discrete “totem-pole” design for sink or source capability. Q10-Q13 comprise
circuits into the ever increasing ranks of timer users. a Darlington differential pair which serves as a trigger comparator.
Starting with a positive voltage on the trigger, Q10 and Q11 turn on
when the voltage at Pin 2 is moved below one third of the supply
DESCRIPTION voltage. The voltage level is derived from a resistive divider chain
The 555 timer consists of two voltage comparators, a bistable consisting of R7, R8 and R9. All three resistors are of equal value
flip-flop, a discharge transistor, and a resistor divider network. To (5kΩ). At 15V supply, the triggering level would be 5V.
understand the basic concept of the timer let’s first examine the When Q10 and Q11 turn on, they provide a base drive for Q15,
timer in block form as in Figure 1. turning it on. Q16 and Q17 form a bistable flip-flop. When Q15 is
saturated, Q16 is ”off’ and Q17 is saturated. Q16 and Q17 will remain
The resistive divider network is used to set the comparator levels.
in these states even if the trigger is removed and Q15 is turned ”off’.
Since all three resistors are of equal value, the threshold comparator
While Q17 is saturated, Q20 and Q14 are turned off.
is referenced internally at 2/3 of supply voltage level and the trigger
comparator is referenced at 1/3 of supply voltage. The outputs of the The output structure of the timer is a “totem-pole” design, with Q22
comparators are tied to the bistable flip-flop. When the trigger and Q24 being large geometry transistors capable of providing
voltage is moved below 1/3 of the supply, the comparator changes 200mA with a 15V supply. While Q20 is ”off’, base drive is provided
state and sets the flip-flop driving the output to a high state. The for Q22 by Q21, thus providing a high output.
threshold pin normally monitors the capacitor voltage of the RC
For the duration that the output is in a high state, the discharge
timing network. When the
transistor is ”off’. Since the collector of Q14 is typically connected to
VCC the external timing capacitor, C, while Q14 is off, the timing capacitor
555 OR 1/2 556
now can charge through the timing resistor, RA.
DISCHARGE The capacitor voltage is monitored by the threshold comparator
(Q1-Q4) which is a Darlington differential pair. When the capacitor
CONTROL R voltage reaches two thirds of the supply voltage, the current is
VOLTAGE directed from Q3 and Q4 thru Q1 and Q2. Amplification of the current
change is provided by Q5 and Q6. Q5-Q6 and Q7-Q8 comprise a
THRESHOLD COMP
diode-biased amplifier. The amplified current change from Q6 now
provides a base drive for Q16 which is part of the bistable flip-flop, to
R FLIP
FLOP OUTPUT change states. In doing so, the output is driven “low”, and Q14, the
OUTPUT
discharge transistor, is turned “on”, shorting the timing capacitor to
TRIGGER COMP ground.
The discussion to this point has only encompassed the most
fundamental of the timer’s operating modes and circuitry. Several
R
points of the circuit are brought out to the real world which allow the
timer to function in a variety of modes. It is essential that one
understands all the variations possible in order to utilize this device
to its fullest extent.
RESET
SL00954
Reset Function
Figure 1. 555/556 Timer Functional Block Diagram Regressing to the trigger mode, it should be noted that once the
capacitor voltage exceeds 2/3 of the supply, the threshold device has triggered and the bistable flip-flop is set, continued
comparator resets the flip-flop which in turn drives the output to a triggering will not interfere with the timing cycle. However, there may
low state. When the output is in a low state, the discharge transistor come a time when it is necessary to interrupt or halt a timing cycle.
is “on”, thereby discharging the external timing capacitor. Once the This is the function that the reset accomplishes.
capacitor is discharged, the timer will await another trigger pulse, the In the normal operating mode the reset transistor, Q25, is off with its
timing cycle having been completed. base held high. When the base of Q25 is grounded, it turns on,
The 555 and its complement, the 556 Dual Timer, exhibit a typical providing base drive to Q14, turning it on. This discharges the timing
initial timing accuracy of 1% with a 50ppm/C timing drift with capacitor, resets the flip-flop at Q17, and drives the output low. The
temperature. To operate the timer as a one-shot, only two external reset overrides all other functions within the timer.
components are necessary; resistance & capacitance. For an

1988 Dec 2
Philips Semiconductors Application note

NE555 and NE556 applications AN170

FM
CONTROL VOTLAGE

VCC R1 R2 R3 R4 R7 R12
4.7K 330 4.7K 1K 5K 6.8K

Q21
Q5 Q6 Q7 Q9
Q22
Q8
Q19 R13
3.9K

Q1 Q4 R10
82.K
THRESHOLD Q2 Q3 OUTPUT
Q23
C B
CB
Q18 R11
R5 E 4.7K Q20
10K R8
Q11 Q12 5K
Q17 R14
Q10 Q13 220
TRIGGER Q16
Q24
Q25
RESET Q15
R9 R15
DISCHARGE R6 4.7K
Q14 100K 5K
GND R16
NOTE: 100
All resistor values are in ohms.
SL00955
Figure 2. Schematic of 555 or 1/2 556 Dual Timer
Trigger Requirements voltage function is not used, it is strongly recommended that a
Due to the nature of the trigger circuitry, the timer will trigger on the bypass capacitor (0.01µF) be placed across the control voltage pin
negative-going edge of the input pulse. For the device to time-out and ground. This will increase the noise immunity of the timer to
properly, it is necessary that the trigger voltage level be returned to high frequency trash which may monitor the threshold levels causing
some voltage greater than one third of the supply before the timeout timing error.
period. This can be achieved by making either the trigger pulse
sufficiently short or by AC coupling into the trigger. By AC coupling Monostable Operation
the trigger (see Figure 3), a short negative-going pulse is achieved The timer lends itself to three basic operating modes:
when the trigger signal goes to ground. AC coupling is most 1. Monostable (one-shot)
frequently used in conjunction with a switch or a signal that goes to 2. Astable (oscillatory)
ground which initiates the timing cycle. Should the trigger be held
low, without AC coupling, for a longer duration than the timing cycle 3. Time delay
the output will remain in a high state for the duration of the low
trigger signal, without regard to the threshold comparator state. This By utilizing one or any combination of basic operating modes and
is due to the predominance of Q15 on the base of Q16, controlling suitable variations, it is possible to utilize the timer in a myriad of
the state of the bistable flip-flop. When the trigger signal then returns applications. The applications are limited only to the imagination of
to a high level, the output will fall immediately. Thus, the output the designer.
signal will follow the trigger signal in this case. One of the simplest and most widely used operating modes of the
timer is the monostable (one-shot). This configuration requires only
Control Voltage two external components for operation (see Figure 4). The
One additional point of significance, the control voltage, is brought sequence of events starts when a voltage below one third VCC is
out on the timer. As mentioned earlier, both the trigger comparator, sensed by the trigger comparator. The trigger is normally applied in
Q10-Q13, and the threshold comparator, Q1-Q4, are referenced to an the form of a short negative-going pulse. On the negative-going
internal resistor divider network, R7, R8, R9. This network edge of the pulse, the device triggers, the output goes high and the
establishes the nominal two thirds of supply voltage (VCC) trip point discharge transistor turns off. Note that prior to the input pulse, the
for the threshold comparator and one third of VCC for the discharge transistor is on, shorting the timing capacitor to ground. At
trigger comparator. The two thirds point at the junction of R7, R8 and this point the timing capacitor, C, starts charging through the timing
the base of Q4 is brought out. By imposing a voltage at this point, resistor, R. The voltage on the capacitor increases exponentially
the comparator reference levels may be shifted either higher or with a time constant T=RC. Ignoring capacitor leakage, the capacitor
lower than the nominal levels of one third and two thirds of the will reach the two thirds VCC level in 1.1 time constants or
supply voltage. Varying the voltage at this point will vary the timing. T = 1.1 RC (1)
This feature of the timer opens a multitude of application possibilities
such as using the timer as a voltage-controlled oscillator,
pulse-width modulator, etc. For applications where the control

1988 Dec 3
Philips Semiconductors Application note

NE555 and NE556 applications AN170

Where T is in seconds, R is in ohms, and C is in Farads. This transistor. The transistor discharges the capacitor, C, rapidly. The
voltage level trips the threshold comparator, which in turn drives the timer has completed its cycle and will now await another trigger
output low and turns on the discharge pulse.

VCC VCC Astable Operation

In the astable (free-run) mode, only one additional component, RB,
is necessary. The trigger is now tied to the threshold pin. At
power-up, the capacitor is discharged, holding the trigger low. This
10k
triggers the timer, which establishes the capacitor charge path
through RA and RB. When the capacitor reaches the threshold level
.001µF of 2/3 VCC, the output drops low and the discharge transistor turns
2 555 on.
The timing capacitor now discharges through RB. When the
capacitor voltage drops to 1/3 VCC, the trigger comparator trips,
automatically retriggering the timer, creating an oscillator whose
frequency is given by:
1.49
VCC f  (2)
(R A
2R B) C

Selecting the ratios of RA and RB varies the duty cycle accordingly.

Lo and behold, we have a problem. If a duty cycle of less than fifty
percent is required, then what? Even if RA=0, the charge time
cannot be made smaller than the discharge time because the
1/3 VCC charge path is RA+RB while the discharge path is RB alone. In this
case it becomes necessary to insert a diode in parallel with RB,
cathode toward the timing capacitor. Another diode is desirable, but
OVOLTS not mandatory (this one in series with RB), cathode away from the
1 timing capacitor. Now the charge path becomes RA, through the
QUALIFICATION OF parallel diode into C. Discharge is through the series diode and RB
TRIGGER PULSE AS
SEEN BY THE TIMER to the discharge transistor. This scheme will afford a duty cycle
SWITCH GROUNDED range from less than 5% to greater than 95%. It should be noted that
AT THIS POINT
SL00956 for reliable operation a minimum value of 3kΩ for RB is
Figure 3. AC Coupling of the Trigger Pulse recommended to assure that oscillation begins.

VCC Time Delay

In this third basic operating mode, we aim to accomplish something
a little different from monostable operation. In the monostable mode,
R when a trigger was applied, immediately changed to the high state,
555 OR 1/2 556
timed out, and returned to its pre-trigger low state. In the time delay
DISCHARGE
mode, we require the output not to change state upon triggering, but
at some precalculated time after trigger is received.
CONTROL R
VOLTAGE The threshold and trigger are tied together, monitoring the capacitor
THRESHOLD COMP voltage. The

C
R FLIP
OUTPUT
FLOP
OUTPUT

COMP
TRIGGER

RESET
SL00957

Figure 4. Monostable Operation

1988 Dec 4
Philips Semiconductors Application note

NE555 and NE556 applications AN170

VCC
VCC
ICHARGE

RA
RA
555 OR 1/2 556
7 OPTIONAL
DISCHARGE 555 RB
OR 6
R R
1/2 555
CONTROL 2 IDISCHARGE
VOLTAGE
COMP C
THRESHOLD

SL00959
R FLIP OUTPUT
FLOP Figure 6. Method of Achieving Duty
Cycles Less Than 50%
COMP
TRIGGER Selecting External Components
In selecting the timing resistor and capacitor, there are several
R considerations to be taken into account.
Stable external components are necessary for the RC network if
C
good timing accuracy is to be maintained. The timing resistor(s)
should be of the metal film variety if timing accuracy and
RESET
SL00958 repeatability are important design criteria. The timer exhibits a
Figure 5. Astable Operation typical initial accuracy of one percent. That is, with any one RC
network, from timer to timer only one percent change is to be
discharge function is not used. The operation sequence begins as expected. Most of the initial timing error (i.e., deviation from the
transistor (T1) is turned on, keeping the capacitor grounded. The formula) is due to inaccuracies of external components. Resistors
trigger sees a low state and forces the timer output high. When the range from their rated values by 0.01% to 10% and 20%. Capacitors
transistor is turned off, the capacitor commences its charge cycle. may have a 5% to 10% deviation from rated capacity. Therefore, in a
When the capacitor reaches the threshold level, only then does the system where timing is critical, an adjustable timing resistor or
output change from its normally high state to the low state. The precision components are necessary. For best results, a good
output will remain low until T1 is again turned on. quality trim pot, placed in series with the largest feasible resistance,
will allow for best adjustability and performance.
The timing capacitor should be a high quality, stable component with
GENERAL DESIGN CONSIDERATIONS
very low leakage characteristics. Under no circumstances should
The timer will operate over a guaranteed voltage range of 4.5V to
ceramic disc capacitors be used in the timing network! Ceramic disc
15VDC with 16VDC being the absolute maximum rating. Most of the
capacitors are not sufficiently stable in capacitance to operate
devices, however, will operate at voltage levels as low as 3VDC. The
properly in an RC mode. Several acceptable capacitor types are:
timing interval is independent of supply voltage since the charge rate
silver mica, mylar, polycarbonate, polystyrene, tantalum, or similar
and threshold level of the comparator are both directly proportional
types.
to supply. The supply voltage may be provided by any number of
sources, however, several precautions should be taken. The most The timer typically exhibits a small negative temperature coefficient
important, the one which provides the most headaches if not (50ppm/°C). If timer accuracy over temperature is a consideration,
practiced, is good power supply filtering and adequate bypassing. timing components with a small positive temperature coefficient
Ripple on the supply line can cause loss of timing accuracy. The should be chosen. This combination will tend to cancel timing drift
threshold level shifts, causing a change of charging current. This will due to temperature.
cause a timing error for that cycle.
In selecting the values for the timing resistors and capacitor, several
Due to the nature of the output structure, a high power totem-pole points should be considered. A minimum value of threshold current
design, the output of the timer can exhibit large current spikes on the is necessary to trip the threshold comparator. This value is 0.25µA.
supply line. Bypassing is necessary to eliminate this phenomenon. A To calculate the maximum value of resistance, keep in mind that at
capacitor across the VCC and ground, directly across the device, is the time the threshold current is required, the voltage potential on
necessary and ideal. The size of a capacitor will depend on the the threshold pin is two thirds of supply. Therefore:
specific application. Values of capacitance from 0.01µF to 10µF are
Vpotential = VCC - VCapacitor
not uncommon, but note that the bypass capacitor would be as
close to the device as physically possible. Vpotential = VCC - 2/3VCC = 1/3VCC

1988 Dec 5
Philips Semiconductors Application note

NE555 and NE556 applications AN170

Maximum resistance is then defined as The most important characteristic of the capacitor should be as low
a leakage as possible. Obviously, any leakage will subtract from the
V CC * V CAP charge count, causing the calculated time to be longer than
R MAX + (3)
I THRESH anticipated.

Example: VCC = 15V Control Voltage

Regressing momentarily, we recall that the control voltage pin is
15 * 10 connected directly to the threshold comparator at the junction of R7,
R MAX + + 20M

0.25(10 * 6) or
R8. The combination of R7, R8 and R9 comprises the resistive
VCC = 5V voltage divider network that establishes the nominal VCC trigger
comparator level (junction R8, R9) and the VCC level for the
5 * 3.33
R MAX + + 6.6M
threshold comparator (junction R7, R8).
0.25(10 * 6)
For most applications, the control voltage function is not used and
NOTE: therefore is bypassed to ground with a small capacitor for noise
If using a large value of timing resistor, be certain that the capacitor leakage is significantly filtering. The control voltage function, in other applications, becomes
lower than the charging current available to minimize timing error. an integral part of the design. By imposing a voltage at this pin, it
becomes possible to vary the threshold comparator “set” level above
On the other end of the spectrum, there are certain minimum values
or below the 2/3 VCC nominal, thereby varying the timing. In the
of resistance that should be observed. The discharge transistor,
monostable mode, the control voltage may be varied from 45% to
Q14, is current-limited at 35mA to 55mA internally. Thus, at the
90% of VCC. The 45-90% figure is not firm, but only an indication to
current limiting values, Q14 establishes high saturation voltages.
a safe usage. Control voltage levels below and above those stated
When examining the currents at Q14, remember that the transistor,
have been used successfully in some applications.
when turned on, will be carrying two current loads. The first being
the constant current through timing resistor, RA. The second will be In the oscillatory (free-run) mode, the control voltage limitations are
the varying discharge current from the timing capacitor. To provide from 1.7V to VCC. These values should be heeded for reliable
best operation, the current contributed by the RA path should be operation. Keep in mind that in this mode the trigger level is also
minimized so that the majority of discharge current can be used to important. When the control voltage raises the threshold comparator
reset the capacitor voltage. Hence it is recommended that a 5kΩ level, it also raise the trigger comparator level by one-half that
value be the minimum feasible value for RA. This does not mean amount due to R8 and R9 of Figure 2. As a voltage-controlled
lower values cannot be used successfully in certain applications, yet oscillator, one can expect ±25% around center frequency (fO) to be
there are extreme cases that should be avoided if at all possible. virtually linear with a normal RC timing circuit. For wider linear
variations around fO it may be desirable to replace the charging
VCC
resistor with a constant-current source. In this manner, the
exponential charging characteristics of the classical configuration
RA will be altered to linear charge time.
555 OR 1/2 556

DISCHARGE Reset Control

R R The only remaining function now is the reset. As mentioned earlier,
CONTROL
VOLTAGE
the reset, when taken to ground, inhibits all device functioning. The
COMP
output is driven low, the bistable flip-flop is reset, and the timing
capacitor is discharged. In the astable (oscillatory) mode, the reset
THRESHOLD
R FLIP can be used to gate the oscillator. In the monostable, it can be used
OUTPUT
FLOP as a timing abort to either interrupt a timing sequence or establish a
standby mode (i.e., device off during power-up). It can also be used
COMP in conjunction with the trigger pin to establish a positive
TRIGGER edge-triggered circuit as opposed to the normal negative
edge-trigger mode. One thing to keep in mind when using the reset
C R function is that the reset voltage (switching) point is between 0.4V
and 1.0V (min/max). Therefore, if used in conjunction with the
trigger, the device will be out of the reset mode prior to reaching 1V.
At that point the trigger is in the “turn on” region, below 1/3 VCC. This
RESET
SL00960 will cause the device to trigger immediately, effectively triggering on
Figure 7. Time Delay Operation the positive-going edge if a pulse is applied to Pins 4 and 2
simultaneously.
Capacitor size has not proven to be a legitimate design criteria.
Values ranging from picofarads to greater than one thousand
microfarads have been used successfully. One precaution need be
utilized, though. (It should be a cardinal rule that applies to the
FREQUENTLY ASKED APPLICATIONS
usage of all ICs.) Make certain that the package power dissipation is QUESTIONS
not exceeded. With extremely large capacitor values, a maximum The following is a harvest of various maladies, exceptions, and
duty cycle which allows some cooling time for the discharge idiosyncrasies that may exhibit themselves from time to time in
transistor may be necessary.

1988 Dec 6
Philips Semiconductors Application note

NE555 and NE556 applications AN170

various applications. Rather than cast aspersions, a quick review of here are some ingenious applications devised by our applications
this list may uncover a solution to the problem at hand. engineers and by some of our customers.
1. In the oscillator mode when reset is released the first time Missing Pulse Detector
constant is approximately twice as long as the rest. Why? Using the circuit of Figure 10a, the timing cycle is continuously reset
Answer: In the oscillator mode the capacitor voltage fluctuates by the input pulse train. A change in frequency, or a missing pulse,
between 1/2 and 2/3 of the supply voltage. When reset is pulled allows completion of the timing cycle which causes a change in the
down, the capacitor discharges completely. Thus for the first cycle output level. For this application, the time delay should be set to be
it must charge from ground to 2/3 VCC, which takes twice as long. slightly longer than the normal time between pulses. Figure 10b
2. What is maximum frequency of oscillations? shows the actual waveforms seen in this mode of operation.
Answer: Most devices will oscillate about 1MHz. However, in the Figure 11b shows the waveforms of the timer in Figure 11a when
interest of temperature stability, one should operate only up to used as a divide-by-three circuit. This application makes use of the
about 500kHz. fact that this circuit cannot be retriggered during the timing cycle.
3. What is temperature drift for oscillator mode?
Answer: Temperature drift of oscillator mode is 3 times that of Pulse Width Modulation (PWM)
one-shot mode due to the addition of a second voltage In this application, the timer is connected in the monostable mode as
comparator. Frequency always increases with an increasing shown in Figure 12a. The circuit is triggered with a continuous pulse
temperature. Therefore it is possible to partially offset this drift train and the threshold voltage is modulated by the signal applied to
with an offsetting temperature coefficient in the external the control voltage terminal (Pin 5). This has the effect of modulating
resistor/capacitor combination. the pulse width as the control voltage varies. Figure 12b shows the
actual waveform generated with this circuit.
4. Oscillator exhibits spurious oscillations on crossover points. Why?
Answer: The 555 can oscillate due to feedback from power Pulse Position Modulation (PPM)
supply. Always bypass with sufficient capacitance close to the This application uses the timer connected for astable (free-running)
device for all applications. operation, Figure 13a, with a modulating signal again applied to the
5. Trying to drive a relay but 555 hangs up. How come? control voltage terminal. Now the pulse position varies with the
Answer: Inductive feedback. A clamp diode across the coil modulating signal, since the threshold voltage, and hence the time
prevents the coil from driving Pin 3 below a negative 0.6V. This delay, is varied. Figure 13b shows the waveform generated for
negative voltage is sufficient in some cases to cause the timer to triangle-wave modulation signal.
malfunction. The solution is to drive the relay through a diode,
Tone Burst Generator
thus preventing Pin 3 from ever seeing a negative voltage.
The 556 Dual Timer makes an excellent tone burst generator. The
6. Double triggering of the TTL loads sometimes occurs. Why? first half is connected as a one-shot and the second half as an
Answer: Due to the high current capability and fast rise and fall oscillator (Figure 14).
times of the output, a totem-pole structure different from the TTL
The pulse established by the one-shot turns on the oscillator,
classical structure was used. Near TTL threshold this output
allowing a burst to be generated.
exhibits a crossover distortion which may double trigger logic. A
1000pF capacitor from the output to ground will eliminate any Sequential Timing
false triggering.
One feature of the dual timer is that by utilizing both halves it is
7. What is the longest time I can get out of the timer? possible to obtain sequential timing. By connecting the output of the
Answer: Times exceeding an hour are possible, but not always first half to the input of the second half via a 0.001µF coupling
practical. Large capacitors with low leakage specs are quite capacitor, sequential timing may be obtained. Delay t1 is determined
expensive. It becomes cheaper to use a countdown scheme (see by the first half and t2 by the second half delay (Figure 15).
Figure 15) at some point, dependent on required accuracy. VCC
Normally 20 to 30 min. is the longest feasible time.

R
DESIGN FORMULAS
4 8
Before entering the section on specific applications it is 7 D2
advantageous to review the timing formulas. The formulas given 3
here apply to the 555 and 556 devices. RELAY
5
2 1 5
C .01
APPLICATIONS
The timer, since introduction, has spurred the imagination of
thousands. Thus, the ways in which this device has been used are
far too numerous to present each one. A review of the basic SL00961
operation and basic modes has previously been given. Presented
Figure 8. Driving High Q Inductive Loads

1988 Dec 7
Philips Semiconductors Application note

NE555 and NE556 applications AN170

VCC VCC

RA RA
T = 1.1 RAC
7 2 (T = TIME BEFORE
OUTPUT GOES LOW)

8 6
C C
T (OUTPUT HIGH) = 1.1 RAC

a. Monostable Timing
b. True Time Delay
VCC
VCC

RA RA

7
RB
RB
6

6 C
t1 (OUTPUT HIGH) = 0.67 (RA + (RB)C
t1 (OUTPUT lLOW) = 0.67 (RB)C
t1 (OUTPUT HIGH) = 0.67 RAC C
T = t1 + t2(TOTAL PERIOD)
t1 (OUTPUT lLOW) = 0.67 RBC
1 1.49
T = t1 + t2(TOTAL PERIOD) f  
1 T (R A
2R B) C
f 
T RA
RB
D(DUTY CYCLE) =
R A
2R B
c. Modified Duty Cycle (Astable) d. Astable Timing SL00962
Figure 9.
The first half of the timer is started by momentarily connecting Pin 6
VCC (5 TO 15V)
to ground. When it is timed-out (determined by 1.1 R1C1) the
second half begins. Its duration is determined by 1.1 R2C2.

RA
4 8 7
OUTPUT 3

NE/SE 555 6
5
1 2
C

.02µF

INPUT
a. Schematic Diagram

INPUT 2V/CM

OUTPUT VOLTAGE 5V/CM

CAPACITOR VOLTAGE 5V/CM

RA 1KΩ C = .09 — F
b. Expected Waveforms
SL00963
Figure 10.

1988 Dec 8
Philips Semiconductors Application note

NE555 and NE556 applications AN170

+ VCC (5 TO 15V) + VCC (5 TO 5V)

RESET

RA RA
4 8
2 7 OUTPUT 3 4 8 7

NE/SE 555 6 C NE/SE 555 RB

OUTPUT 3 5
1 1 5 26
CONTROL C
VOLTAGE
.01µF
MODULATION
INPUT
a. Schematic Diagram
INPUT a. Schematic Diagram
T = 0.1 MS/CM
INPUT 2V/CM MODULATION INPUT 2V/CM

OUTPUT VOLTAGE 5V/CM

OUTPUT VOLTAGE — 5V/CM

CAPACITOR VOLTAGE 5V/CM

t = 0.1 MS/CM
RA 11250Ω C = .02µF — F CAPACITOR VOLTAGE — 2V/CM
RA — 3KΩ RB — 500ΩC = .01µF
b. Expected Waveforms
SL00964 b. Expected Waveforms SL00966
Figure 11. Figure 13.
+ VCC (5 TO 5V)
Long Time Delays
In the 556 timer the timing is a function of the charging rate of the
external capacitor. For long time delays, expensive capacitors with
RA
OUTPUT extremely low leakage are required. The practicality of the
3 4 8
7 components involved limits
C
NE/SE 555 6
VCC VCC VCC
CLOCK 2
INPUT 1 5
MODULATION R1 R2
INPUT
2k 2k
MIN 4 14 MIN
1, 2 13
a. Schematic Diagram
INPUT R2
6
T = 0.5 MS/CM TRIGGER 555 12
MODULATION INPUT 2V/CM 5 C2
8

C1 10 9 OUTPUT
7 3 11

CLOCK INPUT 5V/CM

.01‘ .01

NOTE:
All resistor values are in ohms. SL00967
OUTPUT VOLTAGE 5V/CM
Figure 14. Tone Burst Generator
OUTPUT VOLTAGE 5V/CM the time between pulses to around twenty minutes.
b. Expected Waveforms To achieve longer time periods, both halves may be connected in
SL00965
tandem with a “divide-by” network in between.
Figure 12.

1988 Dec 9
Philips Semiconductors Application note

NE555 and NE556 applications AN170

The first timer section operates in an oscillatory mode with a period that capacitor C can charge. When capacitor voltage reaches the
of 1/fO. This signal is then applied to a “divide-by-N” network to give timer’s control voltage (0.33VCC), the flip-flop resets and the
an output with the period of N/fO. This can then be used to trigger transistor conducts, discharging the capacitor (Figure 19).
the second half of the 556. The total time is now a function of N and
Greater linearity can be achieved by substituting a constant-current
fO (Figure 16).
source for the frequency adjust resistor (R).
Speed Warning Device VCC VCC VCC VCC VCC
Utilizing the “missing pulse detector” concept, a speed warning
device, such as depicted, becomes a simple and inexpensive circuit R2
R1
(Figure 17a). 10K 1me 130K 10K
4 10 14
g
Car Tachometer 1 12
C2
The timer receives pulses from the distributor points. Meter M 13 50µF
receives a calibrated current thru R6 when the timer output is high. 2 556 8
After time-out, the meter receives no current for that part of the duty C1 .001
.001 5 OUTPUT 1
cycle. Integration of the variable duty cycle by the meter movement 1µF
INPUT 6 9 OUTPUT 2
provides a visible indication of engine speed (Figure 18). 7 3
11

Oscilloscope-Triggered Sweep .01‘ .01

The 555 timer holds down the cost of adding a triggered sweep to
an economy oscilloscope. The circuit’s input op amp triggers the SL00968
timer, setting its flip-flop and cutting off its discharge transistor so Figure 15. Sequential Timer
LONG TIME COUNTER
(HOURS, DAYS, WEEKS,, ETC.)
VCC
RA
(5K) INPUT FROM 10K R
RB
6 14 1 3 4 10 111314 6 N8281 COUNTER
(5M) 10 14
1 5 (30 MIN.) 13
2 1/2–556 5 8 N8281 9 (1 HOUR) .01µF 12 1/2–556 9 OUTPUT
2 (2 HOUR) 8
6
C 7 3 12 (4 HOUR) 7 11
7
(130µF) CLOCK TO NEXT
N8281 COUNTER C .01µF
.01µF .01µF
FOR LONGER TIMES

NOTE:
All resistor values are in ohms.
SL00969

Figure 16. Method of Achieving Long Time Delays

VCC = 12V VIN

R15 R1 RBUFFER
10K 10K
PIN 6
PIN
1 & 2 BV

4 14 PIN 5
10 14
1 12 PIN 8

1/2–556 13 1/2–556 9 PIN

2 VOUT 12 & 138V
VIN 6 5 8
7 3 OUT
7 11
PIN 9
.01µF .01µF 15µF .01µF

b. Operating Waveforms
Speed Warning Device
a. Schematic of Speed Warning Device
SL00970
Figure 17.

1988 Dec 10
Philips Semiconductors Application note

NE555 and NE556 applications AN170

R7
15
12 V
D3
C3 R4 R5
9V 10µF 50K 5K
IGNITION 1N960 R3 4 8
COIL
5K 6
C1
R1 0.1µF
1K 2 555
7
DISTRIBUTOR C2
POINTS
0.1µF
D1 3 R6
R2
5V 5K 5 1 200K
1N5231 CALIBRATION
C4 DC
0.1µF M 50mA
FULL
NOTE: SCALE
All resistor values are in ohms.
SL00971
Figure 18. Tachometer

+ VCC + VCC

2K 2K
FROM 1KFREQUENCY
VERTICAL 1M ADJUST
AMPLIFIER R + VCC
100K 8 5V
+ VCC CONTROL
SENSITIVITY 100K
ADJUST 5K NE555 0
+ VCC 6
1M COMPARATOR
+ VCC
5K TO
– VCC HORIZONTAL
DISCHARGE 7
2 AMPLIFIER
100K COMPARATOR FLIP FLOP
100pF 10kHz RANGE
TRIGGER 10K 5K PULSE
LEVEL 1 MHz 1 – 100Hz
TRIGGER OUTPUT
ADJUST – VCC

c 100Hz
4 VREF 3 +
0.001 10kHz
µF 0.1µF 10µF
10K

NOTE:
All resistor values are in ohms.

+ VCC SL00972

Figure 19. Schematic of Triggered Sweep

VCC (5–15V)
OUTUT

PB VCC (5–15V)
SW
R1
300
R2
C2 R5 4.7M
3 8
60µF 2.2K
4 NE555 6
R4
7.5K 2
R3 1
C1
300K 1000pF
NOTE:
All resistor values are in ohms.
SL00973

Figure 20. Square Wave Tone Burst Generator

1988 Dec 11
Philips Semiconductors Application note

NE555 and NE556 applications AN170

+ 15V UNREG
12 13
6 10 Q2 2N3642
REMOTE SHUTDOWN
2 + 15 V OUT
PEAK INVERSE 110V µA723 R4
5.6
3 C8 C11
+ 6VDC
C4 0.1µF 0.1µF
1N2071 R5
0.1µF 22mF 5 4
BACK EMF 3 13
R1 35V 7
+ 30 V 2
3K
4 8 4 C6 C7
T1 R6
7 2N3054 C5 0.05µF 100pF 2.2K
R12 NE/SE55N 3 D2 22µF
1 GND OUT
82K R3 5 35V –– 15 UNREG.
2
6 1 5 25
C9
*SM3359 1N2071
C1 C2 R7 0.05µF
C3 2A 18K
100µF 510pF 0.01µF R9 R10
GND 12 11 47K 2K
6 10
1N914
30µSEC D3
9 Q3
µA733 2N3644
Q4

5 4 2N3644
7 13 C10 R11
R8 100 5.6 C12
NOTES: 0.1µF
22K pF
All resistor values are in ohms.
*Shafer Magnetics – 15 V OUT
Covina, Calif.
(213) 331-3115
SL00974
Figure 21. Regulated DC-to-DC Converter

VCC + 15V
OFFSEWT PULSE GENERATOR
OR SYSTEM CLOCK VOUT
ADJUST 5K 15V FOR
10µF
VIN = 0
2.5K 1M
10K 100K
VIN + – VOUT
8 4
100K 741 6 b FOR
5 a
VREF + 555 VIN = V1
2/3 VCC
3 2
7 1 C1
1µF VOUT
VOUT FOR
47K – 15V
2N3642 VIN = V2
V2 V1

NOTES:
All resistor values in ohms.
*VIN is limited to 2 diode drops within ground or below VCC.
SL00975

Figure 22. Voltage-to-Pulse Duration Converter

Square Wave Tone Burst Generator Servo System Controller
Depressing the pushbutton provides square wave tone bursts To control a servo motor remotely, the 555 needs only six extra
whose duration depends on the duration for which the voltage at Pin components (Figure 23).
4 exceeds a threshold. Components R1, R2 and C1 cause the
astable action of the timer IC (Figure 20). Stimulus Isolator
Stimulus isolator uses a photo-SCR and a toroid for shaping pulses
Regulated DC-to-DC Converter of up to 200V at 200µA (Figure 24).
Regulated DC-to-DC converter produces 15VDC outputs from a
+5VDC input. Line and load regulation is 0.1% (Figure 21). Voltage-to-Frequency Converter (0.2% Accuracy)
Linear voltage-to-frequency converter (a) achieves good linearity
Voltage-to-Pulse Duration Converter over the 0 to -10V range. Its mirror image (b) provides the same
Voltage levels can be converted to pulse durations by combining an linearity over the 0 to +10V range, but is not DTL/TTL compatible
op amp and a timer IC. Accuracies to better than 1% can be (Figure 25).
obtained with this circuit (a), and the output signals (b) still retain the
original frequency, independent of the input voltage (Figure 22).

1988 Dec 12
Philips Semiconductors Application note

NE555 and NE556 applications AN170

TO PIN
POSITION SET VCC V OF 543
R1
5K 4.3K

R8
0.2µF 100

4 8 2 8
7 2.2pF 1 11.5Ω
IN457 CR1 555 NE544
6 3 4 MOTOR
SERVO
R2 V AMPLIFIER
2
68K
1 5
R1 6 5 3 7 9
R3 10K V
R2
R9
C1 0.1µF 3.3K 50K
220
0.33µF R4 R5 R7
33 33 56K
4.7µF 04.7µF TO PIN 5
OF 543
V
R6 4.7µF
4.7µF
TRANSMITTER 56K
GEAR
NOTE: TRAIN
All resistor values in ohms.

TO CONTROL SURFACE SL00976

Figure 23. Servo System Controller

NOTE:
All resistor values in ohms.
*Power rating depends on duty cycle from 1/2W for 20-25% duty cycle to 15-20W for 75-90% duty cycle.
SL00977
Figure 24. Stimulus Isolator

1988 Dec 13
Philips Semiconductors Application note

NE555 and NE556 applications AN170

Positive-to-Negative Converter
Transformerless DC-DC converter derives a negative supply voltage
from a positive. As a bonus, the circuit also generates a clock signal.
The negative output voltage tracks the DC input voltage linearity (a),
but its magnitude is about 3V lower. Application of a 500Ω load, (b),
causes 10% change from the no-load value (Figure 26).

Auto Burglar Alarm

Timer A produces a safeguard delay, allowing driver to disarm alarm
and eliminating a vulnerable outside control switch. The SCR
prevents timer A from triggering timer B, unless timer B is triggered
by strategically-located sensor switches (Figure 27).

Cable Tester
a. Compact tester checks cables for open-circuit or short-circuit
conditions. A differential transistor pair at one end of each cable line
remains balanced as long as the same clock pulse-generated by the
timer IC appears at both ends of the line. A clock pulse just at the
clock end of the line lights a green light-emitting diode, and a clock
pulse only at the other end lights a red LED (Figure 28).

Low Cost Line Receiver

The timer makes an excellent line receiver for control applications
involving relatively slow electromechanical devices. It can work
without special drivers over single unshielded lines (Figure 29).

NOTE:
All resistor values in ohms.
b. SL00978

Figure 25.

NOTE:
All resistor values in ohms.

a. Positive-to-Negative Converter
b. c. SL00979

Figure 26.

1988 Dec 14
Philips Semiconductors Application note

NE555 and NE556 applications AN170

NOTES:
Timer Philips Semiconductors NE555
All resistor values in ohms. SL00980

Figure 27. Auto Burglar Alarm

1988 Dec 15
Philips Semiconductors Application note

NE555 and NE556 applications AN170

SL00981

Figure 28. Cable Tester

Temperature Control
A couple of transistors and thermistor in the charging network of the
555-type timer enable this device to sense temperature and produce
a corresponding frequency output. The circuit is accurate to within
±1Hz over a 78°F temperature range (Figure 30).

Automobile Voltage Regulator

A monolithic 555-type timer is the heart of this simple automobile
voltage regulator. When the timer is off so that its output (Pin 3) is
low, the power Darlington transistor pair is off. If battery voltage
becomes too low (less than 14.4V in this case), the timer turns on
NOTES:
All resistor values in ohms. SL00982
and the Darlington pair conducts (Figure 31).

Figure 29. Low Cost Line Receiver

1988 Dec 16
Philips Semiconductors Application note

NE555 and NE556 applications AN170

NOTES:
a. b.
All resistor values in ohms. SL00983

Figure 30. Temperature Control

NOTES:
* Can be any general purpose Silicon diode or 1N4157.
** Can be any general purpose Silicon transistor.
All resistor values are in ohms. SL00984
Figure 31. Automobile Voltage Regulator
DC-to-DC Converter Ramp Generator

SL00985

Figure 32. DC-to-DC Converter SL00986

Figure 33. Ramp Generator

1988 Dec 17
Philips Semiconductors Application note

NE555 and NE556 applications AN170

Ramp Generator In other low power operations of the timer where VCC is removed
until timing is needed, it is necessary to consider the output load. If
the output is driving the base of a PNP transistor, for example, and
its power is not removed, it will sink current into Pin 3 to ground and
use excessive power. Therefore, when driving these types of loads,
one should recall this internal sinking path of the timer.

1.49
f +
(R A @ 2R B) C
SL00987

Figure 34. Ramp Generator

Low Power Monostable Operation

In battery-operated equipment where load current is a significant
factor, Figure 35 can deliver 555 monostable operation at low
standby power. This circuit interfaces directly with CMOS 4000
series and 74L00 series. During the monostable time, the current
drawn is 4.5mA for T=1.1RC. The rest of the time the current drawn
is less than 50µA. (Circuit submitted by Karl Imhof, Executone Inc.,
Long Island City, NY.)

SL00988

Figure 35. Low Power Monostable

Theory of Operation the threshold voltage on Pin 6 from activating the reset action of the
The missing pulse detector (see Figure 10) operates as a triggered timer if the time delay between input pulses is shorter than the
monostable multivibrator but with the added feature that the output programmed time delay set by the external R/C network. This inhibit
signal remains high for a repetitive pulse condition at the trigger action occurs whenever the timing capacitor is prevented from
input node. This is accomplished by the addition of a reset inhibit exceeding 2/3 VCC. Note that the degree of capacitor discharge is
function which prevents the normal time-out of the timer as long as directly proportional to the duration of the turn-on time of the
there are input pulses present with period less than the time delay external PNP transistor. The capacitor voltage is equal to charge
period. The circuit which provides this feature is an external PNP Q/capacitance C. The amount of delta VC per input pulse is (IC x TP
transistor with its base tied in parallel with the trigger input pin. (sec)) / C(F) where TP is the width of the trigger pulse and IC is the
collector current of the PNP transistor during the duration of the
As the input pulse waveform exceeds the instantaneous timing trigger pulse. The inhibit condition is fulfilled by making the time
coapacitor voltage by one VBE in the negative direction, the PNP constant of the RC network, connected to Pin 6 and 7, somewhat
transistor is turned on momentarily, pulling the capacitor voltage longer than the interpulse period for normal fault free operation. The
toward ground potential. This incremental discharge action prevents

1988 Dec 18
Philips Semiconductors Application note

NE555 and NE556 applications AN170

output will then remain positive until such a fault is long than the RC from the first stage continually toggles for a speed condition below
time constant. The missing pulse detector then provides a negative the set point. Next, stage one output signal is fed directly into the
going output pulse proportional to the number of missing pulses trigger input, Pin 8, of the second stage of the NE556, and
received at the input. simultaneously to the base of the external PNP discharge transistor.
The second stage operation is identical to the one described in the
The Speed Warning Circuit missing pulse detector section above. The second stage timer
Figure 17 shows an application which uses two missing pulse output is held high when the speed transducer pulse train rate is
detectors in tandem as an aover-speed sensor. A speed transducer below the critical threshold. This stage of the dual timer acts to alter
pulse signal of negative polarity is fed into the first stage of the the dynamic response of the speed detector so that a number of
NE556 which is actually used in the mode for which the timer is pulses must be missed to activate its output. This gives the detector
always allowed to time out if the pulse rate is below the desired a form of hysteresis and prevents the occurance of intermittent
speed threshold. This occurs, as discussed above, if the pulse input output signaling due to an instantaneous over speed condition. The
period is longer than the natural time-out period of the timer (as length of the stage-two time delay threshold is programmed by
determined by the external RC network). The wavetrain coming adjusting RBUFFER.

14 VCC
1 13
DISCHARGE DISCHARGE

2 12
THRESHOLD THRESHOLD
COMP COMP

3 11
CONTROL VOLTAGE CONTROL VOLTAGE
4 10
RESET RESET

FLIP FLOP FLIP FLOP

5 9
OUTPUT OUTPUT

6 COMP COMP 8
TRIGGER TRIGGER

GROUND 7

SL00989
Figure 36. Block Diagram
BIBLIOGRAPHY 8. “Pair of IC Timers Sounds Auto Burglar Alarm”, Michael
1. “Unconventional Uses for IC Timers” Jim Wyland and Eugene Harvey, Electronics, June 21, 1973, p. 131.
Hnatek, Electronic Design, June 7, 1973, pp. 88-90. 9. “Timer ICs and LEDs Form Cable Tester”, L.W. Herring, Elec-
2. “DC-to-DC Converter Uses the IC Timer”, Robert Soloman tronics, May 10, 1973, p. 115.
and Robert Broadway, EDN, September 5, 1973, pp. 87-91. 10. “IC Timer can Function as Low Cost Line Receiver”, John
3. “Oscilloscope--Triggered Sweep: Another Job for IC Timer”, Pate, Electronics, June 21, 1973, p. 132.
Robert McDermott, Electronics, October 11, 1973, p. 125. 11. “IC Timer Plus Thermister can Control Temperature”, Donald
4. “Get Square Wave Tone Bursts With a Single Timer IC”, Sol Dekold, Electronics, June 21, 1973, p. 132.
Black, Electronic Design, September 1973, p. 148. 12. “IC Timer Makes Economical Automobile Voltage Regula-
5. “Toroid and Photo-SCR Prevent Ground Loops in High- tor”, T.J. Fusar, Electronics, September 21, 1974, p. 100.
Isolation Biological Pulser”, Joseph Sonsino, Electronic De- 13. “Switching Regulators, the Efficient Way to Power”,
sign, June 21, 1973. p. 128.
Robert Olla, Electronics, August 16, 1973, pp. 94-95.
6. “Voltage-to-Frequency Converter Constructed With Few
14. “Put the IC Timer to Work in a Myriad of Ways”, Eu-
Components is Accurate to 0.2%”, ’Chaim Klement, Electronic
Design, June 21, 1973, p. 124. gene Hnatek, EDN, March 5, 1973, pp. 54-58.

7. “Positive Voltage Changed into Negative and No Transform-

er is Required”, Bert Pearl, Electronic Design, May 24, 1973, p.
164.

1988 Dec 19