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Thomson Chassis Mt35

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0% found this document useful (0 votes)

2K views89 pages

Thomson Chassis Mt35

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ricardo_Massis

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Service Manual

CHASSIS MT35

Contents
1. Caution..........2 2. Product Specification.......6 3. Test and Alignment......9 4. Main IC Brief Instruction MT5335PU....................................................16 MT5133........................................................22 MT8295..............................................................................24 WL6702F.............................25 WM8501..........................................................................................................30 SiL9185A.........................................................................................................33 RT8110............................................................................................................47 MP1411...........................................................................................................50 TDA7266.........................................................................................................54 AO4459...........................................................................................................55 13N03LT..........................................................................................................56 5 Block Diagram... .........................57 6 Schematic Diagram ...............................58 7 Exploded View 26E90....................86 26E92 ...... .......................87 32E90...........................88 32E92..............................................................................................................89

1 CAUTION:

Use of controls, adjustments or procedures other than those specified herein may result in hazardous radiation exposure. CA UTION: TO REDUCE THE RISK OF ELECTRICAL SHOCK, DO NOT REMOVE COVER (OR BACK). NO USER SERVICEABLE PARTS INSIDE. REFER SER VICING TO QUALIFIED SERVICE PERSONNEL.

CAUTION
RISK OF ELECTRIC SHOCK DO NOT OPEN.

The lighting flash with arrowhead symbol, with an equilateral triangle is intended to alert the user to the presence of uninsulated dangerous voltage within the products enclosure that may be of sufficient magnitude to constitute a risk of electric shock to the person. The exclamation point within an equilateral triangle is intended to alert the user to the presence of important operating and maintenance (servicing) instructions in the literature accompanying the appliance.

WARNING: TO REDUCE RISK OF FIRE OR ELECTRIC SHOCK, DO NOT EXPOSE THIS APPLIANCE TO RAIN OR MOISTURE.

IMPORTANT SAFETY INSTRUCTIONS

CAUTION:
Read all of these instructions. Save these instructions for later use. Follow all Warnings and Instructions marked on the audio equipment. 1. Read Instructions- All the safety and operating instructions should be read before the product is operated. 2. Retain Instructions- The safety and operating instructions should be retained for future reference. 3. Heed Warnings- All warnings on the product and in the operating instructions should be adhered to. 4. Follow Instructions- All operating and use instructions should be followed.

FOR YOUR PERSONAL SAFETY

1. 2. 3. 4. 5. 6. 7. 8. 9. When the power cord or plug is damaged or frayed, unplug this television set from the wall outlet and refer servicing to qualified service personnel. Do not overload wall outlets and extension cords as this can result in fire or electric shock. Do not allow anything to rest on or roll over the power cord, and do not place the TV where power cord is subject to traffic or abuse. This may result in a shock or fire hazard. Do not attempt to service this television set yourself as opening or removing covers may expose you to dangerous voltage or other hazards. Refer all servicing to qualified service personnel. Never push objects of any kind into this television set through cabinet slots as they may touch dangerous voltage points or short out parts that could result in a fire or electric shock. Never spill liquid of any kind on the television set. If the television set has been dropped or the cabinet has been damaged, unplug this television set from the wall outlet and refer servicing to qualified service personnel. If liquid has been spilled into the television set, unplug this television set from the wall outlet and refer servicing to qualified service personnel. Do not subject your television set to impact of any kind. Be particularly careful not to damage the picture tube surface. Unplug this television set from the wall outlet before cleaning. Do not use liquid cleaners or aerosol cleaners. Use a damp cloth for cleaning.

10.1. Do not place this television set on an unstable cart, stand, or table. The television set may fall, causing serious injury to a child or an adult, and serious damage to the appliance. Use only with a cart or stand recommended by the manufacturer, or sold with the television set. Wall or shelf mounting should follow the manufacturer s instructions, and should use a mounting kit approved by the manufacturer. 10.2. An appliance and cart combination should be moved with care. Quick stops, excessive force, and uneven surfaces may cause the appliance and cart combination to overturn.

PROTECTION AND LOCATION OF YOUR SET

11. Do not use this television set near water ... for example, near a bathtub, washbowl, kitchen sink, or laundry tub, in a wet basement, or near a swimming pool, etc. Never expose the set to rain or water. If the set has been exposed to rain or water, unplug the set from the wall outlet and refer servicing to qualified service personnel.

12. Choose a place where light (artificial or sunlight) does not shine directly on the screen. 13. Avoid dusty places, since piling up of dust inside TV chassis may cause failure of the set when high humidity persists. 14. The set has slots, or openings in the cabinet for ventilation purposes, to provide reliable operation of the receiver, to protect it from overheating. These openings must not be blocked or covered. Never cover the slots or openings with cloth or other material. Never block the bottom ventilation slots of the set by placing it on a bed, sofa, rug, etc. Never place the set near or over a radiator or heat register. Never place the set in a built-in enclosure, unless proper ventilation is provided.

PROTECTION AND LOCATION OF YOUR SET

15.1. If an outside antenna is connected to the television set, be sure the antenna system is grounded so as to provide some protection against voltage surges and built up static charges, Section 810 of the National Electrical Code, NFPA No. 70-1975, provides information with respect to proper grounding of the mast and supporting structure, grounding of the lead-in wire to an antenna discharge unit, size of grounding conductors, location of antenna discharge unit, connection to grounding electrode, and requirements for the grounding electrode.

EXAMPLE OF ANTENNA GROUNDING AS PER NATIONAL ELECTRICAL CODE INSTRUCTIONS

EXAMPLE OF ANTENNA GROUNDING AS PER NATIONAL ELECTRICAL CODE ANTENNA LEAD- IN WIRE

GROUND CLAMP ANTENNA DISCHARGE UNIT (NEC SECTION 810-20)

ELECTRIC SERVICE EQUIPMENT

GROUNDING CONDUCTORS (NEC SECTION 810-21)

GROUND CLAMPS NEC-NATIONAL ELECTRICAL CODE POWER SERVICE GROUNDING ELECTRODE SYSTEM (NEC ART 250. PART H)

15.2. Note to CATV system installer : (Only for the television set with CATV reception) This reminder is provided to call the CATV system installer s attention to Article 820-40 of the NEC that provides guidelines for proper grounding and, in particular, specifies that the cable ground shall be connected to the grounding system of the building, as close to the point of cable entry as practical. 16. An outside antenna system should not be located in the vicinity of overhead power lines or other electric lights or power circuits, or where it can fall into such power lines or circuits. When installing an outside antenna system, extreme care should be taken to keep from touching such power lines or circuits as contact with them might be fatal. For added protection for this television set during a lightning storm, or when it is left unattended and unused for long periods of time, unplug it from the wall outlet and disconnect the antenna. This will prevent damage due to lightning and power-line surges.

17.

OPERATION OF YOUR SET

18. This television set should be operated only from the type of power source indicated on the marking label.If you are not sure of the type of power supply at your home, consult your television dealer or local power company. For television sets designed to operate from battery power, refer to the operating instructions. If the television set does not operate normally by following the operating instructions, unplug this television set from the wall outlet and refer servicing to qualified service personnel. Adjust only those controls that are covered in the operating instructions as improper adjustment of other controls may result in damage and will often require extensive work by a qualified technician to restore the television set to normal operation. When going on a holiday : If your television set is to remain unused for a period of time, for instance, when you go on a holiday, turn the television set off and unplug the television set from the wall outlet.

19.

20.

IF THE SET DOES NOT OPERATE PROPERLY

21. If you are unable to restore normal operation by following the detailed procedure in your operating instructions, do not attempt any further adjustment. Unplug the set and call your dealer or service technician. 22. Whenever the television set is damaged or fails, or a distinct change in performance indicates a need for service, unplug the set and have it checked by a professional service technician. 23. It is normal for some TV sets to make occasional snapping or popping sounds, particularly when being turned on or off. If the snapping or popping is continuous or frequent, unplug the set and consult your dealer or service technician.

FOR SERVICE AND MODIFICATION

24. Do not use attachments not recommended by the television set manufacturer as they may cause hazards. 25. When replacement parts are required, be sure the service technician has used replacement parts specified by the manufacturer that have the same characteristics as the original part. Unauthorized substitutions may result in fire, electric shock, or other hazards. 26. Upon completion of any service or repairs to the television set, ask the service technician to perform routine safety checks to determine that the television is in safe operating condition.

MT35-EU Product Specification

Model # 22E92NH22 Brand THOMSON Panel technology (LCD / PDP) LCD Cabinet Design (Example: SC VII, V 6,,,) E9B PJO Nb 22E92 EAN Code 3244480284643 Chassis name MT5335 Certification(Gostandard/CE/MPTT/) CE COUNTRIES France Yes Germany Yes Italy, Greece Yes Spain, Portugal Yes Benelux (Belgium, Netherland, Luxemburg) Yes Northern Europe (Sweden, Norway, Denmark, Yes Finland) Eastern Europe (Russia, Poland, Czech, Yes Hungary) PICTURE Screen size : diagonale (inch) 22" Aspect ratio (16/9 // 4/3 // 15/9) 16/9 Color depth (8/10/12 bits) 8 1st panel supplier : panel suppliers AUO 1st panel supplier : panel reference T220SW01 V0 1st panel supplier : resolution 1680x1050 1st panel supplier : pixel Pitch (mmxmm) 0.282x0.282 1st panel supplier : Horizontal and vertical 170(H)/160(V) viewing angle 1st panel supplier : Typical response time (Grey 5mS to Grey) 1st panel supplier : Typical white luminance 300 (Nits) 1st panel supplier : Contrast VESA std 1000:1 1st panel supplier : Typical panel Life Time 50000 (Hours) VIDEO Noise Reduction (adaptative/) Yes Comb Filter (2D/3D) 3D Deinterlacer (no/linerar/motion adaptive/motion Frame buffer compensative) Film mode / reverse 3:2 pull down Yes/Yes Format control (Pin8/WSS) Yes/Yes Zoom type : 4/3 format Yes Zoom type : 14/9 Zoom Yes Zoom type : 16/9 Zoom Yes Zoom type : 16/9 Zoom up/down Yes Zoom type : Cinerama Yes Zoom type : 16/9Format Yes Colour preset (Cool/Normal/Warm/Favourite) Cool/Normal/Warm Contrast expend (low/medium/high) high Picture Reset Yes Backlight Adjust on factory menu Dynamic Backlight Dynamic Contrast adjustment Picture Autoadjustment (PC mode) Yes Vivid/Standard Picture presets : Standard / Film / Studio / /Movie/ Power Sport / Personal / Game / Video Camera saver/ Personal Sound RMS Power (Watt) 2x3W Yes/Yes/Yes/Yes/Y Treble, Bass, Balance, Volume, Mute Control es Sound presets (My personal/speech/mu sound/Music/Film/Voice/Flat/Standard/Panoram sic/movies/Multimed a) ia NICAM,German Sound techno (Stereo Nicam/Virtual Dolby Stereo/AVL/Wide Surround/SRS Trusurround XT/BBE Viva/SRS stereo/Visually WoW /) Impaired Loudspeakers built in (T/M/B) -/2/Decoding capability Standard BG/DK/I/LL` 26E90NH22 THOMSON LCD E9A 26E90 3244480284629 MT5335 CE Yes Yes Yes Yes Yes Yes Yes 26E92NH22 THOMSON LCD E9B 26E92 3244480284636 MT5335 CE Yes Yes Yes Yes Yes Yes Yes 32E90NH22 THOMSON LCD E9A 32E90 3244480284445 MT5335 CE Yes Yes Yes Yes Yes Yes Yes 32E92NH22 THOMSON LCD E9B 32E92 3244480284612 MT5335 CE Yes Yes Yes Yes Yes Yes Yes

26" 16/9 8 CMO V260B1-L02 1366x768 0.1405x0.4215 160(H)/150(V) 8mS 400 800:1 50000

32" 16/9 8 LG-Philips LC320WXN-SAC1 1366x768 0.17x0.51 178(H)/178(V) 8mS 500 1100:1 50000

Yes 3D Frame buffer

Yes/Yes Yes/Yes Yes/Yes Yes/Yes Yes/Yes Yes/Yes Yes/Yes Yes/Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Cool/Normal/Warm Cool/Normal/Warm Cool/Normal/Warm Cool/Normal/Warm high high high high Yes Yes Yes Yes on factory menu on factory menu on factory menu on factory menu Dynamic Backlight Dynamic Backlight Dynamic Backlight Dynamic Backlight adjustment adjustment adjustment adjustment Yes Yes Yes Yes Vivid/Standard Vivid/Standard Vivid/Standard Vivid/Standard /Movie/ Power /Movie/ Power saver/ /Movie/ Power /Movie/ Power saver/ saver/ Personal Personal saver/ Personal Personal 2x6W 2x6W 2x6W 2x6W Yes/Yes/Yes/Yes/Y Yes/Yes/Yes/Yes/Ye Yes/Yes/Yes/Yes/Y Yes/Yes/Yes/Yes/Ye es s es s personal/speech/mu personal/speech/mu personal/speech/mu personal/speech/mus sic/movies/Multimed sic/movies/Multimedi sic/movies/Multimed ic/movies/Multimedia ia a ia NICAM,German NICAM,German NICAM,German NICAM,German Stereo/AVL/Wide Stereo/AVL/Wide Stereo/AVL/Wide Stereo/AVL/Wide stereo/Visually stereo/Visually stereo/Visually stereo/Visually Impaired Impaired Impaired Impaired -/2/-/2/-/2/-/2/BG/DK/I/LL` BG/DK/I/LL` BG/DK/I/LL` BG/DK/I/LL`

Color System (PAL/SECAM/NTSC) DVBT (yes/no) Video standard NTSC 3.58 / 4.43 (AV) HD capability PC capability (up to maximum format) User convenience

PAL/SECAM/NTSC( PAL/SECAM/NTSC( PAL/SECAM/NTSC( PAL/SECAM/NTSC( PAL/SECAM/NTSC( AV) AV) AV) AV) AV) Yes(MPEG 2) Yes(MPEG 2) Yes(MPEG 2) Yes(MPEG 2) Yes(MPEG 2) Yes Yes Yes Yes Yes YES (720p, 1080i; YES (720p, 1080i; YES (720p, 1080i; YES (720p, 1080i; YES (720p, 1080i; 1080P 480i/p; 1080P 480i/p; 1080P 480i/p; 1080P 480i/p; 1080P 480i/p; 576i/p) 576i/p) 576i/p) 576i/p) 576i/p) UXGA UXGA UXGA UXGA UXGA English\Czech\Ger man\Spanish\Finnis h\French\Greek\Hun garian\Italian\Dutch\ Polish\Portuguese\ Russian\Swedish\Sl ovak\Ukrainian\Esto nian\Latvian\Lithuan ian\Turkish\Norwegi an 999+1AV+1SVIDEO 999+1AV+1SVIDEO 999+1AV+1SVIDEO 999+1AV+1SVIDEO +1CMP+1VGA+2HD +1CMP+1VGA+2HD +1CMP+1VGA+2HD +1CMP+1VGA+2H MIs+1SCART MIs+1SCART MIs+1SCART DMIs+1SCART Power, CH +/, Vol Power, CH +/, Vol Power, CH +/, Vol Power, CH +/, Vol +/, Menu +/, Menu +/, Menu +/, Menu No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes English\Czech\Germ an\Spanish\Finnish\ French\Greek\Hung arian\Italian\Dutch\P olish\Portuguese\Ru ssian\Swedish\Slova k\Ukrainian\Estonian \Latvian\Lithuanian\ Turkish\Norwegian English\Czech\Germ an\Spanish\Finnish\ French\Greek\Hung arian\Italian\Dutch\P olish\Portuguese\Ru ssian\Swedish\Slova k\Ukrainian\Estonian \Latvian\Lithuanian\ Turkish\Norwegian English\Czech\Germ an\Spanish\Finnish\F rench\Greek\Hungari an\Italian\Dutch\Poli sh\Portuguese\Russi an\Swedish\Slovak\ Ukrainian\Estonian\L atvian\Lithuanian\Tur kish\Norwegian Yes No No No Yes Bulgarian\Czech\Da nish\German\Greek\ English\Spanish\Fre nch\Croatian\Italian\ Hungarian\Dutch\No rwegian\Polish\Portu guese\Romanian\Ru ssian\Slovak\Sloveni an\Serbian\Finnish\ Swedish\Turkish No No No TOP & FLOF 1.5 1000 Latin Pan-Euro West Latin Pan-Euro East CyrillicRussiaBulgarian/Ukrainian/ Byelorussia Greek Arabic Yes Yes/Yes No only PAT No Yes(in DVB-T) Yes No No No Yes Bulgarian\Czech\Da nish\German\Greek\ English\Spanish\Fre nch\Croatian\Italian\ Hungarian\Dutch\No rwegian\Polish\Portu guese\Romanian\Ru ssian\Slovak\Sloveni an\Serbian\Finnish\ Swedish\Turkish No No No TOP & FLOF 1.5 1000 Latin Pan-Euro West Latin Pan-Euro East CyrillicRussiaBulgarian/Ukrainian/ Byelorussia Greek Arabic Yes Yes/Yes No only PAT No Yes(in DVB-T) Yes No No No Yes Yes No No No Yes English\Czech\Germ an\Spanish\Finnish\F rench\Greek\Hungari an\Italian\Dutch\Polis h\Portuguese\Russia n\Swedish\Slovak\Uk rainian\Estonian\Latv ian\Lithuanian\Turkis h\Norwegian 999+1AV+1SVIDEO +1CMP+1VGA+2HD MIs+1SCART Power, CH +/, Vol +/, Menu No Yes Yes Yes Yes No No No Yes Bulgarian\Czech\Dan ish\German\Greek\E nglish\Spanish\Frenc h\Croatian\Italian\Hu ngarian\Dutch\Norwe gian\Polish\Portugue se\Romanian\Russia n\Slovak\Slovenian\S erbian\Finnish\Swedi sh\Turkish No No No TOP & FLOF 1.5 1000 Latin Pan-Euro West Latin Pan-Euro East CyrillicRussiaBulgarian/Ukrainian/ Byelorussia Greek Arabic Yes Yes/Yes No only PAT No Yes(in DVB-T)

IB languages

Program Numbers (example: 99+3AV) Number of buttons on cabinet (Power; Vol+/-; Pr+/-, Menu ) Main switch button (yes/no) Clock Sleep timer wake-up timer Parent Control - Channel lock (Input code for certain channel) Parent Control - Child lock (set the lock of the keyboard, only the RCU can control the TV) Parent Control - Kid pass (preset the ontime, channel for each day of the week) Parent Control - Channel lock (For digital transmission and DVD program, to filter some programms) Program auto switch off

OSD Language*

Bulgarian\Czech\Dan Bulgarian\Czech\Da ish\German\Greek\E nish\German\Greek\ nglish\Spanish\Frenc English\Spanish\Fre h\Croatian\Italian\Hu nch\Croatian\Italian\ ngarian\Dutch\Norwe Hungarian\Dutch\No gian\Polish\Portugue rwegian\Polish\Port se\Romanian\Russia uguese\Romanian\R n\Slovak\Slovenian\ ussian\Slovak\Slove Serbian\Finnish\Swe nian\Serbian\Finnish dish\Turkish \Swedish\Turkish No No No TOP & FLOF 1.5 1000 Latin Pan-Euro West Latin Pan-Euro East CyrillicRussiaBulgarian/Ukrainian/ Byelorussia Greek Arabic Yes Yes/Yes No only PAT No Yes(in DVB-T) No No No TOP & FLOF 1.5 1000 Latin Pan-Euro West Latin Pan-Euro East CyrillicRussiaBulgarian/Ukrainian/ Byelorussia Greek Arabic Yes Yes/Yes No only PAT No Yes(in DVB-T)

OSD Positioning OSD Transparency Adjust OSD Timeout Adjust Text Standard: (Top, FLOF,,,) Teletext Level: 2.5 / 1.5 Pages for teletext

Teletext character sets ****

TV Guide Auto Naming/Auto Sorting Auto update (for DVBT software ugrades) Multipicture : PIP (Double Tuner) / PIP (AV) / PAP / PAT / PIC Hotel mode (Y/N) Tuner FM (yes/no) Connectors (if possible, please indicate the position) RF Input (Antenna): Analogical / Digital Scart 1 : CVBS / RGB / S-VIDEO CINCH audio in / out (No volumpe control on Audio out/can be jack 3,5mm) CINCH video in / out S-video in / out

2 in 1 1/1/1(side)/1(side)/1(side)/-

Component Video Input (YCrCb/YPrPb) Component Audio Input (YCrCb/YPrPb) VGA in / Audio L/R in / Jack audio in 3.5mm HDMI1.3 DVI-HDCP Audio input for DVI HDCP CINCH subwoofer out / Coaxial out (SP-DIF) Headphone connector (mm) RS232 (Y/N) USB slot (NO/1.1/2) DVB-CI (common interface) Accessories included Remote control reference Carton (English/French/Spanish) Batteries IB Product registration Card AC power cords Audio Cord (Cinch to Jack 3.5mm) VGA Cord Wallmount Antenna Cable General Data Size (W x H x D, with stand) in mm Size (W x H x D, without stand) in mm Package Size (W x H x D, with stand but not mount) in mm Net Weight in kg Gross Weight in Kg Power supply Power consumption working / standby / Annual Design / Mechanical Wallmount VESA compatible (standard reference) Wallmount VESA Size Adaptor for VESA wallmount compatibility (accessory ref) Desktop Stand (included/optionnal + ref/NO) Panel Tilt (Fowards/Backwards/Rotation) Swivel function desktop stand (yes/no) + motorized? Docking station (yes/no) Floor Stand (included/optionnal + ref/NO) Glass shield (yes/no) Finish on Front Finish on side Finish on back Finish on stand number of colors on carton box Brand logo External AC/DC Power with DC power cord (yes/no) Number of Speaker Rating Label langages

1(rear) 1(rear) 1/-/1 2(1.3) Share with HDMI share with VGA -/Yes 3.5mm,x1 (side) share with VGA Yes(only for SW update) Yes RC1994906 Yes(English) Yes Yes No 1 No No No No 529x439x180 529x403x73.5 640x520x202 4.9 7 220-240V 50HZ 53W/1W/85KWH

1(rear) 1(rear) 1/-/1 2(1.3) Share with HDMI share with VGA -/Yes 3.5mm,x1 (side) share with VGA Yes(only for SW update) Yes RC1994906 Yes(English) Yes Yes No 1 No No No No 663x504x205 663x461x108 771x548x237 12 14 220-240V 50HZ

1(rear) 1(rear) 1/-/1 2(1.3) Share with HDMI share with VGA -/Yes 3.5mm,x1 (side) share with VGA Yes(only for SW update) Yes RC1994906 Yes(English) Yes Yes No 1 No No No No 796x582x230 796x535x102 915x652x249

15.5 15.5 18 18 220-240V 50HZ 220-240V 50HZ 130W/<1W/197KW 85W/<1W/132KWH 85W/<1W/132KWH 130W/<1W/198KWh h

VESA compatible 100mmx100mm No Yes No No No No No HG Spray paint(Black Q8257) Black A8252 as moulded Black A8252 as moulded HG Spray paint(Black Q8257) 1 THOMSON No/No grounded plug 2 DE, FR, IT, ES, EN, PL, CS, HU, RU, PT, EL, NL, SV, DA, FI, NO CE, GOST, Recycling, Class II,DTB, WEEE bin, Caution

VESA compatible 100mmx100mm No Yes No No No No No Half translucent as moulded (high glossy black) Black A8252 as moulded Black A8252 as moulded HG Spray paint(Black Q0003) 1 THOMSON No/No grounded plug 2 DE, FR, IT, ES, EN, PL, CS, HU, RU, PT, EL, NL, SV, DA, FI, NO CE, GOST, Recycling, Class II,DTB, WEEE bin, Caution

VESA compatible 200mmx100mm No Yes No No No No No Half translucent as moulded (high glossy black) Black A8252 as moulded Black A8252 as moulded HG Spray paint(Black Q0003) 1 THOMSON No/No grounded plug 2 DE, FR, IT, ES, EN, PL, CS, HU, RU, PT, EL, NL, SV, DA, FI, NO CE, GOST, Recycling, Class II,DTB, WEEE bin, Caution

VESA compatible 200mmx100mm No Yes No No No No No HG Spray paint(Black Q8257) Black A8252 as moulded Black A8252 as moulded HG Spray paint(Black Q8257) 1 THOMSON No/No grounded plug 2 DE, FR, IT, ES, EN, PL, CS, HU, RU, PT, EL, NL, SV, DA, FI, NO CE, GOST, Recycling, Class II,DTB, WEEE bin, Caution

Rating Label Logos/Icons (GOST, Bin, Recycling, Caution, )

Test and Alignment Specification for MT35-V0.20

The xxE90/E92NH22 models are Europe LCD platform with DVB-T designed for driving below panels: 32 LPL (LVDS) 26 CMO(LVDS) 22 AUO(DUAL LVDS) The main chip is from Mediatec (MTK5335 series) and supports below inputs: one analog and digital mixed RF (PAL B/G D/K I, SECAM B/G D/K L/L,DVB-T) one SCART (CVBS & RGB) one CMP (YPrPb can support from 480i up to 1080p) one VGA two HDMI (can support 480i/p, 576i/p, 720p up to 1080i/p) compliant v1.2. with HDCP, audio included as EIA-861B standard one S-Video input one Headphone output one SPDIF output More relevant details are listed into the Spec. INFO: All tests and measurements mentioned hereafter have to be carried out at a normal mains voltage (110 ~ 240 VAC) All voltages have to be measured with respect to ground, unless otherwise stated All final tests have to be done on a complete set including LCD panel in a room with temperature of 25+/-7C The White Balance (color temperature) has to be performed into subdued lighted room after at least 1 hour of warm-up/burn-in. This is applicable for both Alignment and Picture Performance evaluation at OQA in order to be set free of any temperature drift (colorimetry vs time) 1. Electrical Assembly Alignment 1.1. Preconditions DC/DC Check Before Power On the chassis, please check and make sure that U801,U802,U805, U809, U803, U804, U811,U201,C817(positive) outputs are not shorted to ground. Supply 12v and 5v to P804 and test the relative voltage. position value U811 3.3V +/-5% U801 3.3V +/-5% U802 9V +/-5% U803 1.2V +/-5% U804 2.5V +/-5% U805 5V +/-5% U809 3.3V +/-5%

U201 C817(+)

2.6V +/-5% 1.19V +/-5%

Download latest release MCU_SW into the Standby CPU(U810) using WT_MCU_ISP SW tool. See Appendix How to download MCU SW. Download latest release SW into the flash using MTK SW tool. See Appendix How to download FLASH SW. Or download the SW from USB port. 1.2. Functional Test Once the boards (chassis, FAV, KB, IR, PSU) and the panel are well interconnected, connect all external generator devices to relevant inputs/outputs below according to their respective test patterns format and check picture content and sound quality accordingly: Source Analog /Digital Tuner SCART1 (CVBS) Side av (cvbs) SVideo(Y/C) SCART1 (RGB) SCART1 (CVBSOut) HDMI VGA Headphone Loud Speakers CMP (YPrPb) Test signal (generator) RF cable Chroma/Fluke Chroma/Fluke Chroma/Fluke RF cable DVD with HDMI compliancy Chroma/QuantumData RF cable RF cable Chroma/QuantumData Test pattern (format/image) Full Band (VHF/UHF) + CATV DVB-T PAL Half Color & Gray bars PAL Half Color & Gray bars Half Color & Gray bars First channel Movie 720p@60Hz 1024x768@60Hz Half Color & Gray bars First channel First channel

1080i@60Hz Half Color & Gray bars Audio tones can be defined by the factory (ie: 1KHz & 3KHz, sweep, ). Picture video formats can be changed by the factory according to their own standard. 1.3. ADC Calibration Two inputs require an ADC calibration for the time being, That are: VGA Provide a test signal 1024768@60Hz with White Black squares. Select the corresponding Auto Color submenu item from Factory Menu, then press OK to start. When VGA channel is aligned, SCART-RGB is also aligned, so it is not necessary for RGB to be separately aligned. CMP Provide a test signal 576i@50Hz with 100% 8 steps Color Bar. Select the corresponding Auto Color submenu item from Factory Menu, then press OK to start.

The ADC is well performed when its displayed CMP after few seconds. 1.4. DDC & EDID Test The E-EDID data structure are according to VESA Enhanced EDID 1.3 (and EIA/CEA-861B for HDMI). Both VGA and HDMI have their own separate bin files: For EDID check, its needed to check whether the correct EDID is downloaded by checking corresponding EDID NVM Checksum or read them out to check bit by bit if it is in line with the released EDID bin file. **Before check the EDID please ensure the Factory Key in factory menu is disabled 1.5. HDCP Test For HDCP compliancy, its needed to check whether the HDCP key has been well set. 2. Final Assembly Alignment 2.1. Entering to Factory Menu To enter into Factory Menu in case of Factory Key is disabled, please to follow below steps: - press Remote Control key MENU to display main menu - press the subsequence Remote Control keys 7, 9, 1 and 5 - press Remote Control key MENU to exit main menu - press Remote Control key MENU to display main menu again The main menu will display FACTCORY at the last item To pop-up Factory Menu in case of Factory Key is enabled, please to follow below step: - press Remote Control key Blue To enable/disable Factory Key, please to follow below steps: - press Remote Control OK key to enter into System submenu - press Remote Control RIGHT or LEFT key till Factory Key item - press Remote Control OK key to toggle mode To exit Factory Menu, press Exit key from Remote Control. To comeback to Factory Menu root when you are into a submenu: - press Remote Control RED key. 2.2. Entering to P Mode To enter into P mode, an external serial 3.3VDC device is required for sending relevant commands. See appendix Serial Command Protocol for MTKxx. 2.3. White Balance Alignment Only VGA input requires color temperature adjustment as all other inputs or relative ones. Both Warm and Cool Color Coordinates are also relatives to Normal Color Temperature mode ones. See appendix CVBS/RGB/CMP/HDMI Relative Matrix Offsets and WARM/COOL Relative

Matrix Offsets. Those offsets values dont require any alignment but can be fine-tuned in Factory Menu as well. <The appendix is just a template, Every lot the relative offset is different. We need to align 5 sets first to get the relative offset data every lot. > Expected Targets and Tolerances The measured parameters should be x, y coordinates. The White Balance alignment should be performed using a contact less analyzer (ei: Minolta CA-210). The analyzer may not touch the screen surface, and measurement must be performed in a dark environment keeping the probe(s) at 90+/-2 from the panel. The alignment has to fulfill the requirements in Application Form. 2.4. High Pot. and Insulating Resistance Tests At the end of the process, a High Pot. and an Insulating Resistance tests are required for matching Safety Electrical requirements (ei: xxxx) High Voltage Withstanding requirements - Voltage - Max Leakage Current - Test Time 4240 VDC 1 mA 3 sec

Insulating Resistance requirements DC500V 4M 3 sec

- Voltage - Threshold Max - Threshold Min - Test Time 3. Factory Menu Definition 1) System Item Sub-item Factory Key

Burning Mode Power Mode

OFFFactory Key is invalidation ON Factory Key is availability, and BLUE key is the shortcut key. Note: option step 1Enter menu 27915 3Exit/Enter menu 4Enter Factory Item Enter Factory menu .(Or Enter Factory mode by hotkey ) Off/On Boot/Standby/Previous Boot: Enter power on mode Standby: Enter standby mode

Previous: power on according to last status Prefrequency HuiZhou/ Poland table Note:Pre-Frequency table(HuiZhou/ Poland) Reset Reset EEPROM data, and load the default value of EEPROM All: clear NVM valuesand set to default value User: Clear date of NVM in user menu, except the value of language / related installation/Factory setting, then set to the default value. Shop: Clear date of NVM in user menu, include the value related installation, and Clear date of factory menu except the item of Balance and sound ,set to default value TECI command Note:Priority below basic function of Factory menu 2) Balance Item Balance Sub-item Source Tone

Auto Color

White R White G White B Gray R Gray G Gray B 3)Sound Volume Curve Item Sound Sub-item VOL_0 VOL_10 VOL_50 VOL_90 VOL_100

For balance source Note:Switch SOURCE used left/right key Normal/Warm/Cool Note: RGB gain range is 0-255 The value of Warm and cool is the offset of Normal mode, their range is -128127, if the offset value beyond the boundaryset to max or min value. Note:display the completed source name on the right of item,If all the sourcs is ok ,show All R White balance G White balance B White balance R Gray balance G Gray balance B Gray balance

0 2 14 135 255 Note:mapping volume value to 0255 of the MCU register

TV Pre AV Pre 4)INFO SW version information Info Project MTK Version Version DATE

186 186

LCD_5335_TCL XXXXXX IDTV-XXXXXX_XX 2008-XX-XX

5)Factory default settings Followed as OOB setting. Appendix How to download MCU SW Prepare WT_MCU_ISP SW tool for update. 1. Connect the PC to board using MCU updating tool on P802 connector form chassis board. 2. Provide the +5VDC on P804 connector form chassis board and check U811 output voltage should be 3.3V. 3. Start WT_MCU_ISP.exe and download the MCU SW. ( please see file ISPToolGuideV33-08-2-17) Appendix How to download FLASH SW Prepare MTK SW tool for update. 1. Connect the PC to the board using an external +3.3VDC serial device (USB or COMx) on P201 connector from chassis board. VGA input can also be used using pin12 (RXD) & pin15 (TXD) just taking care that Factory Key from Factory Menu is enabled. 2. Provide the +5VDC STB on P804 connector from chassis board 3. Start MTKTOOL.exe application under MTKxx folder, and set the parameters as below picture:

4. Press Browse button to select the corresponding SW bin file to upload 5. Press Upgrade button to start downloading the SW and wait the gauge displayed 100% that means the SW has been successfully downloaded. In the meanwhile, all operations such erasing flash and so are parsed into the debug window script. 6. Once the SW is downloaded, switch-off/on the chassis board and wait few seconds for Eeprom update. Appendix Serial Command Protocol for MTKxx 1. A serial protocol for driving MTK chip through external +3.3VDC serial device (USB or COMx) is available. It may facilitate manufacturing process. Thus, both P201 connector from chassis board or either VGA input can also be used using pin12 (RXD) & pin15 (TXD) just taking care that Factory Key from Factory Menu is enabled. 2. The required serial port settings are as below 115200 bps 8 data bit 1 bit stop none parity 3. The command format is like hereafter described into BNS representation: 0xBB + Command + Data[[..] + ..] + 0xEE Both 0xBB and 0xEE bytes are mandatory and used as header and footer of the transmitted frame. Apart from INIT frame that is described further, all sent bytes need to be triggered before by an additional one as 0x50. So a complete frame might match following one: 0x50+0xBB+0x50+Command+0x50+Data[[..]+0x50+..]+0x50+0xEE 4. At first time, it might be required to initialize MTK chip by using once below INIT command (without any triggering byte): 0x02 + 0x00 + 0x00 + 0x13 + 0x01 + 0x00 5. A none exhaustive list of commands is already available. Appendix WARM/COOL Relative Matrix Offsets 1. These offsets should be done in the production by AOE.

MT5335PU Approval Datasheet

DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE

MTK CONFIDENTIAL, NO DISCLOSURE

GENERAL DESCRIPTION The MediaTek MT5335PU family consists of a backend decoder and a TV controller and offers high integration for advanced applications. It combines a transport de-multiplexer, a high definition MPEG-2 video decoder, an MPEG2 audio decoder, an LVDS transmitter, and an NTSC/PAL/SECAM TV decoder with a 3D comb filter. The MT5335PU enables consumer electronics manufactures to build high quality, low cost and feature-rich iDTVs. World-Leading Audio/Video Technology: The MT5335PU family has built-in high resolution and high-quality audio codec. It includes MediaTek MDDiTM de-interlace solution to generate very smooth picture quality for motions. A 3D comb filter added to the TV decoder recovers great detail for still pictures. The special color processing technology provides natural, deep colors and true studio quality graphics. Rich Features for High Value Products: The MT5335PU family enables a true single-chip experience. It integrates high-quality HDMI1.3, high speed VGA ADC, dual-channel LVDS, and USB2.0 receiver Reliable Front-end Receiving Capability: Excellent adjacent and co-channel rejection capability grants customers never miss any wonderful stream. Professional error-concealment provides stable, smooth and mosaic-free video quality.

Key Features:

An transport demultiplexer An MPEG2 video decoder An AC3 audio decoder HDMI1.3 receiver Audio codec Note: All Package are Lead Free

FEATURES

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MT5335PU Approval Datasheet

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MTK CONFIDENTIAL, NO DISCLOSURE

Host CPU
ARM 926EJS 8K I-Cache and 8K D-Cache 4K Instruction TCM JTAG ICE interface Watch Dog timers

Transport Demultiplexer
Supports a serial or parallel transport stream input Supports DVB-T, MPEG-2 transport stream input Supports DES/3-DES/DVB de-scramblers Up to 8-PID even/odd keys for descrambling Supports 32 PID filters and 32 section filters Supports positive/negative/mask section filtering Supports hardware CRC-32 check Supports PCR recovery function Supports a micro-processor for stream process and MPEG start code detection

MPEG2 Decoder
Supports one MPEG-2 HD decoder MPEG MP@ML, MP@HL and MPEG-1 video standards

2D Graphics
Supports multiple color modes Point, horizontal/vertical line primitive drawings Rectangle fill and gradient fill functions Bitblt with transparent options Alpha blending and alpha composition Bitblt Stretch Bitblt Font rendering by color expansion YCbCr to RGB color space conversion Supports off-line scaler

OSD Plane
Two linking list OSDs with multiple color mode and one of them has scaler

Video Plane
Supports video capture and over scan. Flesh tone management Gamma/anti-Gamma correction Color Transient Improvement (CTI) 2D Peaking Saturation/hue adjustment Brightness and contrast adjustment Black and White level extender Adaptive Luma/Chroma management Automatic detect film or video source 3:2/2:2 pull down source detection The MT5335PU support bob mode de-interlace with excellent low angle image processing. Arbitrary ratio vertical/horizontal scaling of video, from 1/32X to 32X Advanced non-linear panorama scaling.

2/14

MT5335PU Approval Datasheet

DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE

MTK CONFIDENTIAL, NO DISCLOSURE

Programmable zoom viewer Progressive or interlace scan output Supports alpha blending Dithering processing for flat panel display Frame rate conversion. The MT5335PU supports up to 1680x1050 panel and VGA dot-to-dot. Supports 2 video source PIP/POP feature. MT5335PU supports 6/8/10-bit onechannel or 6/8-bit dual-channel LVDS transmitter, LVDS speeding up to 75 MHz Built-in spread spectrum for EMI performance Programmable panel timing output On-chip 54 MHz 10-bit video ADC Supports PAL (B,G,D,H,M,N,I,Nc), NTSC, NTSC-4.43, SECAM Macrovision detection NTSC/PAL support 3D comb filter, SECAM supports 2D comb filter Built-in motion-adaptive 3D Noise Reduction VBI data slicer for CC/TT decoding Supports 2-S-Video. The MT5335PU supports 3-channel CVBS. Supports SCART connector Supports VGA input up to UXGA 162 MHz Supports full VESA standards

LVDS

CVBS In

VGA In

Component Video In
Supports two component video inputs Supports 480i / 480p / 576i / 576p / 720p / 1080i / 1080p

Audio line in interface

The MT5335PU support 1-bit line in data (two channels)

HDMI Receiver
Mixed 3 channels of HDMI1.3, data rate can be up to 2.25 GHz EIA/CEA-861B CEC

Audio ADC
The MT5335PU supports 8-channel (4 R/L pairs) analog audio input.

TV audio demodulator
Supports BTSC/EIA-J/A2/NICAM/PAL FM/SECAM world-wide formats Standard automatic detection Stereo demodulation, SAP demodulation Mode selection (Main/SAP/Stereo)

Audio DAC
Four on-chip audio DACs (2 R/L pairs) support R/L channel and subwoofer outputs

DRAM Controller

3/14

MT5335PU Approval Datasheet

DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE

MTK CONFIDENTIAL, NO DISCLOSURE

Supports 64 Mb to 512 Mb DDR DRAM devices The MT5335PU supports 16-bit data bus; address offers up to 64 M bytes space. Supports DDR1-333, DDR1-400, DDR2-400, DDR2-533, DDR2-667, DDR2-800

Audio DSP
Supports Dolby Digital AC-3 decoding MPEG-1 layer I/II decoding (DVB) Dolby Prologic II Audio output: 7.1ch + 2ch (down mix) Pink noise and white noise generator Equalizer Bass management 3D surround processing with virtual surround Audio and video lip synchronization Supports reverberation Automatic volume control One SPDIF out If internal audio DAC is disabled, the MT5335PU supports 1-bit (2-channel) main audio I2S output interface. Each channel is up to 24-bit resolution.

Flash Interface
The MT5335PU supports two one serial flash Serial flash interface supports up to 60 MHz clock rate, depending on the spec. of the flash device (currently 20 MHz at maximum) Supports on-the-fly decompression from Serial Flash to DRAM

Peripherals
The MT5335PU has one dedicated UART and one shared UART with GPIO. The MT5335PU has three basic serial interfaces; one is for the tuner, one is the master for general purpose and the other is the slave for HDMI EDID data. Three PWMs IR blaster and receiver Real-time clock and watchdog controller 1-port USB2.0/1.1 host supports USB mass storage class devices. Supports five-channel servo ADC.

IC Outline
The MT5335PU is 256-pin LQFP-EPAD Package 3.3V/1.1V and 2.5V for DDR1, 1.8V for DDR2

4/14

MT5335PU Approval Datasheet

DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE

MTK CONFIDENTIAL, NO DISCLOSURE

The MT5335PU is designed as an advanced, highly integrated SoC with improved connectivity features including HDMI interface and component/composite signal connections. Figure 1-1 shows the MT5335PU system block diagram while Figure 1-2 shows the MT5335PU functional block diagram.

L V DS

M T5131/ 3

M T 533 5P U

LC D Pa nel

Tuner

Flas h

D RA M

Figure 1-1 System Block Diagram

5/14

MT5335PU Approval Datasheet

DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE

MTK CONFIDENTIAL, NO DISCLOSURE

TS In

CVBS/ Analog YC Input Input

Component

HDMI Rx

Tuner In Audio Demod

Audio Input

Panel

16-bit DDR

VADCx4 TV Decoder VDO-In

HDMI In I/F

Audio ADC

LVDS

DDR DRAM Controller

Audio In
TS Demux

Mix and Post Processing

ARM BIM

De-interlace

JPEG,MPEG 2-D Graphic

OSD scaler

Vplane scaler

DRAM Bus IO Bus Audio DSP Audio I/F Audio DAC SPDIF, I2S JTAG BScan IrDA PCR Serial IF RTC USB2.0 Watchdog Serial Flash PWM CKGEN Servo ADC NAND Flash

UART

MS,SD,SM,xD

Figure 1-2 Functional Block Diagram

6/14

MT5133 DATA SHEET

General Description
1. Introduction
MT5133 is Media Taks 2nd generation COFDM (Coded Orthogonal Frequency Division Multiplex) channel demodulator for DVB-T receiver. It is fully compliant with the DVB-T specification (ETSI 300744) and Nordig Unified. MT5133 implements the functions from tuner IF out to MPEG-2 transport stream input. The device can support 2K, 4K or 8K mode with 6, 7, 8MHz channel. By integrating high performance A/D converters into the chip, MT5133 can accept first or second IF signal from conventional tuner thus eliminating the need for an external down-converter. Pure digital synchronization, advance channel estimation and equalization guarantee the wide acquisition range of MT5133. User can easily access on-chip information, including signal-to-noise ratio, Bit Error Ratio (BER) before and after Viterbidecoder. Serial or parallel MPEG transport stream output can be interfaced to all commonly available backend processor chips.

2. Features
ETSI300744 and Nordig Unified compliant Suitable for Single Frequency Network (SFN) operation Support 2K, 4K, 8K modes Support QPSK, 16QAM,64QAM constellations 1/4, 1/8, 1/16, 1/32 Guard interval Support hierarchical & non-hierarchical modes Automatic mode detection Full-digital timing/frequency with wide acquisition range Support triple offset On-chip high-performance 10-bit ADC Excellent adjacent Channel interference (ACI) rejection capability Excellent Co-Channel interference (CCI) rejection capability Build-in PID filters Very low power consumption < 180Mw Controlled by I2C interface Package: QFN48

3. Block Diagram

AGC IF

ADC&RF interface

Time Domain Processing

Freq. Domain Processing

FEC

TSIF

System Control

Host interface

I2C

Block Diagram of MT5133

MT8295 DATA SHEET

1. Introduction
The MediaTek MT8295 is a companion chip combined with MT533X serial chips to enable Common Interface (CI) and with the second generation of the Common Interface (CIV2) functions. It supports DVB compliant Conditional Access Module (CAM) and PCMCIA type memory cards. A NAND-flash-like bus bridge is built-in to perform the communication between a host and the card. Highly Flexible Interface: MT8295 supports one parallel or two serial MPEG2 transport stream interfaces from the front end demodulator and a serial MPEG2 transport stream interface to MPEG2 decoder. Also, the MT8295 is designed with highly flexible interface timing to compliant with the maximum vendors CAMs in the word. Extra Value for Your TV: MT8295 enables TV to receive DVB-CI protected program. It helps content providers to protect their programs and allows customers to receive more high-value TV programs. Fully tested compliant software is also available for this device.

2. DTV System Use MT8295

DRAM

FLASH

Tuner

MT513X
Demod TS in Decoder TS out

MT5335/6/7
Host interface

Panel

MT8295
CI/PCMCIA interface Card TS out Card TS in

CAM

WT6702F Data Sheet v0.93

1. General Description
The WT6702F is a microcontroller for system power manager with 1)Turbo 8051 compatible (3T) CPU, 2) 8K bytes flash memory, 3) 256 bytes SRAM, 4) 2 PWMs, 5) DPMS detector, 6) 8051 2 timers and UART, 7) Three Slave IIC interface, 8) 4 channel 8-bit A/D converter, 9) Real Time Clock, 10) watch-dog timer, 11) Embedded ISP, 12) Power down mode, 13) Embedded ICE mode.

1.1. Features
Embedded turbo 8051(3T) CPU Normal operation mode : 12MHz, 2MHz Stand by mode : 32KHz Memory : RAM: 256 Bytes Flash memory: 8K Bytes Turbo 8051 Timer0, Timer1, & UART Sync processor for monitoring DPMS (VGA connector) wake up signal 8-bit A/D converter with 4 selectable inputs, shared with IO pin 2 PWM pin output 3 slave mode IIC interface Universal IR Receiver INT pin to main chip Watch Dog timer Low voltage reset 32.768KHz crystal Oscillator & build-in RC Oscillator Build-in RTC Maximum 18 programmable IO pins 18-IO: 24 pin package 14-IO: 20 pin package 11/12-IO: 16 pin package Power consumption : Lower than 6mA at 12Mhz mode Lower than 4mA at 2Mhz mode Lower than 2mA at low speed mode(32KHz) Operating voltage range : 3.6V 2.5V Package: SOP16 SOP20/SSOP20 SOP24

1.2. Application
Display system power management MCU with RTC. I/O expander with RTC and ADC.

WT6702F Data Sheet v0.93

2. Pin Assignment
2.1. Package Type

32KOSCO 32KOSCI VSS NRST PWM1/GPIOC1 RXD/IRQ3/GPIOB7 TXD/IRQ2/GPIOB6 HIN/GPIOB5

1 2 3 4 5 6 7 8

WT6702F_S161

16 15 14 13 12 11 10 9

VDD GPIOA0/AD0 GPIOA3/AD3/IR GPIOA6/SCL1 GPIOA7/SDA1 GPIOB0/SCL2 GPIOB1/SDA2 GPIOB4/VIN

32KOSCO 32KOSCI VSS NRST PWM1/GPIOC1 RXD/IRQ3/GPIOB7 TXD/IRQ2/GPIOB6 HIN/GPIOB5 VIN/GPIOB4 IRQ1/P1.3/GPIOB3

1 2 3 4 5 6 7 8 9 10

WT6702F_S200

20 19 18 17 16 15 14 13 12 11

VDD_RTC VDD GPIOA0/AD0 GPIOA3/AD3/IR GPIOA4/SCL3/P1.0 GPIOA5/SDA3/P1.1 GPIOA6/SCL1 GPIOA7/SDA1 GPIOB0/SCL2 GPIOB1/SDA2

32KOSCO 32KOSCI VSS NRST PWM1/GPIOC1 PWM0/GPIOC0 RXD/IRQ3/GPIOB7 TXD/IRQ2/GPIOB6 HIN/GPIOB5 VIN/GPIOB4 IRQ1/P1.3/GPIOB3 IRQ0/P1.2/GPIOB2

1 2 3 4 5 6 7 8 9 10 11 12

WT6702F_S240

24 23 22 21 20 19 18 17 16 15 14 13

VDD_RTC VDD GPIOA0/AD0 GPIOA1/AD1 GPIOA2/AD2 GPIOA3/AD3/IR GPIOA4/SCL3/P1.0 GPIOA5/SDA3/P1.1 GPIOA6/SCL1 GPIOA7/SDA1 GPIOB0/SCL2 GPIOB1/SDA2

Package Type
SOP 16 pin SOP 20 pin SSOP 20 pin SOP 24 pin

Package Outline
150mil 300mil 150mil 300mil

WT6702F Data Sheet v0.93

2.2. Pin Description
S240 S200 S161 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 16 16 1 2 3 4 5 6 7 8 9 Pin I/O Function Description Name VDD PWR Power 3.3V VDD_RTC PWR RTC Power (<3.3V) 32KOSCO O 32kHz oscillator output 32KOSCI I 32kHz oscillator input VSS GND Ground NRST I Reset pin, active low (internal pull high) GPIOC1 I/O PWM1 output. Shared with GPIO C1 GPIOC0 I/O PWM0 output. Shared with GPIO C0 GPIOB7 I/O 8051 UART RXD or external IRQ3 interrupt input. Shared with GPIO B7 GPIOB6 I/O 8051 UART TXD or external IRQ2 interrupt input. Shared with GPIO B6 GPIOB5 I/O HIN input. Shared with GPIO B5 GPIOB4 I/O VIN input. Shared with GPIO B4 GPIOB3 I/O 8051 P1.3 or external IRQ1 interrupt input. Shared with GPIO B3 GPIOB2 I/O 8051 P1.2 or external IRQ0 interrupt input. Shared with GPIO B2 nd GPIOB1 I/O 2 slave IIC SDA2. Shared with GPIO B1 nd GPIOB0 I/O 2 slave IIC SCL2. Shared with GPIO B0 st GPIOA7 I/O 1 slave IIC SDA1. Shared with GPIO A7 st GPIOA6 I/O 1 slave IIC SCL1. Shared with GPIO A6 rd GPIOA5 I/O 3 slave IIC SDA or 8051 P1.1. Shared with GPIO A5 rd GPIOA4 I/O 3 slave IIC SCL or 8051 P1.0. Shared with GPIO A4 GPIOA3 I/O Key pad ADC input3 or IR detector input. Shared with GPIO A3 GPIOA2 I/O Key pad ADC input2. Shared with GPIO A2 GPIOA1 I/O Key pad ADC input1. Shared with GPIO A1 GPIOA0 I/O Key pad ADC input0. Shared with GPIO A0

10 11 12 13

(a) All GPIOs have Schmitt trigger input. (b) When use Slave IIC or 8051 P1.x (or UART), the external circuit need pull high(4.7k) (c) GPIOA3, GPIOA2, GPIOA1, GPIOA0 MAX input are +3.6v(=3.3v+0.3v) and the other GPIOs MAX input is +5v (5v tolerant PAD)

WT6702F Data Sheet v0.93

3. Selection Guide
Part NO. DPMS Detection UART 8K Flash Memory RAM 256 Byte PWM Output 2 Slave I C RTC IO Oscillator 8-bit ADC Package WT6702F_S240 V V V V 2 3 V 18max 32KHz Crystal/ RC OSC 4 selectable inputs 24-pin SOP WT6702F_S200 V V V V 1 3 V 14max 32KHz Crystal/ RC OSC 2 selectable inputs 20-pin SOP/SSOP WT6702F_S161 V V V V 1 2 V 11 max 32KHz Crystal/ RC OSC 2 selectable inputs 16-pin SOP

WT6702F Data Sheet v0.93

4. Functional Block Diagram

Turbo 8031 MCU

8K bytes code flash Internal 256 bytes SRAM 32K Oscillator RTC RC Oscillator Key Pad ADC Reset Processor Clock Processor Clock off & Wake Up Watchdog timer internal bus

8051 UART,Timer0, Timer1 1st SIIC

2nd SIIC

3rd SIIC HV DPMS Detector Interrupt Processor IR Detector

PWM 4 IRQ Processor GPIO Processor

w
DESCRIPTION
The WM8501 is a high performance stereo DAC with an integrated 1.7Vrms line driver. It is designed for audio applications that require a high voltage output along with enhanced load drive capability. The WM8501 supports data input word lengths from 16 to 24-bits and sampling rates up to 192kHz. The WM8501 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and stereo DAC in a 14lead SOIC package. The hardware control interface is used for the selection of audio data interface format, enable and de-emphasis. The WM8501 supports I2S, right Justified or DSP interfaces. Operating on separate analog and digital supplies the WM8501 offers very lower power consumption from the digital section, whilst supporting enhanced load drive from the analogue output.

WM8501

24-bit 192kHz Stereo DAC with 1.7Vrms Line Driver

FEATURES
Stereo DAC with 1.7Vrms line driver from 5V analogue supply Audio performance 100dB SNR (A weighted @ 48kHz) -88dB THD DAC Sampling Frequency: 8kHz 192kHz Pin Selectable Audio Data Interface Format I2S, 16-bit Right Justified or DSP 14-lead SOIC package 4.5V - 5.5V analogue, 2.7V - 5.5V digital supply operation

APPLICATIONS
STB DVD Digital TV

BLOCK DIAGRAM

WOLFSON MICROELECTRONICS plc

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Pre-Production, May 2006, Rev 3.1

Pre-Production

WM8501

PIN CONFIGURATION

ORDERING INFORMATION
DEVICE WM8501GED/V WM8501GED/RV TEMPERATURE RANGE -25 to +85oC -25 to +85oC PACKAGE 14-lead SOIC (Pb-free) 14-lead SOIC (Pb-free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PEAK SOLDERING TEMPERATURE 260C 260C

Note: Reel quantity = 3,000

PP Rev 3.1 May 2006 3

WM8501

Pre-Production

PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 NAME LRCLK DIN BCLK ENABLE VMID ROUT AGND AVDD LOUT DGND DVDD DEEMPH TYPE Digital input Digital input Digital input Digital input Analogue output Analogue output Supply Supply Analogue output Digital Supply Digital Supply Digital input Sample rate clock input Serial audio data input Bit clock input Enable input 0 = powered down, 1 = enabled Analogue internal reference Right channel DAC output Ground reference for analog circuits and substrate connection Positive supply for analog circuits Left channel DAC output Digital ground supply Digital positive supply De-emphasis select, Internal pull down High = de-emphasis ON Low = de-emphasis OFF Data input format select, Internal pull up Low = 16-bit right justified or DSP (Mode B) High = 16-24-bit I2S or DSP (Mode A) Master clock input DESCRIPTION

FORMAT

Digital input

MCLK

Digital input

Note: 1. Digital input pins have Schmitt trigger input buffers.

PP Rev 3.1 May 2006 4

SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

General Description
The SiI9185A is the first generation of TMDS switch device supporting Revision 1.3 of the HDMI Specification (HDMI Consortium; June 2006). With three HDMI inputs and a single output, the SiI9185A provides a low-cost method of adding additional HDMI ports to the latest Digital TVs. New DTVs can easily connect to the many HDMI sources coming on the market, including DVDs, STB, game consoles, PCs, camcorders, and digital still cameras. The SiI9185A is a fully HDMI compliant device providing a simple, low-cost method of retransmitting protected digital audio and video, giving end-users a truly all-digital experience. Built-in backward compatibility with DVI 1.0 allows HDMI systems to connect to any DVI 1.0 source. The SiI9185A provides additional integrated features to help lower system cost and provide enhanced features to the end consumer. To lower system cost, the SiI9185A provides a complete solution for switching sink-side HDMI signals. This includes DDC switching, individual HPD control, and 5V sense. The addition of these features eliminates additional external components, helping to lower cost. For source-side applications, the SiI9185A DDC switching can be bypassed with an external 4-channel I2C-bus switch (e.g., Texas Instruments PCA95445) to allow clock stretching. The SiI9185A is the first generation of device from Silicon Image to integrate the Extended Display Identification Data (EDID). The EDID is stored in on-board RAM that is downloaded from the system microcontroller during power up or initialization. The EDID is reflected on each of the three HDMI ports through the DDC bus. Flexibility is built in to allow mixing different EDID formats in an application. This allows elimination of up to three EDID ROMs while also saving board space. Finally, the SiI9185A provides a complete, simple solution to enabling Consumer Electronics Control (CEC) in a DTV. CEC is a single-wire bus that transmits remote control commands throughout a home network. The SiI9185A integrates both an HDMI-compliant I/O and Silicon Images CEC API. The CEC I/O meets all HDMI compliance tests and eliminates the need for additional external components, again saving board space. The CEC API manages reception and transmission of all CEC signals according to the CEC protocol and makes the information available to the system microcontroller. This significantly lowers the system-level control by the system microcontroller, simplifying firmware overhead. A very low power standby mode is available, allowing DTVs to meet industry low-power requirements such as Energy Star. During this mode both the CEC and EDID are still functional. Silicon Images SiI9185A uses the latest generation of TMDS core technology. These TMDS cores are guaranteed to pass all HDMI compliance tests.

Si C lic o C n on In on fid Im te su en a rn m ti ge al er al U E fo se le r P c O tr hi nl on lip y ic s s

SiI-DS-1016-0.80
2007 Silicon Image, Inc. CONFIDENTIAL

SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

Silicon Image, Inc.

Features
Three-input, single-output HDMI switch Integrated TMDS receiver and transmitter cores capable of receiving and transmitting 2.25 Gbps: Supports video resolutions up to 1080p, 60 Hz, 12-bit or 720p/1080i, 120 Hz, 12-bit Built-in adaptive equalizer provides long cable support even at deep-color resolutions Pre-emphasis in transmitter DVI 1.0, HDCP 1.1 and HDMI 1.3 compliant receiver and transmitter

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Built-in Consumer Electronics Control (CEC) support: Integrated EDID capability to lower system cost DDC switching on each input port simplifies board layout and lowers cost Individual control of Hot Plug Detect (HPD) for each port Control via local I2C bus 5V detect to help speed soft mute of audio during plug-in, plug-out conditions Stand-alone mode option: Acts as simple switcher No I2C control required in this mode Low-power standby mode to meet Energy Star and other power saving requirements 80-pin QFP package
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2007 Silicon Image, Inc. CONFIDENTIAL

Uses HDMI-compliant TMDS core for recovery and retransmission, unlike TMDS switches, which use high-speed analog switches and degrade TMDS signals

HDMI-compliant CEC I/O simplifies and lowers cost for adding CEC support to DTV Integrated CEC API lowers overhead requirements on system microcontroller, speeds design

SiI-DS-1016-0.80

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SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

SiI9185A Pin Mapping

DVCC18 AVCC18 AVCC18 AVCC33 I2CSEL/ INT RPWR0 DSDA0 R1XC+ DSCL0 R0X2+ R0X1+ R0X0+ 22 R0X2 R0X1 R0X0 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 80 R1XCDGND AGND AGND 26 HPD1 36

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R1X0 41 R1X0+ 42 43 44 AVCC33 R1X1 R1X1+ 45 AGND 46 47 48 49 R1X2 R1X2+ AVCC18 DSDA1 DSCL1 50

AGND R0XC+ R0XCAVCC18 HPD0 LSCL/ EPSEL[1] LSDA/ EPSEL[0] RESET# EXTSWING TxC TxC+ AGND Tx0 Tx0+ AVCC18 Tx1 Tx1+ AGND Tx2 Tx2+

80-Pin TQFP
(Top View)

51 52 53 54 55 56 57 58 59 60

RPWR1

CEC_D CEC_A

AVCC33

HPD2

AVCC18 R2XC-

R2XC+ AGND

DSCL2

RPWR2

DVCC18

AGND

DGND

TSCL

Figure 1. Pin Mapping

SiI-DS-1016-0.80

TPWR/ I2CADDR AGND

AVCC33

AVCC18

RSVDL

DSDA2

HPDIN

R2X0+

R2X1+

R2X2+

R2X0

R2X1

R2X2

TSDA

2007 Silicon Image, Inc. CONFIDENTIAL

SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

Silicon Image, Inc.

Functional Description
The SiI9185A provides a low-cost method of providing additional HDMI inputs to a DTV. System cost is reduced by integrating DDC and HPD switching along with integrated EDID. Feature enhancements like the embedded CEC API provide a simple method of adding CEC to a DTV without burdening the system microcontroller. Figure 2 and Figure 3 show the functional blocks of the device as applied to sink and source applications, respectively. Pin descriptions begin on page 20.

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Figure 2. System Architecture, Sink Application
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SiI-DS-1016-0.80

Silicon Image, Inc.

SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

Si C lic o C n on In on fid Im te su en a rn m ti ge al er al U E fo se le r P c O tr hi nl on lip y ic s s

Figure 3. System Architecture, Source Application
SiI-DS-1016-0.80
2007 Silicon Image, Inc. CONFIDENTIAL

SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

Silicon Image, Inc.

Block Level Functionality

The SiI9185A 3:1 HDMI 1.3 switch is used to select a single set of HDMI/DVI signals from one of three HDMI/DVI receiver-ports, and to generate a fully compliant HDMI/DVI stream as an output. It also provides DDC/HDCP, HPD, and +5V switching to allow full compliance to the HDMI/DVI specifications. The combination of dynamic equalizer and state-of-the-art DPLL can overcome signal distortion due to the long lengths of HDMI/DVI cables. SiI9185A-based switches can be cascaded many times to regenerate TMDS and HDCP signals.

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Figure 4. Functional Block Diagram As shown in Figure 4, the SiI9185A consists of five major blocks: Receiver block Transmitter block CEC Interface block EDID RAM block Configuration block

Receiver Block
The three HDMI/ DVI receive ports are defined as Port 0, Port 1, and Port 2. Each of the ports is terminated separately and equalized under the control of the receiver digital block and controlled by the local I2C bus. Port 0, Port 1, Port 2, or power down of all ports are selected by using the Port Select (PSEL[1:0]) signals. PSEL[1:0] can either be controlled by a register in I2C mode, or pins in stand-alone mode. The I2C Switch conveys bidirectional DDC/EDID and HDCP information. In order to comply with the HDMI/DVI and HDCP specifications, the SiI9185A also switches and relays information with correct timing from three bidirectional I2C Rx-ports to one bidirectional Tx-port. The HDCP switching and relaying operation is also done in the Receive block by monitoring the I2C/HDCP protocol to decide the right direction of signal transfer. The port selection signal is used to provide correct HDCP data flow between the selected Receiver and the Transmitter port.

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SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

Transmitter Block
The Transmit block consists of a fully compliant, HDMI 1.3 transmitter. This transmitter re-transmits the data received by the selected receiver port.

CEC Interface
The Consumer Electronics Control (CEC) Interface block provides CEC electrically compliant signals between CEC devices and a CEC master. It allows products to meet the electrical specifications of CEC signaling by translating the LVTTL signals of an external microcontroller (CEC host-side or Tx-side) to CEC signaling levels for CEC devices at the Rx-side, and vice versa. Additionally, a CEC controller compatible with the Silicon Image CEC API is included on-chip. This CEC controller has a high-level register interface accessible through the I2C interface which can be used to send and receive CEC commands. This controller makes CEC control very easy and straightforward, and removes the burden of having a host CPU perform these low-level transactions on the CEC bus. In order to use the high-level CEC API, the host must perform a calibration of the internal CEC clock inside the SiI9185A. This calibration is performed by setting the calibration bit, and then sending a 10ms pulse (1%) on the CEC_D signal input to the SiI9185A. The SiI9185A uses this pulse to calibrate an internal clock that is then used to generate all CEC timing to guarantee CEC compliance to the HDMI specification. This calibration must be repeated at time intervals corresponding to changes in temperature of 15C.

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EDID RAM Block Configuration Block
Figure 5. Standalone Mode Configuration
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2007 Silicon Image, Inc. CONFIDENTIAL

The EDID RAM block consists of 256 bytes of RAM that is shared by all ports. This means the timing information must be identical among all the ports if the internal EDID is used. Independent registers for the CEC physical address and checksum values for each port are also included, as these are unique to each port. On-board logic controls arbitration when reading the 256 bytes of EDID RAM, CEC physical address, and checksum values. This allows simultaneous reads of all ports from three different source devices if they are connected and attempt an EDID read at the same time. The internal EDID can be selected on a per-port basis using registers on the local I2C bus. For example: Port 0 and Port 1 can use the internal EDID, and Port 2 can use a discrete EEPROM for the EDID.

The Configuration block is used to configure and control the operation of the SiI9185A. The SiI9185A has two modes of operation: I2C and Standalone. In I2C mode, all functions of the SiI9185A are controlled and observed with I2C registers. All of these registers are accessible over the local I2C Interface. These registers are used to perform port select, HPD control, CEC control, EDID loading, and power-down control. In Standalone mode, all functions are controlled and observed by using pins on the SiI9185A. The mode is determined by the level of the I2CSEL/INT pin at the rising edge of RESET#. A high indicates I2C mode, and a low indicates Standalone mode. In Standalone mode, the SiI9185A operates independently, and has no need for an external microprocessor.

SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

Silicon Image, Inc.

Si C lic o C n on In on fid Im te su en a rn m ti ge al er al U E fo se le r P c O tr hi nl on lip y ic s s

Figure 6. I2C Control Mode Configuration

I2C Interfaces

There are five I2C interfaces in the SiI9185A. There is one local slave I2C port that is used to configure the operation of the SiI9185A in I2C mode. Three slaves are connected to the three DDC receive ports, and one master is connected to the DDC transmit port; these ports are used to transfer DDC and HDPC information. All of the I2C pads are 5V tolerant and compliant to the I2C specification.

Local Slave I2C Interface

The local I2C interface on the SiI9185A (pins LSCL and LSDA) is a slave interface capable of running up to 100 kHz. This bus is used to configure the SiI9185A by reading/writing to necessary registers. The local I2C interface of the SiI9185A consists of three separate I2C slave addresses. This means the SiI9185A will appear as three separate devices on the I2C local bus. The first of these addresses is used for PHY and Chip Control registers, is fixed, and can only be set to one of two values by using the I2CADDR pin. The other two addresses (used for CEC and EDID) have an I2C register programmable address mapped into the PHY and Chip Control register space, so the default value can be changed if there is a bus conflict with another device. Table 1. Control of the Default I2C Addresses with the I2CADDR Pin
I2CADDR=LOW 0xD0 0xE0 0xC0 PHY and Chip Control Registers (fixed) EDID Controller (programmable) CEC Registers (programmable) I2CADDR=HIGH 0xD4 0xE4 0xC4

The PHY and Chip Control I2C address is fixed at boot-up and cannot be changed. The EDID Controller I2C Address and the CEC Controller I2C Address each have a register associated with them that allows the address to be changed. See the SiI9181/9185 HDMI Switch Programmers Reference Guide for more information.

DDC Receiver Ports (Slave) and DDC Transmitter Port (Master) Interfaces

The DDC bus is an I2C interface used in the HDMI interconnection to facilitate bidirectional transfer of DDC/EDID information and perform the HDCP authentication process between source and sink devices. The SiI9185A includes three DDC slave I2C ports, one for each of the receive ports. These are used for direct connection to each of the upstream HDMI transmitters. The SiI9185A also includes a master I2C port for direct connection to the downstream HDMI receiver (Figure 3). The DDC ports support I2C transactions specified by the VESA Enhanced Display Data Channel Standard and supports I2C transactions needed for HDCP. The DDC master I2C port and the three DDC slave I2C ports comply with the Standard Mode timing of the I2C specification (100 kHz). Due to the relaying function in the SiI9185A, the I2C master in the transmit port does not support SCL clock stretching by the slave to which it is connected. This is not an issue when used in sink applications that use Silicon Image receivers because they do not perform any clock stretching. For other applications it should be confirmed that the sink receiver device that connects to the SiI9185A output does not perform clock stretching on the I2C bus. For source applications an external I2C switch (such as the NXP 9545A) can be used to bypass the master and slave DDC ports of the SiI9185A. This will eliminate the SCL clock stretching issue (see Figure 4). The SiI9185A will operate between an HDMI source and sink device, so DDC/EDID and HDCP transactions on the DDC bus must flow through the SiI9185A without causing information loss or timing margin degradation. The SiI9185A
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2007 Silicon Image, Inc. CONFIDENTIAL

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SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

analyzes and regenerates the DDC signal, making it possible to extend the cable length of I2C DDC by cascading multiple SiI9185As together.

Control Pins
The SiI9185A can operate in two distinct modes, depending on the state of the I2CSEL pin at the end of RESET#: Standalone mode, and I2C Control mode. In Standalone mode, the SiI9185A operates independently and has no need for an external microprocessor. The configuration of the switch is set using signals on the external control pins listed below, and after configuration, the switch operates independently. In I2C Control mode, the SiI9185A requires an external processor and is controlled over the I2C interface.

Si C lic o C n on In on fid Im te su en a rn m ti ge al er al U E fo se le r P c O tr hi nl on lip y ic s s

RESET# Control Pin I2CSEL/INT EPSEL1/LSCL and EPSEL0/LSDA
Table 2. Port Selection Using the EPSEL Pins
EPSEL1 0 0 1 1 EPSEL0 0 1 0 1 Port 0 Port 1 Port 2 Standby Mode SiI-DS-1016-0.80
2007 Silicon Image, Inc. CONFIDENTIAL

The system reset pin (RESET#) is an active-low input. When RESET# is low, all digital logic is reset including the I2C interfaces. When RESET# is high, the SiI9185A operates in normal mode. Two pins are used to configure bootstrap options on the rising edge of RESET#: I2CSEL/INT and I2CADDR/TPWR. The I2CSEL/INT is sampled on the rising edge of RESET# to determine the operating mode. The I2CADDR/TPWR pin is sampled on the rising edge of RESET# to determine the base address of the I2C interface. These pins are discussed in the sections that follow.

The dual-purpose I2CSEL/INT pin acts as a configuration input pin for mode selection during the period when RESET# is true (low), and as the interrupt (INT) output during normal operation. The level on the I2CSEL/INT pin is latched when the RESET# signal transitions from low to high. If the I2CSEL/INT value is high on the rising edge of RESET#, the SiI9185A comes up in I2C Control mode. If the I2CSEL/INT value is low at the rising edge of RESET#, the SiI9185A comes up in Standalone mode and the EPSEL[1:0] pins are used as the external port select pins. Note that when I2CSEL is low at the rising edge of RESET#, the local I2C is disabled from that time, but the contents of the local I2C registers are not lost. After RESET# is deasserted (goes high), the I2CSEL/INT pin becomes the interrupt output pin (INT). When interrupt conditions are met and the particular interrupt is enabled, the INT signal goes low indicating to the host that an interrupt has occurred and that actions are needed.

The EPSEL1/LSCL and EPSEL0/LSDA pins are dual-function pins, and their function depends on whether the SiI9185A is in Standalone mode or in I2C Control mode. In Standalone mode, these pins become the external port selection pins EPSEL[1:0]. In I2C Control mode, the EPSEL1/LSCL becomes the I2C Interface clock signal LSCL, and the EPSEL0/LSDA pin becomes the I2C Data signal LSDA. The receive port is selected externally using the EPSEL[1:0] pins in Standalone mode, or internally using I2C registers (I2C Control mode). When I2CSEL is high at the end of RESET#, the receive port is selected by the I2C register IPSEL[1:0] (0xD0: 0x08). When I2CSEL is low at the end of RESET#, the receive port is selected using the external pins EPSEL[1:0] as shown in Table 1, and the local I2C interface is disabled.

SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

Silicon Image, Inc.

Normal and Standby Modes

There are two power modes: P0 for Normal mode and P1 for Standby mode. The Normal mode, P0, is enabled when one of three RX ports is selected to provide audio/visual stream and HDCP/DDC information to the TX port as shown in Table 2. In Normal mode, all power supplies (AVCC33, AVCC18, and DVCC18) must be applied. In P0, all of the functional blocks are active: PLL, data-paths, local I2C and DDC relaying, and CEC. Setting PSEL[1:0] = 11 sets the SiI9185A into low-power standby mode (P1). In P1, all of the receive ports transition to the low-power state and the Tx outputs are disabled (Hi-Z). The purpose of P1 is to make the SiI9185A alive to power the DDC and CEC interfaces only, while the data-path of the SiI9185A (analog and digital) consumes minimum power. The I2C and DDC relay require logic power (DVCC18), I/O power (AVCC33), and OSC power (AVCC18). Because none of the receive ports are selected in P1, the PLL does not get an input clock, and shuts itself down. In Standalone mode P1, the HPD outputs are deasserted (set to 0).

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I2CADDR/TPWR Control Pin CEC Transceiver Control Pins HPD Control Pin
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2007 Silicon Image, Inc. CONFIDENTIAL

The I2CADDR/TPWR pin is sampled on the rising edge of RESET# to determine bit two of the default base address for the I2C interface. If I2CADDR/TPWR is low on the rising edge of RESET#, the I2C interface address for the PHY and Chip Control registers is set to 0xD0, the I2C interface address for the EDID Controller is set to 0xE0, and the I2C interface address for the CEC Registers is set to 0xC0. If I2CADDR/TPWR is high on the rising edge of RESET#, the I2C interface addresses are set to 0xD4, 0xE4, and 0xC4, respectively. The actual address values in both modes are shown in Table 1 on page 8. Once RESET# goes high, the I2CADDR/TPWR pin becomes the normal output Transmit Power (TPWR). TPWR is an output from the SiI9185A that tells the transmit side that the selected receive port is actually connected. The switching time between RPWR0/1/2 and TPWR is determined by the PLL lock behavior and logic that detects the presence of a valid input signal (see RPWR[0:2](+5V) and TPWR(+5V) control pins on page 11 for a description).

The CEC (Consumer Electronics Control) interface is composed of the bidirectional signals CEC_D, CEC_A, and a local I2C interface. CEC_D is the CEC signal from a CEC Master (microcontroller), and CEC_A is an electrical speccompliant CEC signal connected to all CEC Slave devices. The CEC_A signal drives the CEC pins from all three HDMI/DVI Rx connectors at the same time. The CEC interface has two modes: CEC_D relay mode and CEC API mode. In CEC_D relay mode, the SiI9185A is simply a CEC transceiver, and all software must be implemented on the host CPU. In CEC API mode, the SiI9185A performs all the low-level CEC control, and the host CPU must read and write to high-level I2C registers to send and receive CEC commands. In CEC_D relay mode, the CEC interface only monitors the CEC signal direction and provides appropriate timing between events. In CEC API mode, the local I2C provides CEC commands to the CEC interface block to generate CEC signaling to the CEC_A port, and the local I2C monitors the CEC value in the register map.

The Hot Plug Detection (HPD) signal is provided in the HDMI/DVI connector to provide a signal to the host that the EDID is readable. In the SiI9185A there are three outputs for the receive side (HPD0, HPD1, and HPD2), and one input from the transmit side (HPDIN). HPDIN from the Tx port can be relayed to the selected Rx port, or the HPD[0:2] outputs can be set using registers. In Standalone mode, the HPD outputs of non-selected Rx ports are set to low, so no EDID transaction or HDCP authentication is initiated for non-selected ports until that port is selected. The default signal level of the HPD output is low and the high signal level is 3.3V CMOS (and is +5V tolerant). In internal SiI9185A applications, the HPDIN pin may not to be brought out as an external pin. In this case, the local I2C directly controls the HPD output of selected and/or non-selected ports. But in external HDMI switch applications, the HDMI receiver on the video processing board provides an HPD signal input to the HDMI switch board, and the HPD input is re-directed to one of the selected receive ports. In I2C Control mode, the state of the HPD pins is controlled by setting the HP_CTRL_x bits in the Hot Plug Detect Output Control register, where x is the channel number. Each of the HPD0, HPD1, and HPD2 signals is independently controllable. For example, all three signals could be high at the same time. HPD output pins have 1-k series resistors integrated to comply with the impedance requirement specified in version 1.3 of the HDMI Specification. Table 3 on page 11 shows the possible states of the HPD control signals.

SiI-DS-1016-0.80

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Table 3. Hot Plug Control Signal Levels
Condition No power to the SiI9185A. Example: TV unplugged. SiI9185A out of Reset in I2C mode SiI9185A in Standalone mode SiI9185A in I2C mode, register programming HPD[2:0] Level Low Low (default) Pass-through from HPDIN Four options: selected by the HP_CTRL_x bits: 0b00 = Low 0b01 = High (3.3V) 0b10 = Tri-state 0b11 = Pass-Through Low

SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

Si C lic o C n on In on fid Im te su en a rn m ti ge al er al U E fo se le r P c O tr hi nl on lip y ic s s

Port not selected in Standalone mode

Note that to be HDMI compliant, each HPD Output is ANDed with its respective RPWR input. Hence a given HPD Output pin can only reflect a High state when the RPWR input of that port detects a High input (and the appropriate HP_CTRL_ bits are set to 01b, or they are set to 11b with the HPDIN signal being detected as High).

RPWR[0:2](+5V) and TPWR(+5V) Control Pins

The three RPWR (+5V) input signals on the receive side of the SiI9185A (RPWR0, RPWR1, and RPWR2) indicate that an HDMI cable is connected and 5V is electrically present. The PWR(+5V) signal on the transmit side of the SiI9185A (TPWR) notifies the receiving device that the transmit port has this 5V present. When the selected receive port is actually connected to a source device (a DVD player, for example), determined by monitoring the active ports RPWR[0:2](+5V) signal, then the transmit port of the SiI9185A sends the receiver-present signal (TPWR) to the HDMI receiver on the video processing board. The RPWR(+5V) signal of the selected Rx port, (RPWR0, RPWR1, and RPWR2) is transferred to TPWR under the control of PSEL[1:0] signals, which can come from registers in I2C Control mode, or pins in Standalone mode. The TPWR signal to the transmit port is pulled low for a period of 1 S when the port selection is changed. After this time, it follows the state of the newly selected port. RPWR input pins have internal pull-down resistors. When a port is not used, simply leaving them unconnected is sufficient.

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2007 Silicon Image, Inc. CONFIDENTIAL

SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

Silicon Image, Inc.

Embedded EDID
The SiI9185A embeds 256 bytes of RAM for EDID and used to eliminate the discrete EEPROM EDID from the system.
Select the input and control the SiI 9185 2 using either SEL 0/1 or the I C interface from the microcontroller

Si C lic o C n on In on fid Im te su en a rn m ti ge al er al U E fo se le r P c O tr hi nl on lip y ic s s

H D M I 0 +5V TMDS 0 HPD0 DDC0 MicroController H D M I 1 CEC_A +5V TMDS 1 HPD1 DDC1 SiI 9185A CSCL/ CSDA TPWR TMDS _Out HPDIN DDC_Out SiI 9011/ SiI 9013/ SiI 9025/ SiI 9125 H D M I 2 +5V TMDS2 HPD2 DDC2 EDID Optional EDID to support EDID different from Port 0 and Port 1

CEC_D SEL 0 SEL 1

Optional 5V detection output to Audio DAC for muting

Figure 7. EDID in the SiI9185A

EDID Emulation Function

All of the HDMI input ports have a DDC interface consisting of DSDA# and DSCL# where # is the port number. The SiI9185A device incorporates the function of an HDMI 1.3 compliant EDID in internal registers. The first block must conform to the VESA EDID specification. The second block must conform to the CEA-861D specification. The SiI9185A supports two blocks of EDID, each 128 bytes long. Table 4 shows the layout of the EDID block as it appears to each of the DDC interface controllers. Table 4. Layout of the EDID Blocks
Block # 0 1 Description Length DDC I2C Slave Address 0xA0 0xA0 Offset Address Range 0x00 0x7F 0x80 0xFF

EDID 1.3 according to VESA EDID extension according to the CEA 861 specification

128 bytes 128 bytes

The host writes the desired information into the EDID memory through the local I2C interface.

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SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

EDID Emulation Function Using RAM

The EDID is stored in 256 bytes of on-chip RAM. The SiI9185A contains I2C distributor/arbiter logic to ensure that the EDID can be read by all three DDC input buses simultaneously. The EDID memory provides identical information to each DDC channel except for the following: The CEC physical address for each channel. The location of this physical address in the EDID memory is specified by the contents of the CSCPA_ADDR register (0xE0:0x08) in the EDID controller. When the EDID memory is loaded through the local I2C controller, the CEC physical address contains the value for Channel (Port) 0. When the EDID controller detects that DDC for Channel 1 or Channel 2 is trying to read the CEC physical address location, it automatically replaces the information with the actual CEC1 or CEC2 physical address values stored in the CEC Physical Channel Address registers. Checksum. The checksum is always stored in the last register address for the EDID space (location 0xFF). When the EDID memory is loaded through the local I2C controller, the checksum value (location 0xFF) contains the value for Channel (Port) 0. However, the checksum is different for each channel due to the difference in physical CEC addresses for these channels. The host firmware stores different checksums for channels 1 and 2 in two different locations in the EDID controller registers. When the EDID controller logic detects that the DDC for a particular channel is reading the checksum, it responds with the value in one of the two registers, based on the inquiring port. Figure 8 shows a block diagram of how the EDID function is emulated using RAM.

Si C lic o C n on In on fid Im te su en a rn m ti ge al er al U E fo se le r P c O tr hi nl on lip y ic s s

Figure 8. EDID Emulation Using RAM
SiI-DS-1016-0.80
2007 Silicon Image, Inc. CONFIDENTIAL

The EDID contains the CEC physical address and must be loaded before enabling the CEC function. Additionally, HOTPLUG must be controlled to guarantee proper EDID and CEC operation by the host. The basic flow for loading the EDID into SiI9185A is shown below: 1. Power up the system. 2. Reset the SiI9185A. 3. Load the EDID for Port 0 into the SiI9185A. 4. Write the CEC physical addresses for Port 1 and Port 2. 5. Write the checksum values for Port 1 and Port 2. 6. Calibrate the CEC clock if using the CEC API. 7. Initialize the CEC registers if using the CEC API. 8. Enable DDC and CEC for all ports. 9. Write the registers to set HPD0, HPD1, and HPD2 high (now the host can read the EDID).

SiI9185A 3:1 HDMI 1.3 Switch Preliminary Data Sheet

Silicon Image, Inc.

CEC API Control

There is hardware assistance in the SiI9185A for CEC control that makes the software development for CEC much easier. CEC control has been implemented according to the internal Silicon Image CEC API (CPI ) specification. The CEC signal has two modes of operation: 1. Pass-through mode: In this mode, an external microcontroller can control the CEC level by using the CEC_D pin. The CEC API function in the SiI9185A is not used. 2. CEC API mode: In this mode, the SiI9185A performs decoding when acting as a follower, and a high-level command interface when acting as an initiator. Pass-through mode is engaged under the following conditions: When the SiI9185A is working in Standalone mode, or When the SiI9185A is working in I2C Control mode but the CEC enable bit is set to 0 (offset 0x08 bit 6)

Si C lic o C n on In on fid Im te su en a rn m ti ge al er al U E fo se le r P c O tr hi nl on lip y ic s s

CEC Reference Clock Calibration CEC Programming Interface (CPI)
14
2007 Silicon Image, Inc. CONFIDENTIAL

An on-chip ring oscillator is used to send and receive CEC data while meeting the CEC timing specification. However, the ring oscillator frequency can vary on a per device basis, based on manufacturing variables. Therefore, it is necessary to calibrate this internal ring oscillator by applying an externally driven pulse of 10 ms to the CEC_D pin. The procedure for applying this calibration signal is: 1. The host processor should set the CEC_D pin high before starting the calibration cycle. 2. The host processor starts the calibration cycle by setting the CALIB bit in local I2C offset 0x09 bit 0 to 1. This bit is self-resetting. 3. The host processor should wait for at least 100 ns after writing the CALIB bit. 4. The host processor should then cause the CEC_D pin to go through a high-to-low transition. The signal should stay low for a period of 10 ms 1%, and then transition back high. 5. At this point calibration is complete. 6. The calibration cycle will be repeated each time the host writes a 1 to the CALIB bit. A counter is used to count the number of ring oscillator clocks in this 10 ms pulse, and the frequency of the ring oscillator is determined from this count. This is used as the time base to accurately send and receive CEC commands according to the CEC specification. Note that unless the calibration pulse is properly applied to the SiI9185A and the calibration cycle is properly completed, the CEC logic will NOT operate correctly. The host should complete the calibration cycle before setting the CEC enable bit in the local I2C. The oscillator used in the CEC timing mechanism may vary slightly with temperature. It is recommended that as a precaution the CEC reference clock calibration process be repeated for every 15C of change. For example, it may be periodically recalibrated approximately every 10 minutes. In standalone applications where CEC-relay mode is used, the incoming CEC timing is measured using the internal oscillator clock to reproduce the correct output timing. For example, if the START period of CEC_D is measured to be some number of internal oscillator clocks, that number is used as the basis to re-shape the CEC output timing. Therefore, in CEC-relay mode a calibration pulse is not required.

The CEC application solution involves both low-level and a high-level components. For low-level components, the lowlevel CEC protocol is handled by the slave I2C interface of the SiI9185A. For high-level components, the Silicon Image CEC software source code allows command strings to be exchanged over the I2C interface as discussed above. For development, Silicon Image provides Windows-based software tools, including a kit that allows a PC to be used to generate I2C commands over any USB 1.1-capable port. The I2C register set used for this solution is referred to as CEC Programming Interface or just CPI. This standard register set is used across all Silicon Image devices and applications, both software and hardware.

SiI-DS-1016-0.80

Conceptual

RT8110

Wide Range Input Voltage Simple Synchronous DC/DC Converter

General Description
The RT8110 is a single power supply PWM DC-DC controller designed to drive N-MOSFET in a synchronous buck topology. The IC integrates the control, output adjustment, monitor and protection functions in a small 8-pin package. The RT8110 uses an internal compensation high DC gain voltage mode PWM control for simple application design. An internal 0.8V reference allows the output voltage to be precisely regulated for low voltage requirement. A fixed 400kHz oscillator reduces the component size for saving board space. The RT8110 features over current protection, and under voltage lock-out. The output current is monitored by sensing the voltage drop across the Low side MOSFET's RDS(ON), which eliminates the need for a current sensing resistor.

Features

Wide Input Operation Voltage 5V to 23V 0.8V Internal Reference Drive Two N-MOSFETs High DC gain Voltage Mode PWM Control Fast Transient Response Fixed 400kHz Oscillator Frequency Fully Dynamic 0 to 80% Duty Cycle Internal Soft Start Adaptive Non-Overlapping Gate Driver Over-Current Protection Under Voltage Lockout RoHS Compliant and 100% Lead (Pb)-Free

Applications

Ordering Information
RT8110 Package Type V8 : SOT-23-8 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)

Motherboard Power Regulation for Computers Subsystems Power Supplies Cable Modems, Set Top Boxes, and DSL Modems DSP and Core Communication processor Supplies Memory Power Supplies Personal Computer Peripherals Industrial Power Supplies 5V-Input DC-DC Regulators Low Voltage Distributed Power Supplies

Pin Configurations
(TOP VIEW)
UGATE PHASE LGATE 5 4 VCC GND 6 3 FB

Note : RichTek Pb-free and Green products are :

RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

8 1 BOOT

7 2 DRIVE

Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating.

Marking Information
For marking information, contact our sales representative directly or through a RichTek distributor located in your area, otherwise visit our website for detail.

SOT-23-8 Note : There is no pin1 indicator on top mark for SOT-23-8 type, and pin 1 will be lower left pin when reading top mark from left to right.

DS8110-01C March 2007

www.richtek.com 1

RT8110
Typical Application Circuit

Conceptual

D1 MA732

V IN
+

C1 1uF

RT8110 4 VCC BOOT 1 UGATE 7 2 DRIVE PHASE 8 LGATE 5 6 GND

C2 0.1uF MU

C3 1uF

C4 470uF

L1 5uH V OUT 2.5V C5 1000uF C6 10nF

R1 2k
En

Q1 2N2222

R2 10k

3 FB

Vhv

R3 120

R4 255

V IN
+

D1 MA732

C3 1uF C2 0.1uF MU L1 5uH

R2 20k R1 10
5V RT8110 4 VCC BOOT 1 C1 UGATE 7 1uF 8 2 DRIVE PHASE Q1 LGATE 5 2N7002 6 3 FB GND

V OUT 2.5V C5 1000uF

Chip Shutdown

C6 10nF

R3 120

R4 255

www.richtek.com 2

DS8110-01C March 2007

Conceptual Functional Pin Description

Pin No. 1 Pin Name BOOT Pin Function

RT8110

This pin provides ground referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive a logic-level N-MOSFET when operating at a single 5V power supply. This pin connects to the base of the external BJT(2N2222), which is designed to withstand to 23V and provides a regulated 5.3V voltage to VCC pin as the power of the PWM controller. The pin also can function as shut down with two different application circuits. The one can pull low the pin to gnd, the other can pull low drive to make VDD lower than POR threshold. This pin is connected to the PWM controllers output divider. This pin also connects to internal PWM error amplifier inverting input and protection monitor. This is the main bias supply for the RT8110. This pin also provides the gate bias charge for the lower MOSFET gate. The voltage at this pin is monitored for power-on reset (POR) purpose. Connect LGATE to the PWM controllers lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. Signal and power ground for the IC. All voltage levels are measured with respect to this pin. Connect UGATE pin to the PW M controllers upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. This pin is used to monitor the voltage drop across the lower MOSFET for over-current protection.

DRIVE

VCC

5 6 7 8

LGATE GND UGATE PHASE

Function Block Diagram

DRIVE VCC VCC V CC Regulator 0.8V REF 0.5V
+

PowerOn Reset POR UVP Soft-Start and Fault Logic S1L OC

IOC R OC
+ + PH_M

PHASE

SSE SS FB
+ +Gm -

1.5V UGATE BOOT LGATE GND

+ + -

PWM

Gate Control Logic

VCC

Oscillator

DS8110-01C March 2007

www.richtek.com 3

AO4459 P-Channel Enhancement Mode Field Effect Transistor

General Description
The AO4459 uses advanced trench technology to provide excellent RDS(ON) with low gate charge. This device is suitable for use as a load switch or in PWM applications. Standard product AO4459 is Pb-free (meets ROHS & Sony 259 specifications). AO4459L is a Green Product ordering option. AO4459 and AO4459L are electrically identical .

Features
VDS (V) = -30V ID = -6.5A (V GS = -10V) RDS(ON) < 46m (VGS = -10V) RDS(ON) < 72m (VGS = -4.5V)

SOIC-8 Top View S S S G D D D D

G S

Absolute Maximum Ratings TA=25C unless otherwise noted Parameter Symbol VDS Drain-Source Voltage VGS Gate-Source Voltage Continuous Drain A Current Pulsed Drain Current B TA=25C Power Dissipation A TA=70C Junction and Storage Temperature Range Thermal Characteristics Parameter Maximum Junction-to-Ambient Maximum Junction-to-Ambient C Maximum Junction-to-Lead TA=25C TA=70C ID IDM PD TJ, TSTG

Maximum -30 20 -6.5 -5.3 -30 3.1 2 -55 to 150

Units V V A

W C

Symbol
A A

t 10s Steady-State Steady-State

RJA RJL

Typ 33 62 18

Max 40 75 24

Units C/W C/W C/W

Alpha & Omega Semiconductor, Ltd.

PHKD13N03LT
M3D315

Dual TrenchMOS logic level FET

Rev. 01 23 June 2003 Product data

1. Product prole
1.1 Description
Dual N-channel enhancement mode eld-effect transistor in a plastic package using TrenchMOS technology. Product availability: PHKD13N03LT in SOT96-1 (SO8).

1.2 Features
I Low gate charge I Low on-state resistance I Surface mount package I Fast switching.

1.3 Applications
I Portable appliances I Lithium-ion battery chargers I Notebook computers I DC-to-DC converters.

1.4 Quick reference data

I VDS 30 V I Ptot 3.57 W I ID 10.4 A I RDSon 20 m

2. Pinning information
Table 1: Pin 1 2 3 4 5,6 7,8 Pinning - SOT96-1 (SO8), simplied outline and symbol Description source1 (s1) gate1 (g1) source2 (s2) gate2 (g2) drain2 (d2) drain1 (d1)
1 Top view 4
MBK187

Simplied outline
8 5

Symbol
d1 d1 d2 d2

SOT96-1 (SO8)

MBK725

DC-DC 12V to 5V RT8110 VCC ON OFF

+12V +5V/ Standby+5v

POWER SUPPLY CONNECTOR

TUNER_I2C
IF+/IF-

MT35 BLOCK DIAGRAM

V2.0

8051 MCU 15 KEY 9 POWERON 11 STANDBY 14 IR

EEPROM M24C16MN

TUNER

SAW-Sif

SAW-Vif

IF amplif ier

DVB-T demodulat or

PARALLEL TS PARALLEL TS CI CARD PARALLEL TS

I2C

CI function Chip

Main Chip
KEY BOARD 152 KEY 93 IR

205 SCL 206 SDA

132 TV_CVBS 164 SIF

SERIAL TS PANEL

FLASH 32Mbit

LV DS

LVDS To TTL 386

TTL

DDR 32Mb x16

62 OSCL1 63OSDA1 73 HDMI_5V 79 RX0_CB 80 RX0_C 81 RX0_0B 82 RXO_0 83 RX0_1B 84RXO_1 85 RX0_2B 86 RX0_2 205 DDC_SCL 204 DDC_SDA

104 R 98 B 102 G 96 VSYNC 97 HSYNC

120 Y_IN 121 Pb_IN 123 Pr_IN 173 YPbPr_L 174 YPbPr_R 176 VGA_R 177 VGA_L

170 SCT_R_IN 171 SCT_L_IN 116 SCT_R 108 SCT_G 114 SCT_B 149 SCT_FS 107 SCT_FB 187 SCT_R_OUT 189 SCT_L_OUT

LVDS Broken line is option for TTL interface panel! PRE AUDIO AMP

201 SPDIF _OUT

129 CVBS 172 R_IN 173 L_IN 126 SY 125 SC

185 HP_R_OUT 186 HP_L_OUT

R/L

CEC COMMAND HDMI SWITCH O/P

EDID EDID EDID

AUDIO AMP

HDMI1

HDM2

VGA

YPbPr

SCART

SPDIF

HEAD PHONE

4
TUNER_5V

1
L108 30R
R145 12K

Z100

AV_5V

TUNER_5V MT5133-GPIO-AD R153 0R

ATV-IF-AGC D110 LL4148

C137 0.1U

GND E 74LVC1G66GV

C138 0.1U

VCC

ANALOG_IF

6V3

C2 47U

NC/RFAGC

XTALOUT

NC/GND1

NC/GND2

ANTPWR

IFOUT2

IFAGC

GND1

U101

IFOUT1

C139 0.1U

TUNER_5V

SDA

NC1

SCL

R124 100R R125 100R

FAT_IN5V-OUT RF-AGC FAT_IN+

R139 6K8

R148

R132

NC/0R

RF-AGC C129 0.1U

R140 6K8

R141 22K

E
R135 R127 R126 C124 22P C125 22P 4K7 100R 100R TUNER_SCL0_5V D101 BA982 IF_AGC
C B E

C119 NC/0.01U

D103 BA982
R137 220K

TUNER_SDA0_5V
R123 0R

X100

Q102 BC847C

X102 IN/GND OUT1 OUT2 GND IN

R101 330R

R147 NC/100K

R100 680K

THIS DRAWING CANNOT BE COMMUNICATED TO UNAUTHORIZED PERSONS COPIED UNLES S PERMITTED IN WRITING

C110 0.22U

L103 120R C122 C102 100U TUNER_5V 6V3

0.01U

BA982 L100 1UH

C B E

TV_CVBS

SIF2

SIF1

OP2

AGND

VAGC

TAGC

AFC

VPLL

CVBS

REF

R120

IN/GND

Q105 2N7002 TUNER_SDA0 DV33

TUNER_SDA0_5V

R111 2K2

C128

B
R829 10K Q104 2N7002 TUNER_SCL0 DV33

C107 390P

R119

0.01U C108

C117

TUNER_SCL0_5V

L101 0.56UH

o f
R112 33R

OUT1

OUT2

GND

C118 1000P

AV_5V

T r
5V-OUT
NC

R118 NC

TDA9886T

R113 6K8

R129 75R
CVBS-OUT

C113 0.01U

C130

C123 0.01U

D102

C104 0.01U

R109 2K2

R108 5K6

L106 0

X101

E Q101 NC\BC847C

C120 1P5

R107 0R

R110 2K2

L C
1 2 3 4 5 U100 2 3 4 5 5K6 Index-Lab

P Q T
22K

R149 NC\0R

R152 47K

Q106 BC847C

C140 0.1U

R121

5V-OUT
R146 12K

ATV-IF-AGC

C109 0.01U

C111

1500P

C115 0.1U

C3 NC/0.01U 5V-OUT L102 120R BC847C Q100 TUNER_5V

C100 1U

C114 0.47U

C112

20P

R114 22K

C101 100U

6V3

SIOMAD

FMPLL

DGND

DEEM

VIF1

VIF2

AUD

TOP

SDA

OP1

AFD

SCL

R106 NC\6K8

R102 NC\180R

AV_5V

D100 BA592

0.47U

C105 1000P

R104 NC\47R

R103 NC\1K5

C116 0.01U

1000P

Q103 C124ET

C106 1000P

0.1U

CVBS0 C121 47P

75R R130

R131 0R GND_TUNER 0.01U

SIFP

C127 0.1U

L107 120R

R128 SIF 0R

C131

C B

R828 10K

SIFN C132 0.01U TUNER_SCL0_5V TUNER_SDA0_5V

R116 100R R115 100R R105

R117 NC

TUNER_SCL0
R138 220R NC\100R R93

OSCL0

NC/2K2

TUNER_SDA0
R94 NC\100R

OSDA0

C B E

R133 33R

SBU : SNAME TOCOM-Nr

TCL Thomson Electronics Singapore Pte. Ltd. 8 Jurong Town Hall Road #28-01/06 The JTC Summit SINGAPORE 609434 Tel (65) 63092900 Fax (65) 63092999 DRAWN CHECKED ON: BY: PAGE: OF : ON: BY:

DESIGNATION
DATE NAME DESCRIPTION 4-27-2007_10:59 Last modif DESIGNATION

Last saved :
8 7 6 5

1 FORMAT DIN A3

L12

+3V3SB 3K3 R819

5V_KEY 5V_KEY 5V_KEY NC/10K 10K R817 10K R833 +3V3SB_UP R816 33R X800 32K7
OSCI

R142 5VSB

OSCO

D801 LL4148

C821 20P

OIRI L824 STANDBY POWER_ON/OFF KEY L811 600R NC/EZJZ1V270RA R838 2 1 L821 L822 600R NC/600R NC/600R

600R

1 2 3 4 5 6 CEC R806 27K

C822 20P

DV33 R805 100R

CEC_IRQ

L823 5V_KEY

600R

7 8 9

NC/EZJZ1V270RA R839 2 1

P805

+3V3SB_UP

L820 600R

C871 1U

+3V3SB_UP

THIS DRAWING CANNOT BE COMMUNICATED TO UNAUTHORIZED PERSONS COPIED UNLES S PERMITTED IN WRITING

D
R807 +3V3SB_UP R809 10K

R815 4K7

HDMI_INT

33R 10K 33R 33R

R813 R834

SW_UPDATE_CTL SHORT_PROTECT HSYNC

R835

R812

+3V3SB

L809 120R

C825 0.1U

C826 0.1U

C824 1U

SBU : SNAME A TOCOM-Nr

TCL Thomson Electronics Singapore Pte. Ltd. 8 Jurong Town Hall Road #28-01/06 The JTC Summit SINGAPORE 609434 Tel (65) 63092900 Fax (65) 63092999 DRAWN CHECKED ON: BY: PAGE: OF : ON: BY:

R144 4K7

o f
C802 1U U811 RT9166 2
OUT IN

+3V3SB_UP

T r
U810
OSCO OSCI

1 2 3 4 5 6 7 8

OSCO OSCI VSS

VDD AD0

NRST

SCL1

13 12 11 10 9

R824

33R 33R 33R

STANDBY

C820 0.1U

AD3/IR

PWMI

SDA1

RXD/IRQ3 TXD/IRQ2 HIN

SCL2

CEC_IRQ

SDA2 VIN

L C
NC/10K R810 16 15 14 R820 R823 R825 R814 Index-Lab

C823 0.1U

10K

C876 NC\1000P C875

P Q T
C819 NC/100P +3V3SB_UP 10K R827 R826 1000P
OSCL0_SB

R22 0R

R10 0R

E
Q809 OSCL0 2N7002 Q810 2N7002

OSDA0

+3V3SB_UP

1 2 3 4 P802

10K

R822 R830

33R 33R

KEY OIRI_MCU

OSDA0_SB

C
C877 39P C878 39P

33R 33R

3V3SB_EN VSYNC

WT6702F

+3V3SB

Q4 BT3904 5VSB C872 100U 6V3

OIRI_MCU

C B E

R143 10K

OIRI

GND

C809 100U

6V3

GND

DESIGNATION
DATE NAME DESCRIPTION 4-27-2007_10:59 Last modif DESIGNATION

Last saved :
8 7 6 5

1 FORMAT DIN A3

+5V AV33 NC 12V/4A 11 0 NC/0 R8015 12V_IN R850 4K7 R851 10K P804 R8012 R8013

10 9

R80165VOUT 12V_IN
BL_ON/OFF

Back Light circuit

5V_PW
C

R849 10K

8 7 6 5 4 3 2 5V/2A 1

Q802 BT3904 +5V

R848 100R BL ON/OFF NC R847 L815 600R R9 SELECT NC/10K 1 2 3 4 5 R8001 NC R8003 0R 6 +3V3SB

R853 4K7

NC/1K R8011 10K R860 5V_KEY 0R 5VSB

BL_DIM

R844
C B E

R857 1K Q801 BT3904

R8 NC/47K

R846 10K

C827 1U

4K7 R856 R852 4K7

C B E

NC/1U Q803 BT3904

NC/A04803

C854 NC/1U

POWER CINCH

Q816 BT3904

C B E

R8010 4K7

R46 10K

R865 0R ON/OFF 12V_IN

12V 12V L14 200R

4 4

C863 NC

3V3SB_EN

L819 NC/200R L818 NC/200R 16V

7 P800 C862 NC/0.1U

C828 NC/0.1U

L813 30R 5V_PW

R843 4K7

LL4148 DIMMING D804

L814

600R

ON/OFF

R854 NC/0R

C853 0.1U

L15 200R C804 4U7 LD1117S33 U800 5V_OUTSIDE about 1mm GND BOOT PHASE DRIVE UGATE FB GND 8 7 6 5 R876 NC D808 LL4148 1 2 3 4 U807 PHKD13N03LT
G2 4 S2 3 G1 2 S1 1 D2B 5 D2A 6 D1B 7 D1A 8

LD1117S12 U803
4 4 VIN 3

AV12

R8006 10K

R898 47K

C831 0.1U

AV_5V

R894 100K

C859 0.1U C860 0.1U 5VSB C800 1000U 16V

5VSB 12V_IN C852

AV33 +5V 1K R845

NC/0.1U C829 Q800

1 S2 2 G2 3 S1 4 G1 8 D2A 7 D2B 6 D1A 5 D1B

12V

5V_OUTSIDE

C858

C810 NC/100U

5VSB

R92 2K2

R802 120R

R831 2R7

R832 2R7

C832 0.1U R866 22K

+5V L804 5VOUT 200R L805 200R C830 6V3 T Z805 3 C841 0.1U C806 100U U809 NC/KD1084-33
VIN ADJ/GND OUT

R887 2K2

2 C870 100U

R801 330R

VCC LGATE RT8110

1K2

C834

R871

0.01U

GND R869 10R C805 1U

R872

U808

R888 DV33 2K7

D810 LL4148

+5V NC C833

5VSB GND 0R R1 Q806 BT3904

C B E

U801 LD1117S33

GND

C THIS DRAWING CANNOT BE COMMUNICATED TO UNAUTHORIZED PERSONS COPIED UNLES S PERMITTED IN WRITING

R6 10K

GND

120R L816

C842 0.1U

0.1U

C843

R879

C867 0.1U

U806 MP1411 4 IN NC1 SW EN NC2 GND FB COMP SS 5 BS 2

C864 0.01U DV10 L801 15UH L13 200R 16V C874 4U7 C817 330U 12V

U802 LD1117S
VIN 3

U805 LD1117S50
VIN 3

AV_5V

AV9V R804 6R8 R884 1K C814 47U

R864 6K8

o f
C812 47U 6V3 R882 15K D803 SK24 R883 51K

U804 LD1117S25

T r
4 4
GND/ADJ1

NC R868

R889 4K7

AV33

R890 2K7

D811 LL4148

D805 LL4148

R858 2K7 CI_VCC

C840 0.1U

0.1U C837

R891 4K7

R897 680R

L800 15UH

DV33A C839 0.1U

L C
L802 200R DV33 AV25
4 4
GND/ADJ1

P Q T
D818 LL4148 3K9 R91 D809 LL4148 +5V 3K9 R886 +3V3SB R892 2K7 D812 LL4148 R893 4K7 CI_DV18 D817 LL4148
4 4
GND/ADJ1

C846 0.1U

R98 510R SHORT_PROTECT

GND/ADJ1

R2 NC/510R Q805 BT3904

OUT 2

PROT

D816 LL4148 Q807 BT3904

R4 10K

C B E

GND/ADJ1

100U 6V3

OUT 2

0.1U

C848 0.1U

12V

R896 8K2

R5 10K

VIN 3

R895 10K

C849

C B

C807

C803

6V3

C801 1000U

16V

D807 LL4148

R862 6K8

9 3 C869 0.1U 10

C845 0.1U

7 8 C866 120P NC R874 4K7 C835 0.01U

C865 0.1U

C868 0.01U

... ...
A

R885 6K2

DD-MM

... ... ...

C844 0.1U

... ... ...

SBU : TCLNO:
.............
TCL Thomson Electronics Ltd. B Building, TCL Tower, Nanhai Road Nanshan District, Shenzhen, Guangdong Tel +86-755-3331xxxx Fax +86-755-3331xxxx A

DD-MM DD-MM DD-MM

... ... Index-Lab

... ... DATE NAME DESCRIPTION 5-5-2008_15:52

...

DESIGNATION
DRAWN

Last modif ...........

C851

0.1U

R867 10R 12V C816 100U 16V

4U7

0.1U

R870 220R

OUT 2

VIN 3

3V9

D814

R859 4K7

C818 47U

6V3

C
D806 LL4148 R861 3K DDRV

R7 10K

R3 1K

4 4 OUT 2

GND/ADJ1

VIN 3

R863 3K

AV25

C811 47U

6V3

OUT 2

R803 5R1

C850 0.1U

C815 100U

16V

6V3

C813 100U

16V

Last saved :
8 7 6 5

ON: BY:
2

CHECKED ON: DD-MM-YY BY: ......

PAGE: OF :
1 FORMAT DIN A2

FAT_INL506 NC/0.22UH C527 NC/1000P

C513 1000P

C568 NC/20P

DV33

R134 4K7

FAT_IN+

R136 4K7

C514 1000P

C569 NC/20P

R508

TUNER_SCL0 TUNER_SDA0

AV12 AV12 L500 600R

Digital 1.8V Bypass Caps

DVDD12

C510 0.22U

C511 0.22U

R507

0R DV33

C517 0.1U

C519 0.1U

C516 0.1U

ADVDD33_1 REFTOP VCMEXT REFBOT

R150 100

MT5133-GPIO-AD

E
C506 27P

MT5131_IF_AGC

R500 1M

48 47 46 45 44 43 42 41 40 39 38 37

X500 27M

U502

1K R506 R503NC DVDD33

XTALO 1 2 3 4 5 6 7 8 9 10 11 12 AVSS33_3 AVSS33_2 XTALI XTALO AVDD33_2 ALC_IN VDD1.2 DGND1.2 TSDATA7 TSDATA6 TSDATA5 VDD3.3

XTALI

THIS DRAWING CANNOT BE COMMUNICATED TO UNAUTHORIZED PERSONS COPIED UNLES S PERMITTED IN WRITING

AVDD33

TS0INDATA7 TS0INDATA6 TS0INDATA5

1 2 3 4

R536 33R

DVDD12

8 7
DVDD33

TSDATA4 TSDATA3 TSDATA2 TSDATA1 TSDATA0 TSERR TSVAL TSSYNC TSCLK VDD3.3_1 DGND3.3 VDD1.2_1

6 5

RF_AGC IF_AGC VDD3.3_3 GPIO0 /RESET XTAL_SEL1 XTAL_SEL0 DGND3.3_1 VDD3.3_2 VDD1.2_2 HOST_SDA HOST_SCL

C525 0.1U

TS0INDATA4 TS0INDATA3

1 2 3 4

8 7 6 5

TS0INDATA2 TS0INDATA1

TS0INDATA0

33R 33R 33R 33R C504 120P/NC

TS0INVALID
TS0INSYNC TS0INCLK

o f
R550 R551 R552 R553 C505 120P/NC

DVDD33

DVDD12

C526 0.1U

C502 1U

R535 33R

MT5133

C524 0.1U

C503 1U

T r
13 14 15 16 17 18 19 20 21 22 23 24

L C
DVDD33 DVDD12 SIF_SDA SIF_SCL

36 35 34 33 32 31 30 29 28 27 26 25

R505 100R

R504 10K

R5010R

OSDA0 OSCL0

R502

P Q T
C500 1U DV33
IF_AGC

TUNER_SCL TUNER_SDA

C512 0.22U

AVDD33

DVDD12

R151 4K7

C518 0.1U

C515 0.1U

Digital 3.3V Bypass Caps

DVDD33

AVDD33_3 REF_TOP VCMEXT REFBOT IN+ INAVDD33_1 AVSS33_1 VDD1.2_3 DGND1.2_1 TUNER_SCL TUNER_SDA

C509

L501 600R

0.047U

C508 0.1U

C507 27P

C521 0.1U

C523 0.1U

C520 0.1U

MT5133_RESET

C522 0.1U

C501 1U

D
AVDD33

AV33

Analog 3.3V Bypass Caps

L502 600R

C
AV33 ADVDD33_1

L503 600R

120R

L510

SBU : SNAME A TOCOM-Nr

TCL Thomson Electronics Singapore Pte. Ltd. 8 Jurong Town Hall Road #28-01/06 The JTC Summit SINGAPORE 609434 Tel (65) 63092900 Fax (65) 63092999 DRAWN CHECKED ON: BY: PAGE: OF : ON: BY:

DESIGNATION
Index-Lab DATE NAME DESCRIPTION 4-27-2007_10:59 Last modif DESIGNATION

Last saved :
8 7 6 5

1 FORMAT DIN A3

CLOSE TO CI CONNECTOR
CI_VCC CI_VCC CI_VCC CI_DV33 DV33 CI_DV33 CI_DV18

CI_VCC

R525 NC/10K

R517 NC\10K

R519 NC\10K

R522 10K

R521 10K

R541 4K7

L508 600R C556 47U

LD1117S18

3 VIN

2 OUT

1GND/ADJ

C557 47U

CI_INPACK#

CI_IOIS16#

CI_IREQ#

CI_VS2#

CI_WAIT#

CI_POCE1#

6V3

+5V R516 10K R518 10K

+5V

+5V
CI_CD1# CI_CD2#

U500

4 4

C562 0.1U

+5V

CLOSE TO CI CONNECTOR

R520 10K

R523 10K

R524 10K

3.3V: 0.2W (60mA) 1.8V: 0.2W (100mA)

CI_VPP

CI_VCC

C561 0.1U

CI_CD1#

CI_VS1#

CI_CD2#

L509 NC/30R 4 5

L507 30R

L512 30R

CI_DV33

CI_AV33

CLOSE TO MT8295
L504 600R C533 0.1U C531 0.1U C532 0.1U C539 0.1U C538 0.1U C535 0.1U C534 0.1U C537 0.1U C540 0.1U C554 1U C1 C536 0.1U C541 0.1U C552 1U 1U

R526 10K

L505 600R

CLOSE TO MT8295
10P C530

CI_DV33

TS_DATAO

TS_VALIDO

TS_SYNCO

TS_CKO

R510 4K7

CI_GPIO0 CI_GPIO1

R511 4K7

CLOSE TO MT8295
C528 27P C529 27P DV33 R509 X501 1M NC/10K 27M

CLOSE TO MT8295

C THIS DRAWING CANNOT BE COMMUNICATED TO UNAUTHORIZED PERSONS COPIED UNLES S PERMITTED IN WRITING

Z501

RESET_N GND

CI_GPIO0 CI_GPIO1

HDMIED_WP HPDIN
CI_DV33 TS0INCLK TS0INSYNC TS0INVALID TS0INDATA0 GND TS0INDATA1 TS0INDATA2 TS0INDATA3 TS0INDATA4 CI_DV18 TS0INDATA5 TS0INDATA6 TS0INDATA7

HDMI_SEL YPBPR_SW_IN
GND CI_CD1# CI_D3 CI_OUTDATA3 CI_D4 CI_OUTDATA4 CI_D5 CI_OUTDATA5 CI_D6 CI_OUTDATA6 CI_D7

VCC33_1 D15 CE1# CE2# A10 VS1# OE# IORD# A11 IOWR# GND33_1 A9 A17 A8 A18 A13 A19 A14 A20 VCC33_2 WE# A21 READY A22 A16 A23 A15 GND33_3 A24 A12 A25 A7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

GPIO0 GPIO1 GPIO2 GPIO3 VCC33 T0CLK_I_ T0SYNC_I_ T0VALID_I_ T0DATA0_I_ GND33 T0DATA1_I_ T0DATA2_I_ T0DATA3_I_ T0DATA4_I_ VCC18 T0DATA5_I_ T0DATA6_I_ T0DATA7_I_ GPIO4 GPIO5 GPIO6 GND18 CD1# D3 D11 D4 D12 D5 D13 D6 D14 D7

C549 10P

o f
4K7 R514
CI_WEB CI_DATA2 CI_CEB GPIO9 GPIO8 GPIO7 GND18_1 WP CD2# D2 D10 D1 D9 D0 VCC18_1 D8 A0 BVD1 A1 BVD2 GND33_2 A2 REG# A3 INPACK# A4 WAIT# A5 VCC33_3 RESET A6 VS2# 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

GPIO14 GPIO13 GND33_5 TS_SYNCO TS_DATAO TS_CKO TS_VALIDO VCC33_5 GPIO12 GPIO11 GPIO10 CI_OEB CI_DATA0 CI_DATA1 CI_INT AVSS18_PLL AVDD18_PLL AVSS33_XTAL XTALI XTALO AVDD33_XTAL RESETB CI_RB CI_CLE GND33_4 CI_ALE CI_DATA3 CI_DATA4 CI_DATA5 CI_DATA6 CI_DATA7 VCC33_4

U501

CI_PDD2 CI_PDD6 CI_PDD7 CI_VCC_EN CI_VPP33_EN CI_VPP5_EN GND CI_IOIS16# CI_CD2# CI_D2 CI_OUTDATA2 CI_D1 CI_OUTDATA1 CI_D0 CI_DV18 CI_OUTDATA0 CI_A0 CI_OUTSYNC CI_A1 CI_OUTVALID GND CI_A2 CI_REG# CI_A3 CI_INPACK# CI_A4 CI_WAIT# CI_A5 CI_DV33 CI_RESET CI_A6 CI_OUTCLK

T r
0R R513
CI_DV33

128 127 126 125 CI_TS_SYNCO 124 CI_TS_DATAO 123 CI_TS_CKO 122 CI_TS_VALIDO 121 CI_DV33 120 119 118 PROT 117 CI_PDD3 116 CI_PDD4 115 CI_PDD5 114 CI_POWE# 113 GND 112 CI_AV18 111 GND 110 CI_XTALI 109 CI_XTALO 108 CI_AV33 107 CI_RESET# 106 CI_OEB 105 CI_ALE 104 GND 103 CI_CLE 102 101 100 CI_INT 99 CI_POCE1# CI_RB 98 97 CI_DV33

4K7

OPWM1 OPWM2

L C
MTK_IC_RESET CI_CE1# 100R R543 C564 10P
CI_IORD#

P Q T
CI_VCC_EN CI_WE## 100R R545
CI_WE#

C544 0.1U

C542 0.1U

C551 1U

C543 0.1U

C545 0.1U

R527 NC/0R

C558 0.1U

C559

0.1U

CI_DV33

CI_DV18

C546 0.1U

C547 1U

C550 100U

CI_DV18

CI_AV18

VIN RT9711 EN/EN# 3 GND 2

VOUT FLG 1 U503

6V3

R538

R539

33R R540

33R

R554

120R

L511

R542

R512

C548 10P

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

CI_DV33 CI_OUTDATA7 CI_CE1## CI_CE2# CI_A10 CI_VS1# CI_OE## CI_IORD## CI_A11 CI_IOWR## GND CI_A9 CI_INSYNC CI_A8 CI_INDATA0 CI_A13 CI_INDATA1 CI_A14 CI_INDATA2 CI_DV33 CI_WE## CI_INDATA3 CI_IREQ# CI_INDATA4 CI_INVALID CI_INDATA5

MT8295

GND CI_INDATA6 CI_A12 CI_INDATA7 CI_A7

GND

C
P500 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

CI_CE1##

C566 10P

CI_IORD##

CI_OE## 100R R544

CI_OE# C565 10P CI_VCC CI_VPP

100R R547

CI_D3 CI_D4 CI_D5 CI_D6 CI_D7 CI_CE1# CI_A10 CI_OE# CI_A11 CI_A9 CI_A8 CI_A13 CI_A14 CI_WE# CI_IREQ#

CI_CD1# CI_OUTDATA3 CI_OUTDATA4 CI_OUTDATA5 CI_OUTDATA6 CI_OUTDATA7 CI_CE2# CI_VS1# CI_IORD# CI_IOWR# CI_INSYNC CI_INDATA0 CI_INDATA1 CI_INDATA2 CI_INDATA3

CI_OUTCLK

CI_IOWR## 100R R548

CI_IOWR#

CI_INVALID CI_INCLK CI_A12 CI_A7 CI_A6 CI_A5 CI_A4 CI_A3 CI_A2 CI_A1 CI_A0 CI_D0 CI_D1 CI_D2 CI_IOIS16#

CI_INDATA4 CI_INDATA5 CI_INDATA6 CI_INDATA7 CI_VS2# CI_RESET CI_WAIT# CI_REG# CI_OUTVALID CI_OUTSYNC CI_OUTDATA0 CI_OUTDATA1 CI_OUTDATA2 CI_CD2#

CI_VCC CI_VPP C567 R533 100R NC\0R R532 10P

B
CI_INPACK#

NC/0R R531

CLOSE TO MT8295
... ... ...
CI_INCLK

DD-MM

... ... ...

SBU : TCLNO:
.............
TCL Thomson Electronics Ltd. B Building, TCL Tower, Nanhai Road Nanshan District, Shenzhen, Guangdong Tel +86-755-3331xxxx Fax +86-755-3331xxxx A

DD-MM DD-MM DD-MM

100R R515

...
C563 10P

Index-Lab

... ... DATE NAME DESCRIPTION 5-5-2008_15:52

...

DESIGNATION
DRAWN

Last modif ...........

Last saved :
8 7 6 5

ON: BY:
2

CHECKED ON: DD-MM-YY BY: ......

PAGE: OF :
1 FORMAT DIN A2

LC616 1000P R600 0R R651 NC/0R R652 NC/0R PGND R653 NC/0R R602 0R R601 0R Near the C607 GND PGND 8 PW_GND 9 S_GND 7 STBY 11 NC3 5 NC1
10 NC2

C617 L+ C618 1 2 3 4 1000P P600 R+ C619 1000P GND 1000P

Y600

GND
1 2

F
GND

Near the C607

F
GND

GND U600 1 OUT1+ OUT1TDA7266

Near the Y600 PGND R622 AL1O 0 R621 NC/0R R620 2K2 LOUT

SPEAK-OUTL

GND

PGND

R624 100K

C610 4700P

E
R617 0

AR1O
SPEAK-OUTR

R619 GND R618 NC/0R 2K2 R623 100K

THIS DRAWING CANNOT BE COMMUNICATED TO UNAUTHORIZED PERSONS COPIED UNLES S PERMITTED IN WRITING

12V

12V R643 220R

R640 4K7

R639 4K7 C602 100U 16V

R641 4K7
B E C

Q608 GND BT3906

R642 1K

AMP_MUTE

o f
D600 LL4148 R625 4K7

HW_MUTE

T r
R644 10K D601 LL4148

L C
GND 12V R627 10K R628 10K R632 10K GND
C B E

P Q T
MUTE C612 1U 2 GND C611 0.1U C608 1U PGND R603 0R R648 0R C607 1000U L601 200R C615 0.1U L600 200R 16V PGND

15 OUT2+ ROUT R-

13 VCC2

12 IN2

14 OUT2-

6 MUTE

3 VCC1

4 IN1

C609 4700P

BT3906
E

Q607
C B

SS LOUT R631 NC 1 L+ 2 3 R+ 4 MUTE ROUT 5 6

BT3904 Q602

R630 1NC/0K

R647 10K

P601

16V C606 22U GND

GND GND

SBU : SNAME A TOCOM-Nr

TCL Thomson Electronics Singapore Pte. Ltd. 8 Jurong Town Hall Road #28-01/06 The JTC Summit SINGAPORE 609434 Tel (65) 63092900 Fax (65) 63092999 DRAWN CHECKED ON: BY: PAGE: OF : ON: BY:

DESIGNATION
Index-Lab DATE NAME DESCRIPTION 4-27-2007_10:59 Last modif DESIGNATION

Last saved :
8 7 6 5

1 FORMAT DIN A3

DV33

F
OSDA0 OSCL0 204 205 63 62 191 202 203 146 143 144 147 145 152 151 150 149 148 88 87 71 72

U203 OSDA0 OSCL0 OSDA1 OSCL1 OPWM0 OPWM1 OPWM2 VCXO XTALO XTALI AVDD33_SRV AVDD33_XTAL ADIN4 ADIN3 ADIN2 ADIN1 ADIN0 AVDD33_REG C_XREG ORESET_ OPWRSB

DV33 R209 1K T Z213 C201 220U

R211 NC

16V

R206 1K

OSDA1 OSCL1 BL_DIM OPWM1 MTK_IC_RESET OPWM2

OXTALO OXTALI AVCC_SRV AVDD33_XTAL KEY

MT5133_RESET POWER_ON/OFF

R200

180K PANEL_SLT SCART_FS_IN

E
R44 10K

R210 47K

GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13

D200 LL4148

207 208 209 59 60 210 211 212 214 215 216

C221 10P

C222 10P

PWRDET

C223 1000P

CI_PDD3 CI_PDD4 CI_PDD5 CI_PDD6 CI_PDD7 CI_POWE# CI_OEB CI_ALE CI_CLE

ORESET#

OXTALI

X200 60M
OXTALO

L214 0.82UH

R208 220R
B

Q202 BT3904

PWRDET AVDD33_REG C_XREG ORESET#

OPCTRL0 OPCTRL1 OPCTRL2 OPCTRL3 OPCTRL4 OPCTRL5

92 91 76 75 90 89

LVDSVDD_EN CI_INT AMP_MUTE BL_ON/OFF EDID_PRT DV33

C_XREG

R207 1R

DV33 R202 10K R203 10K MT5335PKU DV33

R201 4K7 R205 NC/10K

THIS DRAWING CANNOT BE COMMUNICATED TO UNAUTHORIZED PERSONS COPIED UNLES S PERMITTED IN WRITING

D
HDMI_INT
E

Q201 CEC
E

DV33 Z959 T DV33 R215

C
R38 NC/10K

C B E

NC/BT3904 R37 10K R40 0R

Z956

C247 0.1U

EDID_PRT

M24C16MN

T Z957

L212 600R

C206 1U

R39 NC/4K7

SBU : SNAME A TOCOM-Nr

TCL Thomson Electronics Singapore Pte. Ltd. 8 Jurong Town Hall Road #28-01/06 The JTC Summit SINGAPORE 609434 Tel (65) 63092900 Fax (65) 63092999 DRAWN CHECKED ON: BY: PAGE: OF : ON: BY:

C226 0.1U

C205 1U

o f
Z958 T 4K7 R217 33R
OSCL0
C

R36 NC/10K

Q206 OSDA0 C124ET

T r
0R R220 R216 U205 4K7 8 7 6 5 VCC WC E0/NC E1/NC E2/NC VSS 1 2 3 4 SCL SDA

NC/BT3904

L C
Z960 T Index-Lab

+3V3SB

P Q T
Adjust the power on timing

C203 4U7

R204 NC/10K

DV33

R214 10K

C204 1U

C224 0.1U

AVDD33_REG

C225 0.1U

B C

Q200 BT3904

L236 NC/200R

L235 200R

L210 600R

AVCC_SRV

L211 600R

AVDD33_XTAL

DESIGNATION
DATE NAME DESCRIPTION 4-27-2007_10:59 Last modif DESIGNATION

Last saved :
8 7 6 5

1 FORMAT DIN A3

U203 USB_VRT USB_DUSB_D+ AVDD33_USB AVDD12_USB 68 65 66 67 69 157 158 USB_VRT USB_DM USB_DP AVDD33_USB AVDD12_USB TP0 TN0 AVDD12_KADCPLL AVDD12_TVDPLL AVDD12_KHDMIPLL AVDD12_KAPLL AVDD12_SYSPLL AVDD12_KDMPLL AVDD12_DTDPLL 160 155 153 161 159 156 154 AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL

AV12

L217 600R

AV33
AVDD12_USB

L216 600R

AVDD33_USB

USB_VRT

R218 5K1

MT5335PKU

AV33 GND

L219 600R

C212 1U

U203 163 165

SIFP SIFN TS_VALIDO TS_CKO

164 166 167 195 194

SIFP SIFN AF TUNER_DATA TUNER_CLK

AVDD25_SADC AVSS25_SADC

AVDD25_SADC

RF_AGC IF_AGC

193 192

TS_DATAO TS_SYNCO

GND

MT5335PKU

U203 RX0_CB RX0_C RX0_0B RX0_0 RX0_1B RX0_1 RX0_2B RX0_2 79 80 81 82 83 84 85 86

o f
MT5335PKU

RX0_CB RX0_C RX0_0B RX0_0 RX0_1B RX0_1 RX0_2B RX0_2

AVDD33_HDMI AVDD12_CVCC

T r
EXT_RES OPWR0_5V 77 73 78 74 AVDD33_H AVDD12_CVCC

HDMI_5V

L C
AV25 L218 600R C229 1U

C213 1U

C230

P Q T
C252 C208 1U 0.1U GND
AVDD33_H

C210 1U

C251 0.1U

GND

AV12

L220 600R

AVDD12_CVCC

C255

C248 0.1U

0.1U

GND

AVDD25_SADC

AV12

L215 600R

AVDD12_PLL

C211 1U

C253 0.01U

C254 0.1U

C207 1U

C228

C249 0.01U

C250 0.1U

GND

U203

+5V
244 243 242 241 240 239 237 236 235 234 233 232 231 230 228 227 226 225 224 223 222 221 A0N A0P A2N A2P CK1N CK1P A3N A3P A4N A4P A5N A5P A6N A6P A7N A7P CK2N CK2P A8N A8P A9N A9P AVDD33_LVDSA AVDD33_LVDSB AVDD33_LVDSC AVDD33_VPLL 220 229 238 217 AVDD33_LVDS AVDD33_LVDS AVDD33_LVDS AVDD33_VPLL

T Z210 12V L232 NC/30R Q203 P209 C202 220U 5 3 1 6 4 2 16V C258 0.1U R219 10K
1 S1 2 S2 3 S3 4 G 8 D1 7 D2 6 D3 5 D4

A0N A0P A1N A1P A2N A2P CK1N CK1P A3N A3P A4N A4P A5N A5P A6N A6P CK2N CK2P A7N A7P

T Z212 VDD_PANEL

TP2 TN2

218 219

CI_POCE1#

L233 30R

MT5335PKU

A0N A0P

L200 EXC24C
1 2 4 3

AN00 AP00

C320 C321

10P 10P 39 AP00 10P 10P AP11 GND AP22 CLK11+ AP33 NC/0R GND P202

40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2

A1N A1P

L201 EXC24C
1 2 4 3

AN11 AP11

C322 C323

37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1

A2N A2P

L202 EXC24C
1 2 4 3

AN22 AP22

C324 C325

10P 10P R213

CK1N CK1P

L203 EXC24C
1 2 4 3

CLK11-C326 CLK11+C327

NC/0R

10P 10P

AV33 NC/1K R222 AV33 NC/1K

R223 PANEL_CTL2 AP44

A3N A3P

L204 EXC24C
1 2 4 3

AN33 AP33

C328 C329

10P 10P

A4N A4P

L205 NC/EXC24C
1 2 4 3

AN44 AP44

C330 C331

10P 10P

A5N A5P

L206 NC/EXC24C
1 2 4 3

AN55 AP55

C332 C333

10P 10P

A6N A6P

L207 NC/EXC24C
1 2 4 3

AN66 AP66

C334 C335

10P 10P

o f
GND

T r
R212 PANEL_CTL1 AP55 AP66 CLK22+ AP77 VDD_PANEL GND

L C
AN00 AN11 AN22 GND CLK11AN33 AN44 AN55 AN66 CLK22AN77 C260 0.1U GND

P Q T
GND GND
LVDSVDD_EN
C B E

C209 1U

AO4459 C259 0.1U

R221 100K

Q204 C143ZT

GND

DV33

R224 1K PANEL_SLT R232 NC R225 390R

C261 0.1U

GND

AV33 AV33 L221 600R

AVDD33_LVDS

AV33 AV33 L222 600R

AVDD33_VPLL

CK2N CK2P

L208 NC/EXC24C
1 2 4 3

CLK22-C336 CLK22+C337

10P 10P

C214 1U

C231 1U

C256 0.1U

A7N A7P

L209 NC/EXC24C
1 2 4 3

C232 1U

C220

C257 0.1U

AN77 AP77

C338 C339

10P 10P

GND

U203 POCE0# POOE# PDD0 PDD1 252 251 250 249 95 94 93 U0RX U0TX OIRI_MT5335

POCE0_ POOE_ PDD0 PDD1

U0RX U0TX OIRI

DV33

CI_RB CI_PDD2

L223 600R
253 1 256 255 254 JTMS JTRST# JTCK JTDO JTDI

245 248

PARB_ PDD2

C240 1U

R270 10K

3 4

NC PO2 PO1 PO0 CS# SO

PO6 PO5 PO4 PO3 GND WP#/ACC MX25L3205

14 13 12

DV33

GND MT5335PKU +5V R289 10K

5 6 7 8

R246 4K7

R235 1K

JTMS JTRST_ JTCK JTDO JTDI

U202 1 2 8 7 6 5 HOLD# VCC SCLK SI 16 15 POOE# PDD1

11 10 9

TVTREF#1 2 JTRST# 4 6 8 10 12 14 16 JTAG_DBGRQ 18 JTAG_DBGACK 20 R236 10K R237 10K R238 10K P203 17 19
C

1 3 5 7 9 11 13 15

POCE0# PDD0

R245 0R

Q3 BT3904 OIRI_MT5335

C B E

R90 10K

OIRI +5V

GND

AV33 USB_DUSB_D+ R233 10K

0R R2011 0R R2012

1 2 3

R234 10K

4 C36 1 2 12P C37 12P

U0TX

C262 0.1U

C263 0.1U

C234 1U

4 P201 GND

GND

DV33

DV10 DDRV_IC
U203 14 48 57 58 61 70 162 213 206 246 10 12 16 18 27 30 52 54 55 56 64 197 247 257

VCCK VCCK1 VCCK2 VCCK3 VCCK4 DVDD10 DVDD10_1 VCCK6 VCCK5 VCCK7

VCC2IO VCC2IO1 VCC2IO2 VCC2IO3 VCC2IO4 VCC2IO5 VCC2IO6 VCC2IO7 VCC2IO8 VCC2IO9 VCC3IO_3_2 VCC3IO_3_1 VCC3IO_3 E-PAD

o f
R244 4K7 Trap MODE ICE MODE TRAP MODE
4

GND

GND DV10

C235 1U

C264 0.1U

U0RX

T r
P200
OPWM2 AOBCK AOLRCK

L C
AOLRCK 0 1 OPCTRL4 1
3

P Q T
FRESET# JTDI JTMS JTCK JTDO R239 33R DV33 C265 0.1U C266 0.1U C237 1U DDRV_IC GND C236 1U C279 0.1U C278 0.1U C238 1U C239 1U GND

R89 4K7

C006 100U

C007 0.1U

C267 0.1U

C270 0.1U

C269 0.1U

C268 0.1U

C272 0.1U

GND

C277 0.1U

C276 0.1U

C275 0.1U

C274 0.1U

DV33 NORMAL MODE 0 0 0 0

C273 0.1U

OPWM2

AOBLK

C271 0.1U

6V3

GND

R240 4K7 R241 4K7 R242 NC\4K7

OPCTRL5 0

GND CORE RESET 1 US MT5335PKU

U204
MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8 MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 14 17 19 25 43 50 53 1 18 33 3 9 15 55 61 34 48 66 6 12 52 58 64 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 NC NC1 NC2 NC3 NC4 NC5 NC6 VDD VDD1 VDD2 VDDQ VDDQ1 VDDQ2 VDDQ3 VDDQ4 VSS VSS2 VSS1 VSSQ1 VSSQ2 VSSQ VSSQ3 VSSQ4 VREF 49

MEM_VREF
MEM_ADDR0 MEM_ADDR1 MEM_ADDR2 MEM_ADDR3 MEM_ADDR4 MEM_ADDR5 MEM_ADDR6 MEM_ADDR7 MEM_ADDR8 MEM_ADDR9 MEM_ADDR10 MEM_ADDR11 MEM_ADDR12

U203 RDQS0 RDQM0 RDQ0 RDQ1 RDQ2 RDQ3 RDQ4 RDQ5 RDQ6 RDQ7 RDQS1 RDQM1 RDQ8 RDQ9 RDQ10 RDQ11 RDQ12 RDQ13 RDQ14 RDQ15 MEM_VREF RCS# 11 13 9 8 7 6 5 4 3 2 17 15 19 20 21 22 23 24 25 26 53 46 47 36 40 43 37 44 38 42 35 45 39 41 32 31 33 34 51 49 50 RA0 RA7 RWE# RBA0 RA6 RBA1 RA5 RRAS# RA8 RA10 RA4 RCAS# RA12 RCKE RA11 RA9 RA3 RA1 RA2

RDQS0 RDQM0 RDQ0 RDQ1 RDQ2 RDQ3 RDQ4 RDQ5 RDQ6 RDQ7 RDQS1 RDQM1 RDQ8 RDQ9 RDQ10 RDQ11 RDQ12 RDQ13 RDQ14 RDQ15 RVREF0 RCS_

RA0 RA7 RWE_ RBA0 RA6 RBA1 RA5 RRAS_ RA8 RA10 RA4 RCAS_ RA12 RCKE RA11 RA9 RA3 RA1 RA2

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12

29 30 31 32 35 36 37 38 39 40 28 41 42

+1V3D

RDQ0 RDQ1 RDQ2 RDQ3

1 2 3 4

R271 47R

8 7 6 5

MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3

1 2 3 4

R287 75R

8 7 6 5

MEM_ADDR13

DDRV_IC

CLK CLK CKE

45 46 44

MEM_CLK0 MEM_CLK0# MEM_CLKEN MEM_CS# MEM_RAS# MEM_CAS# MEM_WE# MEM_DQS0 MEM_DQS1 MEM_DQM0 MEM_DQM1 MEM_BA0 MEM_BA1

RDQ4 RDQ5

1 2 3 4

R272 47R

8 7 6 5

MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7

1 2 3 4

R286 75R

8 7 6 5

RCLK0_ RCLK0

28 29

RCLK0# RCLK0

CS RAS CAS WE

24 23 22 21

RDQ6 RDQ7

LDQS UDQS

16 51

RDQS0 RDQM0

MT5335PKU

LDM UDM

20 47

RDQM1 RDQS1

R248 47R R249 47R R250 47R R251 47R

MEM_DQS0 MEM_DQM0 MEM_DQM1 MEM_DQS1

R254 75R R255 75R R256 75R R257 75R

MEM_ADDR12 MEM_ADDR11 MEM_ADDR9 MEM_ADDR8

1 2 3 4

R275 47R

BA0 BA1

26 27

8 7 6 5

RA12 RA11 RA9 RA8 GND

32M*16DDR

RDQ11 RDQ10

1 2 3 4

R273 47R

8 7 6 5

MEM_DQ11 MEM_DQ10 MEM_DQ9 MEM_DQ8

1 2 3 4

R285 75R

8 7 6 5

MEM_ADDR7 MEM_ADDR6 MEM_ADDR5 MEM_ADDR4

1 2 3 4

R276 47R

8 7 6 5

RA7 RA6 RCKE RA5 RA4 RCLK0 R259 22R MEM_CLK0 R258 22R MEM_CLKEN

+5V L224 600R R265 0R U200 8 7 0R R264 0R R266 6 5 R261 100R NC3 NC2 VIN GND 1 2 3 4

DDRV

VCNTL REFEN NC1 47U 6V3 C217 VOUT RT9199

R269 1K

MEM_WE# MEM_CAS# MEM_RAS#

1 2 3 4

R277 47R

L226 600R

8 7 6 5

RWE# RCAS# RRAS# RCLK0# R260 22R

MEM_CLK0#

MEM_CS# MEM_BA0 MEM_BA1 MEM_ADDR10

1 2 3 4

R278 47R

8 7 6 5

RCS# RBA0 RBA1 RA10

MEM_ADDR0 MEM_ADDR1 MEM_ADDR2 MEM_ADDR3

1 2 3 4

R279 47R

8 7 6 5

RA0 RA1 RA2 RA3

+5V

R301 2R7

DDRV R302 2R7 R303 2R7

4 4

o f
DDRV

L213 600R

T r
DDRV_IC C349 220U C315 100U C280 0.1U 16V 6V3 GND MEM_VREF C300 0.1U C301 0.1U GND +1V3D C295 0.1U C316 1U GND

L C
C284 0.1U C281 0.1U C282 0.1U C283 0.1U +1V3D C296 0.1U GND C288 0.1U C289 0.1U C294 0.1U C292 0.1U C293 0.1U

GND

P Q T
R268 100K MEM_VREF L225 600R C306 0.1U C305 0.1U R267 100K C314 +1V3D 16V 220U GND GND C286 0.1U C298 0.1U

RDQ9 RDQ8

RDQ15 RDQ14 RDQ13 RDQ12

1 2 3 4

R274 47R

8 7 6 5

MEM_DQ15 MEM_DQ14 MEM_DQ13 MEM_DQ12

1 2 3 4

R288 75R

8 7 6 5

C304 0.1U

+1V3D

MEM_CS# MEM_RAS# MEM_CAS# MEM_WE#

1 2 3 4

R280 75R

8 7 6 5

MEM_ADDR10 MEM_BA1 MEM_BA0

1 2 3 4

R281 75R

8 7 6 5

C285 0.1U

C287 0.1U

C349&C280 CLOSE TO PIN33 OF DDR

MEM_ADDR7 MEM_ADDR6 MEM_ADDR5 MEM_ADDR4

1 2 3 4

R282 75R

8 7 6 5

U201 LD1117S
VIN 3

GND/ADJ1

R262 110R

C302 0.1U

C215 4U7

OUT 2

MEM_CLKEN

R252 75R R283 75R

C200 100U GND

C303 0.1U

C216 1U

C297 0.1U

C299 0.1U

R263 120R

C291 0.1U

C290 0.1U

6V3

MEM_ADDR12 MEM_ADDR11 MEM_ADDR9 MEM_ADDR8 MEM_ADDR13

1 2 3 4

8 7 6 5

GND

R253 75R R284 75R

MEM_ADDR3 MEM_ADDR2 MEM_ADDR1 MEM_ADDR0

1 2 3 4

8 7 6 5

U203 VGA_L VGA_R YPBPR_L YPBPR_R AIN2_L AIN2_R SCT_L SCT_R AVDD33_AADC GND VIMD_AADC REFP_AADC GND 177 176 175 174 173 172 171 170 169 181 179 180 178 201 198 199 200 196 186 185 189 187 190 182 188 184 183 168

AIN0_L AIN0_R AIN1_L AIN1_R AIN2_L AIN2_R AIN3_L AIN3_R AVDD33_AADC AVSS33_AADC VMID_AADC REFP_AADC REFN_AADC

ASPDIF AOMCLK AOLRCK AOBCK AOSDATA0 AL1 AR1 AL2 AR2 AVDD33_KADAC0 AVDD33_KADAC1 AVSS33_KADAC0 AVSS33_KADAC1 ADAC_VCM AVDD33_DIG

ASPDIF
AOMCLK AOLRCK A0SDATA0

L234 600R

AOBCK

AL1O
AR1O AL2O AR2O AVDD33_ADAC0 AVDD33_ADAC1 GND GND ADAC_VCM AVDD33_DIG

MT5335PKU

AV33
AV33

AV33 L227 600R

AVDD33_AADC

GND

GND AV33
AV33

L228 600R

REFP_AADC

AV33
AV33

o f
C242 1U L229 600R C243 1U

GND

AVDD33_ADAC0

GND

C309 0.1U

T r
GND C308 0.1U GND GND

AV33

L C
L231 600R
AV33

AVDD33_ADAC1

GND

P Q T
ADAC_VCM

C311 0.1U

C307 0.1U

C246 1U

C313 0.1U

C219 4U7

C241 1U

C245 1U

GND GND
VIMD_AADC

GND

L230 600R

AVDD33_DIG

AV33

C244 1U

C310 0.1U

C218 4U7

C312 0.1U

GND

R906 33K C928 100P

AL1O

C900 NC/1U

R901 470R

R904 10K

R907 5K1

C902 47U 6V3

R908 NC/10R

SPEAK-OUTL

OPAVREF

R900 100K

C925 2200P

C929 NC

4 GND RC4558 VCC-

3 1IN+

2 1IN-

1 U901 1OUT

GND

GND GND

VCC+

2OUT

AV9V_REF C962 220U 16V

L902 600R

AV9V

AR1O

C901 NC/1U

R903 470R

R905 10K

C930 NC

OPAVREF

C912 1U

2IN+ 5

2IN6

R910 5K1 C927 100P

C903 47U GND 6V3

R913 NC/10R

GND

C926 2200P

R909 33K

GND

AV9V_REF R914 10K

OPAVREF

GND

+5V 10R L930 C9008 1U

ADCVA ADCVA

DV33 L931 30R

DACVL

o f

R9018 C9016 1U R9026 NC/33K 0 C9011 1U

L901 600R

C913 1000P

C9018 0.1U

R9025 NC/33K

T r
R9019 47K

C910 1U

C911 1U

10K R9023

BCLK DEEMPH ENABLE DVDD VMID ROUT AGND DGND LOUT AVDD

DACVL 11 10 9 8 C9014 0.1U

4 5 C9015 1U C9012 0.1U 6 C9013 0.1U 7

10K R9024

L C
DV33 AOLRCK 33R R9027 A0SDATA0 AOBCK 33R
A

DAC
U907 LRCLK DIN

P Q T
SPEAK-OUTR

R902 100K

DV33DV33

R9021 10K

R9020 10K 1 14 13 12 R9030 33R AOMCLK

10K/NC

R915 10K

MCLK

33R R9028 2 R9029 3

FORMAT

R9022 R9017 0

1U C9017 ADCVA

L900 600R

SCT1_AUL_OUT

WM8501

GND SCT1_AUR_OUT

C9010 0.1U

C9009 1U

C914 1000P GND

GND DV18-HDMI

DV33

D3V3L4

D108

R21 4K7

L9 600R

AV18-HDMI C38 C42 0.1U GND C43 0.1U

P901 RX2+ GND1 RX2RX1+ GND2 RX1RX0+ GND3 RX0RXC+ GND4 RXCNC1 NC2 DDCCLK DDCDA GND5 VCC HPD 1 2 3 4 5 6 7
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

C39 1U

0.1U

DV33-HDMI

GND R14 4K7 R15 4K7

R16 NC\4K7

R59 R18 R19 100R 100R

R20

100R

OSDA1 OSCL1 HDMI_5V

8 9 10 11 12 HPD1 13 14 15 16 17 18 19 +5V_HDMI1 CEC-IN R42 R41 NC\0R NC\0R HDMI1_SCL HDMI1_SDA

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AGND7 RXC2+ RXC2AVCC18D HPD2 AVCC33C CEC-A CEC-D RPWR1 DSCL1 DSDA1 AVDD18B R1X2+ R1X2AGND6 R1X1+ R1X1AVCC33B R1X0+ R1X0-

D104 D5V0S1

D105 D5V0S1

D106 D5V0S1

C133 10P

C134 10P

AGND5 R1XC+ R1XCAVCC18C HPD1 I2CSEL/INT DGND1 DVCC18A RPWR0 DSCL0 DSDA0 AVDD18A R0X2+ R0X2AGND4 R0X1+ R0X1AVCC33A R0X0+ R0X0-

GND

R32 NC\4K7

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

R33

100R

RESET_N

CEC

DV33

GND

C11 0.1U

C20 0.1U

C19 1U

P903 RX2+ GND1 RX2RX1+ GND2 RX1RX0+ GND3 RX0RXC+ GND4 RXCNC1 NC2 DDCCLK DDCDA GND5 VCC HPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 +5V_HDMI0 0R R58 HDMI0_SCL HDMI0_SDA

GND

o f
HPD0

T r
HPD0
C

C12 0.1U

C13 0.1U

C14 0.1U

C15 0.1U

C16 0.1U

DV33

R52 4K7 R54 4K7 R55 4K7 Q2 BT3904

C B E

GND R53 100R HDMI_SEL

C17 0.1U

+5V_HDMI0

+5V_HDMI0 U905 1 8 A0 VCC 2 7 A1 WP 3 6 A2 SCL 4 5 GND SDA AT24C02 GND

T Z908 R50 47K

DV33 C40 0.1U R23 1K R27 4K7 R24 4K7 T Z907 R13 4K7
C

R56 4K7

R49 47K

HDMI0_SCL HDMI0_SDA T Z906 T Z905

GND

Q21 BT3904
E

GND 5 D3V3L4 GND HPD1

Q23 BT3904
E

R17

100R

HPDIN

+5V_HDMI1

GND R25 1K U906 R47 47K A0 R57 4K7 R48 47K 1 C41 0.1U 8 VCC 2 7 A1 WP 3 6 A2 SCL 4 5 GND SDA AT24C02 GND

T Z903 R26 4K7

Q22 BT3904

B E

HDMI1_SCL HDMI1_SDA T Z901 T Z902

GND

T Z904

C22 0.1U

C23 1U

C21 0.1U

4K7 R51

L C

R30 NC\4K7

R34 R35

NC\100R

CI_DV18

AV18-HDMI

CI_DV18

DV18-HDMI

OSDA0

NC\100R

OSCL0

L11 600R

L10 600R

C135 10P

C136 10P

DV33

EZJZ1V270RA

D107 D5V0S1

AGND9 TPWR/I2CADDR TSCL TSDA HPDIN RSVDL DGND2 DVCC18B RPWR2 DSCL2 DSDA2 AVDD18C R2X2+ R2X2AGND8 R2X1+ R2X1AVCC33D R2X0+ R2X0-

R11 4K7

U904 SII9185

TX2+ TX2AGND1 TX1+ TX1AVCC18A TX0+ TX0AGND2 TXC+ TXCEXTSWING RESET# LSDA LSCL HPD0 AVCC18B R0XCR0XC+ AGND3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

RX0_2 RX0_2B RX0_1 RX0_1B RX0_0 RX0_0B RX0_C RX0_CB R31 750R

GND

P Q T

CEC-IN 1

R45 0R

CEC near to u904 pin63,55,43,23 DV33-HDMI

R72

4 2

1 R12 NC\4K7 D109

P1 11 21 10 20 9 19 8 18 7 17 6 16 5 15 4 14 3 13 2 12 1 1 R63 2 EZJZ1V270RA GND

SCT1_AV_OUT SCT1_R_IN SCT1_G_IN SCT1_AUR_OUT

T Z921 T Z925 T Z926 T Z924

Nearly Connector
SCT1_AV_IN L903 30R R970 100R

Nearly 5335
C968 0.047U
SY0

SCT1_AUR_IN
SCT1_AUL_OUT

R968 75R

C967 47P C969 1U

GND_SV

SCT1_AUL_IN
SCT1_B_IN

GND SCT1_G_IN 1 L904 30R

SCT1_FS_IN

R969 68R

C971 0.01U

Y0P

R60 EZJZ1V270RA GND

R971 75R

C970 16P

GND SCT1_B_IN

L905 30R

STC1_FB_IN

R975 75R R61 EZJZ1V270RA GND

C973 16P

SCT1_AV_IN

T Z920 T Z928 T Z923 T Z919 T Z918 T Z922 T Z927 R64 EZJZ1V270RA

GND 2

SCT1_R_IN 1

STC1_FB_IN 1

L907 30R

R963 SOY0 0R

C979 R65 EZJZ1V270RA 2 SCT1_FS_IN 1 C980 470P L908 30R 470P

R960 75R

GND R961 33K

SCART_FS_IN

o f

GND

T r
SCT1_AUR_IN SCT1_AUL_IN

L C
L906 30R R62 EZJZ1V270RA GND 2 L1 30R L2 30R 1 R68 EZJZ1V270RA 2

R976 75R

C976 16P

P Q T
R972 100R C972 0.01U C974 0.01U Y0N R973 68R PB0P R974 100R C975 0.01U PBR0N R977 68R C977 0.01U PR0P R978 100R C978 0.047U SC0 R964 10K R965 10K R966 10K R967 10K C965 1U C966 1U SCT_R SCT_L C964 470P

2 1

1 2

C963 470P

R962 10K

SCT1_AUR_OUT 1 R67

SCT1_AUL_OUT

GND

2 R66 EZJZ1V270RA EZJZ1V270RA GND 2 GND

AV_5V

L925 10R

C004 0.01U

C003 1U

TV_CVBS

R918 0R R919 NC

R9003 10K

CVBS0

R945 100R

C953 0.047U

T Z917
132 130 129 128 127 126 125

U203 139 140 133 131 124 141 142 137 138 135 134 DVDD25_VADC GND GND_CVBS GND_SV AVDD25_VADC GND AVDD25_REF GND AVDD25_VFE GND

CVBS1

D2SA

C001 47U 6V3

R920 1K

C B E

BC847C Q815 R9004 75R

CVBS2 GND
SY0 SC0 SY1 SC1

CVBS0 CVBS1 CVBS2 SY0 SC0 SY1 SC1

DVDD25_VADC DVSS25_VADC GND_TUNER GD_CVBS GND_SV AVDD25_VADC AVSS25_VADC AVDD25_REF AVSS25_REF AVDD25_VFE AVSS25_VFE

C920 1U

GND_TUNER

SCT1_AV_OUT
D2SA 136

R9002 10K

R9001 470

GND

Nearly Connector
T Z975 1

P902 8 7 6 5 4 3 2 1 2 1

R70

NC/EZJZ1V270RA

Z980 Z981 T T

L926 0R L927 0R

NC/EZJZ1V270RA

o f
C9004 470P 2 GND

Z974

T r
R69 2 R9010 100 R9009 100 C9003 R9012 NC/10K L928 0R GND

GND

NC/EZJZ1V270RA

L C
L915 0R R947 NC/75R C958 47P L916 0R R949 NC/75R C960 47P GND C9001 1U C9002 1U AIN2_L AIN2_R R9011 NC/10K R9014 NC/75R C9007 47P

P Q T
Nearly 5335
R946 100R C959 0.047U SY1 R948 100R C961 0.047U SC1 R9013 100R C9006 0.047U
CVBS2

D2SA

C002 47P

MT5335PKU

AV25 AV25 L911 600R C916 AV25 AV25 L912 600R C917 AV25 AV25 L913 600R C918 1U AV25 AV25 L914 600R C919 1U GND AVDD25_VFE C957 0.1U GND AVDD25_REF C956 0.1U 1U 1U

DVDD25_VADC C954 0.1U

GND AVDD25_VADC C955 0.1U

470P

T Z976

R71

GND

C915 1U GND_CVBS

T Z978

GND

Nearly 5335 Nearly Connector

WHITE

R984 0R

C728 4700P

1 2 3

SOY1

YPBPR_L_IN Y_IN Y_IN L4 30R R981 68R C730 0.01U

GREEN

Y1P
U203

RED

4 5 6

YPBPR_R_IN PB_IN

BLUE

R982 75R

C731 16P R983 100R C729 0.01U

Y1N

RED

PR_IN 7 VGA_R_IN 10 VGA_L_IN 9 P907 8 R985 75R 1 R74 EZJZ1V270RA 2 2 2 R76 EZJZ1V270RA R988 75R C724 16P 2 R77 EZJZ1V270RA GND PR_IN L6 30R R989 68R C723 0.01U 1 1 1 PB_IN L5 30R R986 68R C726 0.01U PB1P GND

SOY0 Y0P Y0N PB0P PBR0N PR0P SOY1

C727 16P R987 100R C725 0.01U PBR1N

GNDR75 EZJZ1V270RA

GND

T Z929

P904 BLACK

2 1

o f
SPDIF_OUT

T r
C732 0.1U C993 33P R980 100R GND

L C
ASPDIF

PR1P

P Q T
T Z939 T Z940
112 111 TN1 TP1

Y1P Y1N PB1P PBR1N PR1P

107 108 109 114 115 116 118 119 120 121 122 123

SOY0 Y0P Y0N PB0P PBR0N PR0P SOY1 Y1P Y1N PB1P PBR1N PR1P

DVDD12_VGA AVSS12_RGBADC AVDD12_RGBADC AVSS12_RGBFE AVDD12_RGBFE RP RN BP BN GP GN VSYNC HSYNC SOG

117 113 110 105 101 104 106 98 99 102 103 96 97 100

DVDD12_VGA GND AVDD12_RGBADC GND AVDD12_RGBFE RP RN BP BN GP GN VSYNC HSYNC SOG

MT5335PKU

AV12 AV12 L909 600R C987 1U AV12 AV12 L910 600R C989 1U AV12 AV12 L3 600R C991 1U GND AVDD12_RGBFE C992 0.1U GND AVDD12_RGBADC C990 0.1U

DVDD12_VGA C988 0.1U

GND

R979 100R

YPBPR_L_IN YPBPR_R_IN

L8 30R L7 30R

R990 10K R991 10K R992 10K R993 10K

C721 1U C720 1U

YPBPR_L YPBPR_R

1 2 R73 EZJZ1V270RA

C719 470P

C722 470P

GND

Nearly 5335
T Z945 T Z941 T Z942 T Z943 T Z944 T Z946 T Z948 T Z947 T Z955
VGASCL_IN

Nearly Connector
L918 30R

R998 0R

C712 4700P

SOG

P908 16 5 15 10 4 14 9 3 13 8 2 12 7 1 11
RED

GREEN

R719 33R

C714 0.01U

GP VGA_PLUGPWR

R996 75R R716 0R W/P VGA_PLUGPWR 3 1 2 D913 BAV70 C005 ESD_0402 R999 75R GND +5V BLUE L919 30R GND

C715 16P R997 100R R720 33R C713 0.01U C710 0.01U VGA_PLUGPWR

Z973 T

W/P_CTR
VSYNC_IN

GN BP

C996 0.1U U903 1 8 VCC 2 7 A1 WP 3 6 A2 SCL 4 5 GND SDA AT24C02 A0 W/P VGASCL VGASDA R715 10K Z970 T Z971 T Z972 T

BLUE
HSYNC_IN

GREEN
VGASDA_IN

C711 16P

RED EZJZ1V270RA R86 EZJZ1V270RA 1 1 1

L920 30R

GND

6 17

GND GND R85 EZJZ1V270RA

T Z949 T Z950 L924 30R L923 30R

VGA_R_IN

R704 10K

VGA_L_IN

C999 470P

C703 470P

HSYNC_IN 1

L921 30R

HSYNC

R82

C705 10P

EZJZ1V270RA 2 GND L922 30R VSYNC VSYNC_IN 1 R717 4K7 R83 C704 10P EZJZ1V270RA 2 GND

o f
R706 10K

R705 10K

T r
C702 1U VGA_R C701 1U VGA_L R707 10K GND

L C
16P GND VGASCL_IN 1 R80 EZJZ1V270RA 2 GND VGASDA_IN 1 R81 EZJZ1V270RA GND 2

R702 75R

C708

P Q T
R701 100R C709 0.01U BN R721 33R C707 0.01U RP R703 100R C706 0.01U RN 5VSB 5VSB R708 10K R709 100R VGASCL C998 16P Q903 C143ZT U0TX
E C

GND

R84

5VSB 5VSB R714 10K

R712 100R

VGASDA_IN R713 100R

Q904 C143ZT
C C B

5VSB R710 10K SW_UPDATE_CTL Q905 C143ZT

R711 100R

VGASDA

R725 10K

C997 16P

GND

5VSB

VGASCL_IN

U0RX

R718 4K7

P Q T
G1

o f
3 +5V GND 2 1 IR

T r
C3 47U 16V C2 10U

R6 100R

R5 100R C1 10U

L C

VCC

GND

DGND

200R 32 VSS2

R828

200R

R827

200R

VOL+

VSS1 12

P1[5] 9

P1[3] 10

P1[1] 11

P1[0] 13

P1[2] 14

P1[4] 15

P1[6] 16

R826

200R

L C
6 P3[3] 10K 7 P3[1] R829 8 P1[7] R804 R825 200R 0R/NC R824 200R DGND

DGND

o f
R822 31 1 P0[1] 2 3 4 5 P2[7] P2[5] P2[3] P2[1]

VOL-

T r
C1 P0[3] 5600P

LED807

LED806

LED805

P Q T
LED804 R830 NC/15K WHITE DGND 5VSB C802 DGND 0.47U C805 2U2 D1 KEY SDA LED-R 1 2 3 4 5 6 P801

WHITE

DGND

U801
CY8C21434

DGND

POWER MENU VOL5VSB VOL+ FB801 CHC803 CH+ 120R 0.1U

LED808

LED803 30 P0[5]

WHITE

28 VDD SDA LED-R

29 P0[7]

27 P0[6]

26 P0[4]

25 P0[2] P0[0] P2[6] P2[4] P2[2] P2[0] P3[2] P3[0] XRES 24 23 22 21 20 19 18 17 T Z1

POWER

D801 4148/0R D802 4148/0R D803 4148/0R D804 4148/0R D805 4148/0R

R837 6K8 R836 3K9 R835 2K4 R834 390R R833 1K

CH+ CH-

D806 4148/0R

R832 1K5

R601 2K2 R602 3K3 R603 1K2 R604 4K7 R605 7K5 R606 750R

CH+ CH-

1 2 1 2 1 2

K606 K605 K604

P601 4 3 5VIN 5VSB

R701 NC

2GND 1 KEY

o f

T r
C601 0.1U

L C
menu VOL+ VOL1 2 1 2

K603 K602

POWER

1 2

K601

P Q T
3 4 3 4 3 4 3 4 3 4 3 4

+5VSB

BC857B QZ1

E B C

RZ3 10K
C B E

QZ2 BC847B P1

RZ4 82K

RZ5 22K

GND

3 GND 2 1

o f

T r
RZ9 10K
C B E

RZ8 10K

QZ4 BC847B

RZ10 10K

L C
GND +5VSB RZ7 5K6 RZ6 120
E

CZ1 1U

LAMP

P Q T
PZ1 KEY 6 5 4 3 2 1 STANDBY PO IR +5VSB STANDBY GND 0R JZ1 PZ2 STANDBY 7 5 +5VSB GND KEY 3 1 8 6 4 2 +5VSB IR GND

RZ1 120

RZ2 5K6 BC857B

B C

QZ3

STANDBY

GND

+5VSB

BC857B QZ1

E B C

RZ3 10K
C B E

QZ2 BC847B PZ2

RZ4 82K

RZ5 22K

STANDBY KEY

GND

CZ1 1U

LAMP

3 GND 2 1 +5VSB

o f

T r
BC857B
E

RZ8 10K

QZ3

STANDBY

L C
GND RZ9 10K QZ4 BC847B
C B E

+5VSB

P Q T
PZ1 PO 13 11 9 7 5 3 1 14 12 10 8 6 4 2 STANDBY KEY +5VSB +5VSB IR IR GND

RZ1 120

RZ2 5K6 RZ6 120 RZ7 5K6 GND RZ10 10K

BC857B QZ1

E B C

QZ2 BC847B/NC

C B E

RZ5 22K

STANDBY 5 PO 4 3 2 1

3 2 1

+5VSB

GND

o f

T r
DZ1 CZ1 1U GND GND

CZ2 1U/NC

+5VSB

GND

RZ4 0R

L C
RZ3 10K/NC

P Q T
PZ1 PZ2

+5VSB

RZ1 390R

RZ2 5K6

D +HV1

VPFC 1

RM7 1M CX1 474 275VAC ZR1 C RM1 1M 14D 680V RM2 1M CY5 471 Y1 RM8 1M CY1 471 Y1 CY3 152 Y1 CY2

L102 ET24 471 Y1

ZR2 14D 680V 4

D101 2 RV5 C101 5A 600V 105 450V LB1 RV8 510K 1% + C102 100uF 450V

BD1 D3SB60 3

510K 1%

L103 RV6 510K 1% 510K 1% RV7 510K 1% RF5 NC CF1 471 RF1 15K CF4 101 RF7 47 RF11 10K RV10 240K 1% RF3 10K 1% DF1 BAV99 RF12 4.7 Q101 13N50 EI28 RV9 C

L1 T13*8*6

RF6 3.9K B RT1 2.5 10D RF2 18K F1 T6.3AH 250V QF1 2N3906 CF6 RF4 474 CF11 3 2 1 L-AC N-AC NC CN1 +Vc Title Size A4 Date: File: 1 2 3 21-May-2008 Sheet of Drawn By: TCL\PCB SCH\MIP260T 0517 .ddb F:\zuzl\Product\MIP260\00 \MIP260T 4 Number Revision RF8 20 6.2K CF5 474 16V 3 2 1 CF3 103 U1 5 6 7 8 L6562 RF9 4 3 2 1 CF2 Z10 6.8V 470 474 16V RFS1 3.3 1% RFS2 3.3 1% RFS3 3.3 1% RS101 1.0 2W RF10 8.2K 1% B

CN3 +12V GND +5V GND GND +5VSB GND DM 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 +12V GND +5V +5V GND +5VSB STB BK

VPFC +HV1

T103 EF25

RK1

10 D103

CK1

222

L104 +12V1

1.5uH

RV1 150K R101 RV2 150K C108 QV1 3906 2 C CV2 104 QV2 3906 1 2 1 QV3 3906 R2 R3 200 R5 100 R4 470 3 100 2 Q1 4403 3 BAV70 R1 68 1 23 1 472 400V 100K 2W D102 HER107 20A 45V D13 C110 NC C109 2200uF 10V KF RV3 150K +VCC D109 HER103 R7 CV1 104 3 RV4 2M D1 Q104 3A 800V 1 3 4.7 R22 15V 68K 2 Q8 25V 45A 1 D3 HER103 3 + GND + T103 C25 100uF 35V C2 221 200V 2 220uF 16V C113 Z4 C + 1000uF 10V KF + Z101 TVS 6.8V

T103

C111 47uF 25V GND

R18 1K

CK7 NC C3 C127 1

224

2 RS1 6 5 4 U2 LD7535 +VC1 1 2 3 R6 100K C107 P103 10uF 50V C1 103 U101 R12 Z1 18V Q2 4401 +VC +VCC R8 2K P102 PC817 R24 10K R23 R16 3K Q4 3904 A 10K C5 103 R21 3K GND Z5 NC TL431 100K 1% R11 10K 1% 3 Q6 3906 2 R29 4.7K R10 470 CK8 474 25V PC817 R9 2K R25 470 R13 10K 1% NC 2.2 1% 2.2 1% 4.7 R14 0 Z2 RS2 RS3 B Q3 4403 3 +5V

100uF 35V GND

B Z9 22V SOT-23 +

+VB

R35 SB 10K R34 33K +5VSB R33 100 A

+5VSB

Q5 3904

R30 4.7K Q10 3904 C6 473 R31 470 Q11 3904 GND R36

C132 104 STB GND

10K

GND

Title Size A3 Date: File: 1 2 3 4 5 6 21-May-2008 Sheet of Drawn By: TCL\PCB SCH\MIP260T 0517 .ddb F:\zuzl\Product\MIP260\00 \MIP260T 7 8 Number Revision

RA17 PWM32K RJ4 0 Q12 2N3904 RA28 D P-CON 20K CA16 NC CA15 RA29 10K 4403 NC RA13 3.3K GND +VB RA6 100 C128 RA8 100 DB20 4401 3 1 RA5 4.7K 2 U104 TL431 C RA48 200K CA24 104 RA9 10K 1% +5VMCU 4.7uF 50V + RA14 4.7 RJ2 0 PT Q9 RA23 10K 1K

RA18 1K CA3 473

RA19 10K

+5VMCU RA41 150K RA42 6 CA22 221 20K 8 CA6 103 1 3 CA5 103 LM358 4 U10A RA45 39K RA40 10K QB3 3904 D

CA4 473 2 RA22 Is1 2K

GND RJ36 0 DB3 RJ34 1K RA46 100K RA34 CA11 474 RA10 10K 1% + C117 2.2uF 50V 6 RA31 2.2 RA32 39K 1% CA19 471 NPO CA21 222 RA39 20K RA33 390K CA20 120K 104 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 U102 SG3525A 4.7K RA30 68K BAV70 3 CA13 RA35 NC QB1 2N3904 2 1

RA44 20K CA14 102

CA18 474

CA17 102

DB19 CA10 GND 103 2K 2 QB2 RB27 2K Vs1 Vs2 CON1 PWM-OUT RA43 13K 1% Is1 DM GND A/EPWM RES CA1 104 SEL BK RB45 10K RB46 10K QB6 C129 103 +5VMCU RA12 3.3K RA11 3.3K +5VMCU RA4 100 RB50 0 DB9A 2 1 LED RA3 4.7K 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 3 2N3904 CA12 224 P-CON +5VMCU PWM32K RA21 1K RB44 10K T102 EE16 RA25 2K RA36 RA24 4.7K 1 RA26 NC BAT54

DB18 BAT54 GND RA27 2.2

CA9 472 QB4 3904 RA15 10K RA1 10K

B +5VMCU

RJ39 1K +5VMCU RB47 10K 1 2 CN8

RA2

RA37 NC RA20 2K CA7 102

3904

1 2 3 4 5

GND

CON2 Title Size A3 Date: File: 1 2 3 4 5 6 21-May-2008 Sheet of Drawn By: TCL\PCB SCH\MIP260T 0517 .ddb F:\zuzl\Product\MIP260\00 \MIP260T 7 8 Number Revision

6 RN9 +VB 100K

C119

10P 6KV

DB10 BAV99 CB60 223

DN1 BAW56 RN11 1.5K 1% RN1 7.5K 1% CB73 102 CB72 102 DN5 BAV99 CB44 NC RA16 100K CA8 NC

VS1

CB27 472 NPO D T104

DN2 BAV70

CN4 RA38 15K CA23 103 VS2 RB37 2K DB8 PT BAV70 1 2

CB61 223 CB26 472 NPO C120 10P 6KV DB11 BAV99

RN2 7.5K 1%

DN2 DN1

RN10 1.5K 1%

VPFC RM3 2 DD3 BAV70 RD8 T102 100 C RD7 10K DD2 QD3 3 2N3904 1 RD12 4.7K DD4 BAV70 2 Q102 5A 500V RD9 RD5 T102 10K RDS1 0.47 RDS2 RDS3 0.47 1.0 270K 100 4.7 1 C105 RD11 RM6 224 400V RK4 RK5 C115 NC NC CK6 NC L105 15uH 470uF 25V + T105 3 RK3 10 CK2 222 2 RM5 270K BAV70 D106 SB540 RD10 3 4.7 1 RM4 270K T101 EFD30 224 400V D104 SB540 Q103 5A500V 270K RK2 C104 10 CK5 222 L106 EE16 13.5uH C116 1uF 100V T104 EEL22

C121 10P 6KV

DB12 BAV99 CB63

RN13 1.5K 1% RN3 7.5K 1% CB74 CB62 223

DN3 BAW56 CB75 102 CN5 102 DN4 BAV70 1 2 C

CB28 472 NPO

223

CB29 472 NPO DB13 BAV99 C122 10P 6KV

RN4 7.5K 1% RN12 1.5K 1%

C123 10P 6KV

DB14 BAV99

RN15 1.5K 1%

DN8 BAW56 CB78 102 CN7 CB79 DN9 BAV70 1 2

CB70 472 NPO

CB66 223 CB67 223

RN5 7.5K 1% RN6 7.5K 1% 102

CB32 472 NPO C124 10P 6KV DB15 BAV99

RN19 1.5K 1%

RD6 B

1K DD1 BAV70 1 CD1 102 QD2 P101 NC 4401 3 2 4403 15V 2 3 Z102 QD1 RD1 2K R102 +12V1 510 2W F2 6A T105 EEL22

C125

10P 6KV DB16 BAV99 CB33 CB64 223 RN17 1.5K 1% RN18 7.5K 1% CB76 102 CB77 102

DN6 BAW56

472 NPO +12V RD4 NC CD2 104 RD3 0 +VC1 CD3 224 PT BAV70 Is1 A CA2 103 RA7 2K 1% DB9B BAV70 DB8B BAV70 1.8K DB7B BAV70 RD14 470 RD13 2K RD2 2K GND 1

CN6 DN7 BAV70 1 2

CB34 472 NPO C126 10P 6KV

CB65 223

RN8 7.5K 1% RN14

DB17 BAV99 T107 UF9.8

1.5K 1%

DB8

RA47

Title Size GND A3 Date: File: 21-May-2008 Sheet of Drawn By: TCL\PCB SCH\MIP260T 0517 .ddb F:\zuzl\Product\MIP260\00 \MIP260T 7 8 Number Revision

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