VLSI Testing

Memory Test
Virendra Singh
Indian Institute of Science Bangalore
virendra@computer.org E0286: Testing and Verification of SoC Designs Lecture 27
Apr 02, 2008 E0286@SERC 1

RAM Organization
. . .
A 5 DATA IN TRISTATE DATABUS INPUT BUFFERS R/W 1 R/W CS CONTROL R/W2 y 0 y 63

ROW ADDRESS BUFFERS

ROW (X) DECODER

a 0

x 0 CELL ARRAY 64 X 64 Cells 4 K Bits b0 b0 b 63 b63

a 5

63

BITLINE PAIRS SENSE AMPLIFIER DATA OUT TRISTATE OUTPUT BUFFER

DATABUS

COLUMN (Y) DECODER s s s 0 0 11 s11 COLUMN ADDRESS BUFFERS A6

. . .

A11

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Test Time
Size Number of Test Algorithm Operations

n bits
1 Mb 4 Mb 16 Mb 64 Mb 256 Mb 1 Gb 2 Gb

n
0.06 0.25 1.01 4.03 16.11 64.43 128.9

n log2n
1.26 5.54 24.16 104.7 451.0 1932.8 3994.4

n3/2

n2

64.5 18.3 hr 515.4 293.2 hr 1.2 hr 4691.3 hr 9.2 hr 75060.0 hr 73.3 hr 1200959.9 hr 586.4 hr 19215358.4 hr 1658.6 hr 76861433.7 hr

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SRAM Fault Models

Faults found only in SRAM

Open-circuited pull-up device Excessive bit line coupling capacitance

Model
DRF CF

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DRAM Only Fault Models

Faults only in DRAM Model
DRF SAF PSF CF PSF AF

Data retention fault (sleeping sickness) Refresh line stuck-at fault Bit-line voltage imbalance fault Coupling between word and bit line Single-ended bit-line voltage shift Precharge and decoder clock overlap

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Fault Modeling
Behavioral (black-box) Model -- State machine modeling all memory content combinations -Intractable Functional (gray-box) Model -- Used Logic Gate Model -- Not used Inadequately models transistors & capacitors Electrical Model -- Very expensive Geometrical Model -- Layout Model Used with Inductive Fault Analysis

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Functional Model

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Simplified Functional Model

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Reduced Functional Faults

SAF TF CF NPSF

Fault Stuck-at fault Transition fault Coupling fault Neighborhood Pattern Sensitive fault*

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Stuck-at Faults
Test Condition: For each cell, read a 0 and a 1. < /0> (<
A A

/1>)
w1 S0 w0 S1 w1

w0

State diagram of a good cell w0 S0 S1 SA1 fault

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w1

w1

w0

SA0 fault
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Transition Faults
Cell fails to make a 0 1 or 1 0 transition. Test Condition: Each cell must have an transition and a transition, and be read each time before making any further transitions. </0>, </1>

w1 w0 S0 w0
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S1

w1
11

</0> transition fault

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Coupling Faults
Coupling Fault (CF): Transition in bit j (aggressor) causes unwanted change in bit i (victim) 2-Coupling Fault: Involves 2 cells, special case of k-Coupling Fault Must restrict k cells for practicality Inversion (CFin) and Idempotent (CFid) Coupling Faults -- special cases of 2-Coupling Faults Bridging and State Coupling Faults involve any # of cells Dynamic Coupling Fault (CFdyn) -- Read or write on j forces i to 0 or 1
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State Transition Diagram of Two Good Cells, i and j

w0/ i, w0/ j w1/ j S00 w1/ i S10 w1/ j w0/ j
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w0/i, w1/ j S01 w0/ i S11 w1/ i

w0/ j

w0/i

w1/ i, w0/ j

w1/i, w1/ j

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State Transition Diagram for CFin < ; >

w0/ i, w1/ j S 01 w0/ i w1/ j w0/ j
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w0/ i, w0/ j

S 00 w1/ i S10

w0/ j w1/ j

w0/ i

w1/ i

w1/ i, w0/ j

S11

w1/ i, w1/ j

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State Coupling Faults (SCF)

Aggressor cell or line j is in a given state y and that forces victim cell or line i into state x < 0;0 >, < 0;1 >, < 1;0 >, < 1;1 >
w0/ i, w0/ j w0/ j w1/ j w0/ i S 10 w1/ i w1/ j w0/ j w0/ i S 11 w1/ i w0/ i, w1/ j S01

S00

w1/ i, w0/ j

w1/ i, w1/ j

State coupling fault (SCF) <1 ; 1>

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March Test Elements

M0: { March element (w0) } for cell := 0 to n - 1 (or any other order) do write 0 to A [cell]; M1: { March element (r0, w1) } for cell := 0 to n - 1 do read A [cell]; { Expected value = 0} write 1 to A [cell]; M2: { March element (r1, w0) } for cell := n 1 down to 0 do read A [cell]; { Expected value = 1 } write 0 to A [cell];
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March Tests
(w0); (r0, w1); (r1) } { (w0); (r0, w1); (r1, w0) } { (w0); (r0, w1); (r1, w0, r0) } { (w0); (r0, w1); (r1, w0); (r0) } { (w0); (r0, w1); (r1, w0); (r0, w1); (r1, w0); (r0) } MARCH C{ (w0); (r0, w1, w0, w1); (r1, w0, w1); (r1, w0, w1, w0); (r0, w1, w0) } MARCH A MARCH Y { (w0); (r0, w1, r1); (r1, w0, r0); (r0) } { (w0); (r0, w1, r1, w0, r0, w1); (r1, w0, w1); (r1, w0, w1, w0); MARCH B (r0, w1, w0) }
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Algorithm
MATS MATS+ MATS++ MARCH X

Description

Address Decoder Faults

Address decoding error assumptions: Decoder does not become sequential Same behavior during both read and write Multiple ADFs must be tested for Decoders can have CMOS stuck-open faults
Cx Ay Cy A Cx

Ax

Cx

Ay

Fault 2 Fault 4 Fault 1 Fault 3 No Address to Multiple Cells No Cell Multiple Addresses Accessed for Ax Access Cell C for Cell Cx x Accessed with Ay
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Theorem
A March test satisfying conditions 1 & 2 detects all address decoder faults. ... Means any # of read or write operations Before condition 1, must have wx element x can be 0 or 1, but must be consistent in test

Condition 1 2
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March element (rx, , w x ) (r x , , wx)

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March Test Fault Coverage

Algorithm MATS MATS+ MATS++ MARCH X MARCH CMARCH A MARCH Y MARCH B

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SAF All All All All All All All All

ADF Some All All All All All All All

TF

CF in

CF id

CF SCF dyn

All All All All All All

All All All All All

All

All

All

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March Test Complexity

Algorithm MATS MATS+ MATS++ MARCH X MARCH CMARCH A MARCH Y MARCH B

Complexity 4n 5n 6n 6n 10n 15n 8n 17n

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MATS+ Example Cell (2,1) SA0 Fault

0 00 0 00 0 0 0 (a) Good machine after M0. 0 00 0 00 0 0 0 (d) Bad machine after M0. 1 11 1 11 1 1 1 (b) Good machine after M1. 1 11 0 11 1 1 1 (e) Bad machine after M1. 0 00 0 00 0 0 0 (c) Good machine after M2. 0 00 0 00 0 0 0 (f) Bad machine after M2.

MATS+: { M0:
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(w0); M1:

(r0, w1); M2:

(r1, w0) }
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MATS+ Example Cell (2, 1) SA1 Fault

0 00 0 00 0 0 0 (a) Good machine after M0. 0 00 1 00 0 0 0 (d) Bad machine after M0. 1 11 1 11 1 1 1 (b) Good machine after M1. 1 11 1 11 1 1 1 (e) Bad machine after M1. 0 00 0 00 0 0 0 (c) Good machine after M2. 0 00 1 00 0 0 0 (f) Bad machine after M2.

MATS+: { M0:
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(w0); M1:

(r0, w1); M2:

(r1, w0) }
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MATS+ Example
Multiple AF: Addressed Cell Not Accessed; Data Written to Wrong Cell
Cell (2,1) is not addressable Address (2,1) maps onto (3,1), and vice versa Cannot write (2,1), read (2,1) gives random data
0 00 0 00 1 11 0 00 0 00 1 11 0 0 0 0 0 0 1 1 1 (a) Good machine (b) Good machine (c) Good machine after M2. after M0. after M1. 0 00 1 11 1 11 X00 X00 X11 0 0 0 1 0 0 1 1 1 (d) Bad machine (e) Bad machine (f) Bad machine after M0. after M1 for cell (2, 1). after M1. 0 00 X00 0 0 0 (g) Bad machine after M2.

MATS+: { M0:
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(w0); M1:

(r0, w1); M2:

(r1), w0 }
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Memory BIST

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LFSR and Inverse Pattern LFSR

NOR gate forces LFSR into all-0 state
Get all 2n patterns

Normal LFSR: G ( x) = x3 + x + 1
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Inverse LFSR:

G ( x) = x3 + x2 + 1
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Up / Down LFSR
Preferred memory BIST pattern generator
Satisfies March test conditions

0 M 0 M

U 1 X

D Q
X0

0 M

U 1 X

D Q
X1

0 M

U 1 X

D Q
X2

U 1 X

Up/Down
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Up / Down LFSR Pattern Sequences

Up Counting 000 100 110 111 011 101 010 001 Down Counting 000 001 010 101 011 111 110 100

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Mutual Comparator
Test 4 or more memory arrays at same time: Apply same test commands & addresses to all 4 arrays at same time Assess errors when one of the di (responses) disagrees with the others

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Mutual Comparator System

Memory BIST with mutual comparator

Benefit: Need not have good machine response stored or generated

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SRAM BIST with MISR

Use MISR to compress memory outputs Control aliasing by repeating test: With different MISR feedback polynomial With RAM test patterns in reverse order March test: { (w Address); (r Address);

(w Address); (w Address);

(r Address); (r Address);

(r Address); (r Address) }

Not proven to detect coupling or address decoder faults

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BIST System with MISR

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LFSR and Inverse Pattern LFSR

NOR gate forces LFSR into all-0 state
Get all 2n patterns

Normal LFSR: G ( x) = x3 + x + 1
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Inverse LFSR:

G ( x) = x3 + x2 + 1
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Up / Down LFSR
Preferred memory BIST pattern generator
Satisfies March test conditions

0 M 0 M

U 1 X

D Q
X0

0 M

U 1 X

D Q
X1

0 M

U 1 X

D Q
X2

U 1 X

Up/Down
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Up / Down LFSR Pattern Sequences

Up Counting 000 100 110 111 011 101 010 001 Down Counting 000 001 010 101 011 111 110 100

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Mutual Comparator
Test 4 or more memory arrays at same time: Apply same test commands & addresses to all 4 arrays at same time Assess errors when one of the di (responses) disagrees with the others

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Mutual Comparator System

Memory BIST with mutual comparator

Benefit: Need not have good machine response stored or generated

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SRAM BIST with MISR

Use MISR to compress memory outputs Control aliasing by repeating test: With different MISR feedback polynomial With RAM test patterns in reverse order March test: { (w Address); (r Address);

(w Address); (w Address);

(r Address); (r Address);

(r Address); (r Address) }

Not proven to detect coupling or address decoder faults

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BIST System with MISR

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Thank You
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