0
EE-4232
Review of
BJTs, JFETs and MOSFETs
1
A simplified structure of the npn transistor.
2
A simplified structure of the pnp transistor.
3
Current flow in an npn transistor biased to operate in the active mode, (Reverse current
components due to drift of thermally generated minority carriers are not shown.)
4
Current flow in an pnp transistor biased to operate in the active mode.
5
The i
C
-v
CB
characteristics for an npn transistor in the active mode.
6
(a) Conceptual circuit for measuring the i
C
-v
CE
characteristics of the BJT.
(b) The i
C
-v
CE
characteristics of a practical BJT.
7
(a) Conceptual circuit to illustrate the operation of the transistor of an amplifier.
(b) The circuit of (a) with the signal source v
be
eliminated for dc (bias) analysis.
8
Linear operation of the transistor under the small-signal condition: A small signal v
be
with a
triangular waveform is superimpose din the dc voltage V
BE
. It gives rise to a collector signal
current i
c
, also of triangular waveform, superimposed on the dc current I
C
. I
c
= g
m
v
be
, where g
m
is
the slope of the i
c
- v
BE
curve at the bias point Q.
9
Two slightly different versions of the simplified hybrid- model for the small-signal
operation of the BJT. The equivalent circuit in (a) represents the BJT as a voltage-
controlled current source ( a transconductance amplifier) and that in (b) represents the
BJT as a current-controlled current source (a current amplifier).
10
Two slightly different versions of what is known as the T model of the BJT. The circuit
in (a) is a voltage-controlled current source representation and that in (b) is a current-
controlled current source representation. These models explicitly show the emitter
resistance r
e
rather than the base resistance r
featured in the hybrid- model.
Junction Field-Effect Transistors
i
D
v
DS
I
DSS
-V
p
n-JFET
v
GS
=0
v
GS
=V
p
Pinch-off
v
DG
> -V
p
v
GS
=-1
i
D
v
SD
I
DSS
V
p
p-JFET
v
SG
=0
v
SG
=-V
p
Pinch-off
v
GD
> V
p
v
SG
=-1
Junction Field-Effect Transistors
Triod (VCR) Region
Boundary
Pinch-Off Region
i
D
I
DSS
2 1
v
GS
V
p
--------
v
DS
V
p
----------
v
DS
V
p
--------
2
=
r
DS
v
DS
i
D
--------
v
DS
small =
2I
DSS
V
p
-------------- 1
v
GS
V
p
--------
1
= =
v
DG
V
p
=
i
D
I
DSS
v
DS
V
p
--------
2
=
i
D
I
DSS
1
v
GS
V
p
--------
2
=
11
MOSFETs
12
Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b)
cross section. Typically L = 1 to 10 m, W = 2 to 500 m, and the thickness of the
oxide layer is in the range of 0.02 to 0.1 m.
13
The enhancement-type NMOS transistor with a positive voltage applied to the gate. An
n channel is induced at the top of the substrate beneath the gate.
14
The drain current i
D
versus the drain-to-source voltage v
DS
for an enhancement-type
NMOS transistor operated with v
GS
> V
t
.
15
Cross section of a CMOS integrated circuit. Note that the PMOS transistor is formed
in a separate n-type region, known as an n well. Another arrangement is also possible
in which an n-type body is used and the n device is formed in a p well.
16
(a) An n-channel enhancement-type MOSFET with v
GS
and v
DS
applied and with the
normal directions of current flow indicated. (b) The i
D
- v
DS
characteristics for a device
with V
t
= 1 V and k
n
(W/L) = 0.5 mA/V
2
.
17
The i
D
- v
GS
characteristic for an enhancement-type NMOS transistor in saturation
(V
t
= 1 V and k
n
(W/L) = 0.5 mA/V
2
).
18
Large-signal equivalent circuit model of the n-channel MOSFET in saturation,
incorporating the output resistance r
o
. The output resistance models the linear
dependence of i
D
on v
DS
and is given by r
o
V
A/
I
D
.
19
Conceptual circuit utilized to study the operation of the MOSFET as an amplifier.
20
Small-signal operation of the enhancement MOSFET amplifier.
21
Small-signal models for the MOSFET: (a) neglecting the dependence of i
D
on v
DS
in
saturation (channel-length modulation effect); and (b) including the effect of channel-
length modulation modeled by output resistance r
o
= |V
A
|
/
I
D
.
22
(a) The CMOS inverter. (b) Simplified circuit schematic for the inverter.
23
Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and
output waveforms.
