Transmission gate and Pass-Transistor Logic
Advanced logic function or switching scheme
are implemented using the feature of transistor
MOS to work as a simple switch
It has the advantage of being simple and fast.
Complex gates are implemented with the
minimum number of transistors (the reduced
parasitic capacitance results in fast circuits
A
OUT
OUT = A B
B
Prof. Gaetano Palumbo 1
The static and transient performance strongly depend
upon the availability of an high quality switch with low
parasitic resistance and capacitance
A single transistor is used as switch: Pass
Transistor
N- and P-transistor are used: Transmission Gate
Implementation with a single transistor reduces the noise
margin and causes static power consumption
V
DD
V
DD
V
DD
-V
tn
0
-V
tp
V
DD
V
DD
-V
tn
OUT
V
DD
0
V
DD
Prof. Gaetano Palumbo
2
1
Transmission Gate Transmission Gate Simbol
C
C
A B
A B
C
C
Transmission gate has better noise margin than
pass transistor
0 0
V
DD
V
DD
0 0
V
DD
V
DD
Prof. Gaetano Palumbo
3
Transmission gate is very efficient to implement
some complex gate (MUX, DEMUX and XOR)
2-input Multiplexer 4-input Multiplexer
X Y
S A
A
X Y
OUT
B
S OUT
X
B
Y
C
S X Y
OUT = A S + B S D
X Y
OUT = A X Y + B X Y + C X Y + D X Y
Prof. Gaetano Palumbo 4
2
4-input MUX as cascade of 2-input MUX
X
A Y
X
B
Y OUT
X
C
X
D
Y
X
OUT = A X Y + B X Y + C X Y + D X Y
More parasitic capacitances on internal nodes, less
on the output node
Prof. Gaetano Palumbo 5
2-input XOR
Can be implemented with a 2-input MUX, or:
B
A
OUT
A OUT = A B + A B
B
Only the left side can implement the XOR logic
function, but a threshold voltages is lost at the
output without implementing the right side circuit
Prof. Gaetano Palumbo 6
3
Transmission Gate MUX Layout
S S
V
DD
S
A
TG1
INV
OUT
S
OUT
TG2
B
TG2 TG1
INV
S
GND
A S S B
Prof. Gaetano Palumbo 7
Transmission Gate Resistance
30000.0
R
n
(W/L)
p
=(W/L)
n
=
20000.0
1.8/1.2
R (Ohm)
R
p
0
10000.0
R
eq
IN
OUT
0.0
0.0
1.0 2.0 3.0 4.0 5.0 5 V
Vout
Prof. Gaetano Palumbo 8
4
Despite the nonlinear behavior of the NMOS and
PMOS transistors varying the input voltage, the
resistance of a transmission gate is almost
constant
We can approximate its value with that given by
the parallel of transistor resistances, assuming both
in linear region
1
= G
eq
=
dI
D
+
dI
D
=
R
eq
dV
DS
dV
DS
n
p
= |
n
(V
GSn
V
tn
V
DSn
)+ |
p
(V
SGp
+ V
tp
V
SDp
)
Prof. Gaetano Palumbo 9
If the gate-source voltage is around V
DD
/2, the
two transistors are in linear region (V
DS
~0)
1
= |
|V
V
|
+ |
|V
+V
|
DD
|
DD
|
R
2
2
n \ tn . p \ tp .
eq
Assuming the threshold voltage and the gain factor
of the NMOS and PMOS are equal (PMOS twice
the NMOS)
1
R
eq
=
n
C
ox
(W / L)
n
(V
DD
2V
t
)
To reduce parasitic effects both transistors
are generally minimum size
Prof. Gaetano Palumbo 10
5
Transmission Gate Delay
0 0 0
V
C1
V
DD
C2
V
DD
C3
V
DD
DD
Cn
R1 R2 R3 Rn
C1 C2 C3 Cn
Prof. Gaetano Palumbo 11
Applying the open-circuit time constant
n i n
t = C
i
R
j
= RC i = RC
n(n
+1)
i=1 j=1 i=1
2
R=R
eq
and C=4(C
gs
+C
sb
)
Approximating the circuit with a pole-dominant
behavior t
PD
= 0.69t . It increase with the
square of n
We can introduce buffer to minimize t
PD
Prof. Gaetano Palumbo 12
6
R
R
R
R
R
R
C C C C C C
m
n m(m +1)( | n |
t
PD
= 0.69
RC
2
( +
1|t
PDinv
m \ m .
d
t
PD
= 0
dm
t
PDinv
m
opt =
2
0.69RC
n
n
0.69RC
t
PDinv
=
0
2 m
2
Typical value 3-4
Prof. Gaetano Palumbo
13
Source of errors
Clock feedthrough due to capacitive coupling
Transistor ON Transistor OFF
V V V V V
V
OUT
A A A A A
V
t
V
C
L
C
L
C
L
C
GS
C
GS C
DD
V
A
+V
t
GS
Prof. Gaetano Palumbo 14
7
Charge conservation yields
(C
L
+ C
GS
)V
OUT
= C
L
V
A
C
GS
V
t
AV = V V
A
=
C
GS
(V
A
+V )
OUT1 OUT C
L
+ C
GS
t
Reduce with the reduction of C
GS
Prof. Gaetano Palumbo 15
Charge Injection due to redistribution of the
charge in the channel
Transistor ON (triode region)
V
V
DD
V
A
A
Oxide
n+ n+
p
V
A
V
A
V
DD
C
L
Q
ch
= C
ox
WL(V
DD
V
A
V
t
)
Prof. Gaetano Palumbo 16
8
When the transistor switch off the charge in the
channel is lost. If the clock edge are sufficiently steep
the charge distribute equally on the two diffusion
node
Q
ch
/2
Q
ch
/2
Oxide
n+ n+
p
AV =
1
C
ox
WL(V
DD
V
A
V
t
)
OUT 2 2 C
L
Prof. Gaetano Palumbo 17
Clock feedthrough and Charge Injection are lower
reducing the transistor dimensions (i.e., W and L)
Both the errors are reduced in Transfer Gates if the
transistor are of equal dimensions.
the charge in the channel of equal NMOS
and PMOS transistors are equal but with
opposite sign
If NMOS and PMOS transistors are equal
and switch off symmetrically the charge in
the C
GS
are equal but opposite
Prof. Gaetano Palumbo 18
9
NMOS-Only TG with Level Restorer
Noise margin reduction of a pass transistor is avoided
with a PMOS transistor in positive feedback which
restores the output value from V
DD
- V
t
to V
DD
V
DD
V
DD
OUT
Prof. Gaetano Palumbo 19
Only a PMOS transistor is needed for a set of TG which
have a common output node
Clock feedthrough and Charge Injection are higher than
than in complementary TG
Reduce the static power consumption of the next inverter
but introduce a contribute due to itself
Design strategy is close to that of ratioed logic
Prof. Gaetano Palumbo 20
10
Design of an NMOS-Only TG
The critical case is when the inner node was previously
restored to V
DD
(output voltage equal to 0), the first
inverter has the input to V
DD
and MR goes from 0 to V
DD
During the transient a direct path between the power
supply and ground exists
V
V
DD
V
DD DD
M2
MR
V
DD MA
X OUT
M1
IN
Prof. Gaetano Palumbo 21
To change the output state node X must be lower than
the inverter threshold voltage V
DD
/2 (the positive
feedback complete the inverter commutation)
To guarantee the above condition consider the Pseudo
NMOS gate M1-MA-MR
V
DD
V
DD
MR
V
DD MA
X
M1
V
DD
Prof. Gaetano Palumbo 22
11
Transistor PMOS is in triode region
W
|2(V
DD
+V
tp
)(V
DD
V
OL
)|(V
DD
V
OL
)
p
n
L +L
M1 MA=
|2(V V )V |V
(W/ L)
MR DD tnOL OL n
W
n
L
M1
+L
MA=
p
(W/ L)
MR
n
If M1-MA are minimum size transistors
|W | W
min
| s
L
min
\ L .
MR
Prof. Gaetano Palumbo 23
CPL
(Complementary Pass-Transistor Logic)
The logic is differential since two
complementary data path are implemented
I1
pass transistor
I1
complementary
I2 I2
In
network
In
pass transistor
F
network
I1 I1
F
I2 I2
In In
F F
Prof. Gaetano Palumbo 24
12
Although differential signal requires extra
circuitry, the differential style results
advantageous in term of transistor number to
implement some complex gates such as adders
The availability of both polarity of every signal
eliminates the need for extra inverter (addition
speed up).
The design is very modular. All gates use
exactly the same topology, only the input are
permutated. Complex gates are implemented
with cascade of standard modules
Prof. Gaetano Palumbo 25
NMOS transistors with V
tn
<-V
tp
are needed to
avoid static power consumption. (The reduced
threshold improve the switching speed)
The low V
tn
leads higher subthreshold current
higher power supply
The low V
tn
determines higher noise margin
Prof. Gaetano Palumbo 26
13
2-input OR/NOR 2-input XOR/XNOR
A B B A
A A A A
B
B
B
B
A+B A+B
A + B A + B
2-input AND/NAND
B A BA
B
B
AB AB
Prof. Gaetano Palumbo 27
3-input AND/NAND 3-input OR/NOR
CA B AB C CA B AB C
A A
B B
A A
B B
ABC ABC A+B+C A+B+C
Prof. Gaetano Palumbo 28
14
Layout of a 4-input NAND CPL
A X
B
B A OUT C D
X Y
X Y
B A OUT C D
A
B X
Y ABCD
X
B B
C Y Y
D
X ABCD
C
X X
D Y
D D
Prof. Gaetano Palumbo 29
A
B
X
A
B
X
Y ABCD
B B
X
C
Y
D
Y
X
ABCD
C
D
Y X X
D D
Prof. Gaetano Palumbo 30
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