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Pass Transistor

Transmission gate and pass-transistor logic use MOS transistors as switches to implement logic functions and complex gates using fewer transistors. This results in faster circuits with reduced parasitic capacitance. Transmission gates use an NMOS and PMOS transistor in parallel to act as a bidirectional switch, providing better noise margins than a single pass-transistor. While the resistance of a transmission gate varies non-linearly with input voltage, it can be approximated as constant to simplify analysis. Transmission gates are commonly used to implement multiplexers and other complex gates.

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112 views13 pages

Pass Transistor

Transmission gate and pass-transistor logic use MOS transistors as switches to implement logic functions and complex gates using fewer transistors. This results in faster circuits with reduced parasitic capacitance. Transmission gates use an NMOS and PMOS transistor in parallel to act as a bidirectional switch, providing better noise margins than a single pass-transistor. While the resistance of a transmission gate varies non-linearly with input voltage, it can be approximated as constant to simplify analysis. Transmission gates are commonly used to implement multiplexers and other complex gates.

Uploaded by

IamIN
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Transmission gate and Pass-Transistor Logic

¾ Advanced logic function or switching scheme


are implemented using the feature of transistor
MOS to work as a simple switch

¾ It has the advantage of being simple and fast.


Complex gates are implemented with the
minimum number of transistors (the reduced
parasitic capacitance results in fast circuits

A OUT
OUT = A ⋅ B
B

Prof. Gaetano Palumbo 1


¾ The static and transient performance strongly depend
upon the availability of an high quality switch with low
parasitic resistance and capacitance
‘ A single transistor is used as switch: Pass
Transistor
‘ N- and P-transistor are used: Transmission Gate

¾ Implementation with a single transistor reduces the noise


margin and causes static power consumption
VDD

VDD -Vtn OUT


VDD VDD -Vtn 0 -Vtp VDD

VDD 0 VDD

Prof. Gaetano Palumbo 2


Transmission Gate Transmission Gate Simbol

C C

A B A B

C
C
¾ Transmission gate has better noise margin than
pass transistor
0 0

VDD VDD 0 0

VDD VDD

Prof. Gaetano Palumbo 3


¾ Transmission gate is very efficient to implement
some complex gate (MUX, DEMUX and XOR)
2-input Multiplexer 4-input Multiplexer
X Y

S A

X Y
A
OUT B
S OUT
X Y
B
C

S X Y

OUT = A ⋅ S + B ⋅ S D

X Y

OUT = A ⋅ X ⋅ Y + B ⋅ X ⋅ Y + C ⋅ X ⋅ Y + D ⋅ X ⋅ Y

Prof. Gaetano Palumbo 4


4-input MUX as cascade of 2-input MUX
X
A Y

B
Y OUT
X
C
X

D
Y
X

OUT = A ⋅ X ⋅ Y + B ⋅ X ⋅ Y + C ⋅ X ⋅ Y + D ⋅ X ⋅ Y

¾ More parasitic capacitances on internal nodes

Prof. Gaetano Palumbo 5


2-input XOR

¾ Can be implemented with a 2-input MUX, or:


B

A OUT A OUT = A ⋅ B + A ⋅ B

¾ Only the left side can implement the XOR logic


function, but a threshold voltages is lost at the
output without implementing the right side circuit

Prof. Gaetano Palumbo 6


Transmission Gate MUX Layout

S S
VDD
S
TG1
A INV
OUT
S
OUT
B TG2 INV
TG2 TG1
S
GND
A S S B

Prof. Gaetano Palumbo 7


Transmission Gate Resistance

30000.0
Rn
(W/L)p =(W/L)n =
1.8/1.2
20000.0
R (Ohm)

Rp
0
10000.0
Req IN OUT

0.0
0.0 1.0 2.0 3.0 4.0 5.0 5V
Vout

Prof. Gaetano Palumbo 8


¾ Despite the nonlinear behavior of the NMOS and
PMOS transistors varying the input voltage, the
resistance of a transmission gate is almost
constant

¾ We can approximate its value with that given by


the parallel of transistor resistances, assuming both
in linear region

1 dI D dI D
= Geq = + =
Req dVDS n dVDS p

= β n (VGSn − Vtn − VDSn ) + β p (VSGp + Vtp − VSDp )

Prof. Gaetano Palumbo 9


¾ If the gate-source voltage is around VDD/2, the two
transistors are in linear region (VDS≈0)
1  VDD   VDD 
= βn  − Vtn  + β p  + Vtp 
Req  2   2 

¾ Assuming the threshold voltage and the gain factor


of the NMOS and PMOS are equal (PMOS twice
the NMOS)
1
Req =
µ n Cox (W / L) n (VDD − 2Vt )

¾ To reduce parasitic effects both transistors are


generally minimum size

Prof. Gaetano Palumbo 10


Transmission Gate Delay

0 0 0

VDD C1 VDD C2 VDD C3 VDD Cn

R1 R2 R3 Rn

C1 C2 C3 Cn

Prof. Gaetano Palumbo 11


¾ Applying the open-circuit time constant

n i n n(n + 1)
τ = ∑ Ci ∑ R j = RC ∑ i = RC
i =1 j =1 i =1 2

R=Req and C=4(Cgs+Csb)

¾ Approximating the circuit with a pole-dominant


behavior τPD= 0.69τ . It increase with the square
of n

¾ We can introduce buffer to minimize τPD

Prof. Gaetano Palumbo 12


R R R R R R

C C C C C C

n m(m + 1)  n 
τ PD = 0.69  RC  +  − 1τ PDinv
m 2  m 

d
τ PD = 0
dm 2τ PDinv
mopt =
n n 0.69 RC
0.69 RC − 2 τ PDinv = 0
2 m

Typical value 3-4

Prof. Gaetano Palumbo 13

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