A HIGH-RESOLUTION FLASH TIME-TO-DIGITAL CONVERTER AND CALIBRATION
SCHEME
Peter M. Levine and Gordon W. Roberts
Microelectronics and Computer Systems Laboratory, McGill University
3480 University Street, Montreal, Quebec, CANADA H3A 2A7
{plevin, roberts}@macs.ece.mcgill.ca
Abstract
Flash time-to-digital converters (TDCs) are well-suited for
use in on-chip timing measurement systems because they
can be operated at high speeds, offer low test time, and are
relatively easy to integrate. However, clock jitter in mod-
ern integrated circuits is often on the same order of mag-
nitude as the temporal resolution of the TDC itself. There-
fore, techniques are required to increase the resolution of
these devices, while ensuring timing accuracy. This paper
presents a high-resolution ash TDC that exploits the ran-
dom offsets on ip-ops or arbiters to perform time quanti-
zation. It also describes a novel technique based on additive
temporal noise to accurately calibrate the measurement de-
vice. Simulation and experimental results reveal that the
latter method can calibrate the high-resolution ash TDC
down to 5 ps within reasonable error limits. In addition,
accurate timing measurement of jitter below 14 ps has been
experimentally validated using a high-resolution ash TDC
fabricated in a 0.18-m CMOS process.
1. Introduction
On-chip measurement of electrical phenomena using cus-
tom mixed-signal test cores is an attractive method for over-
coming the bandwidth limitations and interconnect timing-
related uncertainties common in traditional off-chip test sys-
tems [1]. In particular, on-chip timing measurement of clock
jitter has become increasingly important as clock frequen-
cies approach 10 GHz [2]. At these speeds, a peak-to-peak
jitter of only 10 ps translates to a 10% uncertainty in clock-
edge placement. This demonstrates the need for on-chip
timing measurement devices that possess resolutions below
this level.
Time-to-digital converters (TDCs) have traditionally
been used to evaluate timing performance in on-chip test
systems [3]. But because these are implemented in the same
semiconductor technology as the device-under-test (DUT),
the ne temporal resolutions needed in modern applications
often require circuits that occupy a large silicon area or con-
sume a great deal of power [4]. In addition, temporal non-
linearity in the TDC caused by process variation must of-
ten be corrected with additional complex tuning circuitry.
Therefore, a TDC that has high temporal resolution, is small
in size, and perhaps exploits the effects of process variation,
would be a valuable component in any on-chip test system.
This paper presents a high-resolution ash TDC suit-
able for clock jitter measurement. Such a TDC tradition-
ally uses ip-ops or arbiters to compare signal phases and
relies upon buffer delays to quantize a time interval. How-
ever, one way to save silicon area and achieve higher reso-
lution is to remove the delay buffers completely and instead
use only ip-op temporal offsets caused by process vari-
ation for time quantization. This type of ash converter,
known as a sampling offset TDC [5], can be implemented
easily in any standard CMOS process and has the potential
for very-high-speed operation. Although such a TDC lacks
wide dynamic range, it can be used to quantify clock jitter
in which the timing uncertainty is a small percentage of the
clock period.
Calibration is an important procedure that every mea-
surement instrument must undergo before use. TDC cali-
bration is normally done by exciting the converter with a
series of known time intervals and then correlating the digi-
tal output with the input each time. However, such a scheme
becomes more difcult as the desired resolution falls be-
low 10 ps. This is because the accuracy of on-chip tim-
ing generators [often implemented using delay-locked loops
(DLLs)] is limited by the jitter and mismatch of the circuitry
itself. Conversely, off-chip pulse generators can produce
such time intervals accurately, but these may be too costly
for a production-test environment.
Since the sampling offset TDC is known to have res-
olutions which vary from a few picoseconds to tens of pi-
coseconds [6], calibration of this device is extremely chal-
lenging. Therefore, to reduce the demands on the timing
generation circuitry, a novel calibration technique based on
additive temporal noise will be introduced.
This paper is organized as follows: Section 2 presents
the necessary background for understanding ash TDCs in
general and the sampling offset TDC in particular. Sec-
tion 3 discusses traditional techniques for calibrating the
sampling offset TDC while Section 4 describes a new cali-
bration method involving added temporal noise. Simulation
results showing the viability of the proposed technique, as
ITC INTERNATIONAL TEST CONFERENCE
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Paper 40.2
1148
well as experimental results obtained using a programmable
logic device, are also included in the latter section. Sec-
tion 5 discusses the design of a custom sampling offset TDC
integrated circuit (IC) fabricated in a 0.18-m CMOS pro-
cess. Experimental results from calibration of this device
are included in addition to jitter measurement results. Con-
clusions are drawn and future work is discussed in Sec-
tion 6.
2. Flash Time-to-Digital Converters
Flash TDCs are analogous to ash analog-to-digital con-
verters for voltage amplitude encoding and operate by com-
paring a signal edge to various reference edges all displaced
in time. The elements which compare the input signal to
the reference are usually ip-ops or arbiters (note that an
arbiter is a circuit that decides which of two input signals
arrived rst). For simplicity, ip-ops and arbiters will be
referred to interchangeably in this paper. The three main
types of ash TDC are described next.
2.1. Single Delay Chain
In the single delay chain ash TDC shown in Fig. 1, each
buffer produces a delay equal to [7]. To ensure that is
known accurately, the delay chain is often controlled by a
DLL [8].
Q
0
Q
1
Q
2
Q
M-1
Start
Stop
Fig. 1. Delay chain ash converter.
Suppose it is desired to determine the time difference
T between the rising edges of pulses P
start
and P
stop
using
the 8-level delay chain converter in Fig. 2. Each ip-op
compares the displacement in time of the delayed P
start
to
that of P
stop
. The thermometer-encoded output indicates the
value of T, assuming the ip-ops are given sufcient time
to resolve. The drawback to this implementation is that the
temporal resolution can be no smaller than a single gate de-
lay.
P
stop
P
start
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
0
0
0
0
0
0
0
1
1
P
start
aIter 1 delay
P
start
aIter 2 delays
P
start
aIter 3 delays
P
start
aIter 4 delays
P
start
aIter 5 delays
P
start
aIter 6 delays
P
start
aIter 7 delays
Thermometer
code output
6 5 T
T
Indicates that
Fig. 2. Operation of an 8-level delay chain ash converter.
2.2. Vernier Delay
To achieve sub-gate time resolution, the ash converter can
be constructed with a Vernier delay line as shown in Fig. 3
[8]. This architecture achieves a resolution of
1
2
, where
1
>
2
.
Q
0
Q
1
Q
2
Q
M-1
Start
Stop
Fig. 3. Vernier delay ash converter.
2.3. Sampling Offset
A ash converter that relies solely on ip-op transistor
mismatch can be used to obtain ne time resolution without
separate delay buffers. This type of converter is known as a
sampling offset TDC (SOTDC) [5] and Fig. 4 shows how
it is related to the basic Vernier delay TDC. As displayed
in the diagram, the Vernier delay ash converter is rst rep-
resented as a single delay chain in which each buffer has
Paper 40.2
1149
delay =
1
2
. Note that all ip-ops are assumed to
be ideal (i.e., they possess no transistor mismatch and are
free from noise). An alternative form of the delay chain
ash, in which each buffer has a cumulative delay, can then
be drawn. Finally, the latter model can be replaced by the
SOTDC, in which each ideal ip-op has been substituted
for one with transistor mismatch. Note that the offsets of
the non-ideal ip-ops will be random, and not monotonic
or multiples of a fundamental offset as Fig. 4 might seem to
suggest.
Q
0
Q
1
Q
2
Q
M-1
Q
0
Q
1
Q
2
Q
M-1
Ideal Flip-Flops
Q
0
Q
1
Q
2
Q
M-1
Non-Ideal Flip-
Flops
1. Vernier Delay Flash
Converter
2. Single Delay Chain Flash
Converter
3. Alternative Representation oI
Delay Chain Flash Converter
4. Sampling OIIset Flash
Converter
Start
Stop
Start
Stop
Start
Stop
Ideal Flip-Flops
Ideal Flip-Flops
Q
0
Start
Stop
Q
1
Q
2
Q
M-1
Fig. 4. Relationship of sampling offset ash TDC to basic
Vernier delay TDC.
Simulations and experiments conducted in [6] and [9]
conrm that mismatches due to process variation can pro-
duce time offsets from 30 ps down to 2 ps, depending on the
ip-op architecture and semiconductor technology used.
Of course, calibration is required to determine these off-
sets before the ip-ops can be used for time measurement.
Common calibration procedures are described next.
3. Traditional TDC Calibration
The goal of calibration is to determine the time offset t
os
of
each ip-op or arbiter in the TDC. For purposes of analy-
sis, a ip-op model is dened rst.
3.1. Flip-Flop Model
An ideal rising-edge-triggered ip-op has t
os
= 0 and is
free from noise. A non-ideal ip-op can be modeled as
an ideal ip-op with t
os
= 0 as well as a source of thermal
noise as shown in Fig. 5(a) [10]. The noise voltage V
noise
is
assumed to follow a Gaussian distribution with zero mean
and standard deviation .
An alternative ip-op model, which is more appropri-
ate in the context of time measurement, is shown in Fig. 5(b).
Here, the ideal ip-op takes a time difference T
eff
as in-
put and produces a 1 if T
eff
> 0 and a 0 otherwise. The
input T is equal to t
clock
t
data
, where t
clock
and t
data
are
the times of the rising edges of
clock
and
data
in Fig. 5(a),
respectively. In addition, V
noise
in the original model is ex-
pressed as the temporal noise t
noise
. Assuming a linear rela-
tionship between these two variables, t
noise
follows a Gaus-
sian distribution with zero mean and standard deviation
FF
.
Ideal Flip-
Flop
t
os
J
noise
data
clock
Non-Ideal Flip-Flop
(a)
Q
T
eff
t
noise
t
os
Ideal Flip-
Flop
T
Non-Ideal Flip-Flop
(b)
Fig. 5. Flip-op models. (a) Voltage model (b) Time model
3.2. Indirect Calibration
An indirect calibration technique, involving the use of un-
correlated signals to nd the relative offsets of the ip-ops
in an SOTDC, was experimentally veried in [6]. An im-
plementation of this is displayed in Fig. 6(a), where
1
and
2
are square waves with constant frequencies f
1
and f
2
.
These are input to two ip-ops having offsets t
os
1
and t
os
2
.
The relative ip-op offset is given by
12
= t
os
1
t
os
2
and
it is assumed that
12
t
noise
.
Fig. 6(b) shows how
12
can be found empirically. As-
suming that f
2
is only slightly greater than f
1
,
1
will appear
to move past
2
in time. This ensures that the rising edge
of
1
is uniformly distributed over the interval dened by
the period of
2
. Therefore, the probability P
12
that the cir-
cled rising edge of
1
in Fig. 6(b) will land in the shaded
Paper 40.2
1150
interval
12
is given by
P
12
=
12
1/ f
2
. (1)
When this occurs, ip-op output Q
1
in Fig. 6(a) will be
0 while Q
2
will be 1. Furthermore, measurements with
the circled edge of
1
residing in
12
will occur with a fre-
quency f
p
of
f
p
=
12
1/ f
2
f
1
=
12
f
1
f
2
. (2)
Therefore, the periodic output fromthe ANDgate in Fig. 6(a)
will have a frequency given by (2). This equation can then
be solved for
12
to obtain the relative time offsets of the
ip-ops.
Q
1
Q
2
Ideal Flip-
Flops
1
os
t
2
os
t
1
2
1/f
1
1/f
2
1/f
p
(a)
1/f
2
2
1
2
aIter t
os1
1
os
t
2
os
t
12
1/f
1
2
aIter t
os2
(b)
Fig. 6. Indirect calibration of two ip-ops. (a) Systemused
to determine relative ip-op offset (noise sources are not
shown for simplicity) (b) Clocks in the indirect calibration
system.
Knowledge of the relative ip-op offsets can be used
to obtain a TDC transfer function like that shown for a 5-
level converter in Fig. 7. In this curve, the ip-op offsets
are all expressed relative to the same ip-op. However, the
time from the absolute reference [which is
2
in Fig. 6(a)]
to the rst offset cannot be surmised from the indirect cali-
bration. Consequently, if it is desired to measure jitter hav-
ing a Gaussian distribution using an SOTDC calibrated this
way, only the standard deviation (or equivalently, the rms
value) of the jitter can be found. Furthermore, no infor-
mation about the mean value of the jitter (i.e., how far the
Time Irom absolute reIerence
D
i
g
i
t
a
l
o
u
t
p
u
t
c
o
d
e
12
13
14
15
Unknown
0
Fig. 7. Transfer curve of a TDC determined using an indi-
rect calibration.
jittery clock deviates, on average, from the reference signal)
can be surmised.
However, to acquire both the mean and standard devi-
ation of the timing uncertainty, the absolute values of the
offsets must be ascertained. To determine the absolute off-
sets using the indirect calibration, some information about
the offset statistics must be known. Although it could be
assumed that the mean offset of a large number of ip-ops
constructed on the same die will be zero, this may be invalid
unless care is taken in the layout to ensure that all ip-ops
experience similar process variation. Since this may be dif-
cult to achieve in practice, the direct calibration technique
described next can be used.
3.3. Direct Calibration
In a direct calibration, t
os
of a single ip-op is found by
setting T to M different values in the range (, +) and
recording the ip-op output each time as shown in Fig. 8.
This process is then repeated N times.
data
clock
t
data
t
clock
T
Q
Fig. 8. Direct calibration of a ip-op.
For simplicity, assume that a ip-op under calibration
has t
os
= 0. The data collected from each of the N trials, as
described above, may appear as in Fig. 9. Note that the pres-
ence of thermal noise causes the ip-op output to be dif-
ferent on each trial. By summing the number of times n the
output from the ip-op is 1 for each T, the histogram in
Fig. 10 can be plotted. Next, the histogram can be expressed
as a cumulative distribution function (cdf) by dividing each
n by N and then curve-tting, as shown in Fig. 11(a). In the
Paper 40.2
1151
cdf, the probability P of the event { T} is given by
P( T) =
T (t
os
)
FF
, (3)
where is a randomtime and () is the standard Gaussian
cdf. Inspection of the cdf reveals that P( T =0) =0.5
for a ip-op having t
os
= 0.
0
Trial 1 Trial 2 Trial N
T
0
1
F
l
i
p
-
F
l
o
p
O
u
t
p
u
t
0 T
0
1
0 T
0
1
Fig. 9. Results from each trial of ip-op calibration.
N
u
m
b
e
r
o
I
t
i
m
e
s
I
l
i
p
-
I
l
o
p
o
u
t
p
u
t
i
s
1
`
0
N
0
T
Fig. 10. Histogram result of ip-op calibration.
0
1.0
0.5
0
T
P
(
)
(a)
0
1.0
0.5
T
oIIset
T0 T-t
os
P
(
)
(b)
Fig. 11. Calibration cdfs of ip-ops having different off-
sets. (a) Zero offset (b) Non-zero offset
Now consider the calibration of a ip-op for which
t
os
= 0. Fig. 11(b) shows the cdf of such a device and it is
apparent that P( 0) = 0.5.
The main drawback to this calibration method is that to
accurately produce the cdf in Fig. 11(b) and obtain t
os
, T
may have to be set to values on the order of a few picosec-
onds. Such accuracy is difcult to achieve with on-chip sig-
nal generators. Furthermore, use of high-resolution off-chip
generators may be too impractical or expensive. Therefore,
an improved direct calibration method is described next.
4. Improved TDC Calibration Based on
Added Noise
Performing a direct calibration on a ip-op with a t
os
of
a few picoseconds and a
FF
of a few hundred femtosec-
onds is difcult because T cannot be made small enough
to accurately produce a cdf curve. It would be helpful if
FF
was much larger, say in the order of tens or even hundreds of
picoseconds, so that points on the cdf could be measured ac-
curately. With this data, t
os
could be found by curve-tting.
Fortunately, it is possible to increase
FF
by adding a
temporal noise to that already present on the ip-op in-
puts. A model for this is shown in Fig. 12, where t
noise
added
is
a Gaussian noise source with zero mean and standard devi-
ation
added
and t
noise
FF
is the thermal noise. Assuming the
summed random variables are independent, the total noise
on the ip-op will have zero mean and a standard deviation
that is the square root of the sum of squares of
added
and
FF
. Furthermore, if
added
FF
, the total noise standard
deviation will be very close to
added
.
Q
Ideal Flip-
Flop
T
eff
T
t
os
Non-Ideal Flip-Flop
t
noise
added
t
noise
FF
Fig. 12. Flip-op model with added noise source.
The sum of the time T and the noise t
noise
added
is sim-
ply a set of times which follow a Gaussian distribution with
mean T and standard deviation
added
. Calibration using
these times is performed just like a traditional direct cali-
bration, however the need to set T to very small values is
eliminated. To see why, consider the top graph in Fig. 13
where each set of input times is expressed as a probability
density function (pdf). As T is increased in discrete steps
from to +, a certain number of input times cross the
offset threshold of the ip-op (represented by the dark ver-
tical dashed line in the gure), forcing the output to 1. If
N points are collected from each set of distribution, a his-
togram can be produced as before. Fitting a Gaussian cdf
to the data, the standard deviation of the curve will equal
added
, while the mean will correspond to t
os
, as shown in
the bottom graph in Fig. 13.
4.1. Simulation Results
Simulations were carried out to demonstrate the viability
of the proposed calibration technique. The ip-op model
in Fig. 12 was built using MATLAB with
FF
= 0.35 ps
(this was the measured value reported in [6]). The value of
added
was set to 250 ps while T was moved from400 ps
Paper 40.2
1152
T
1
T
2
T
3
T
M
0.5
0
1.0
p
d
I
T
T
Gaussian pdI
with mean
T
M
and std.
dev.
added
Flip-Ilop
output is 0`
Flip-Ilop
output is 1`
-t
os
P
(
)
Fig. 13. Direct calibration based on addition of temporal
noise.
to +400 ps in steps of 40 ps. Such temporal resolution can
be handled with good accuracy by modern pulse generators
or on-chip DLLs. Time t
os
was set to various values in the
range (40 ps,+40 ps) and N = 10
5
.
Fig.14 shows the result from a single ip-op calibra-
tion. A
2
tting algorithm [11] was used and it is clear that
the tted cdf and the actual ip-op curve described by (3)
nearly coincide at the value of T for which P = 0.5.
-6 -4 -2 0 2 4 6
x 10
-10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Data point from cal. w/ added noise
Fitted curve for cal. w/ added noise
True flip-flop curve
P
(
T
)
T (s)
Fig. 14. Simulated calibration result. Actual t
os
was
+17.4 ps while offset from tted curve was +17.1 ps.
Table 1 compares the actual t
os
of a ip-op to that de-
termined through calibration. The results for each calibrated
t
os
are within acceptable error levels. Note that the tted
values (not shown) were very close to 250 ps in all cases.
4.1.1. Calibration Time
Calibration of the SOTDC using the method based on added
noise depends on the number of values M of T used, the
Table 1. Comparison of calibrated to actual offset fromsim-
ulation.
Actual Offset (ps) Calibrated Offset (ps) % Error
35.0 34.6 1.1
2.2 2.3 4.5
5.0 5.3 6.0
17.4 17.1 1.7
Table 2. Comparison of mean of absolute value of percent-
age errors from calibration of a ip-op for different values
of N
N % Error (Mean of 30 Runs)
10
6
2.83
10
5
12.2
10
4
34.3
10
3
85.2
number of trials N run for each of these values, and the rate
f at which the trials are executed. Since all levels of the
SOTDC can be characterized simultaneously for each T,
the calibration time t
cal
is given by
t
cal
= MN/ f . (4)
As an example, a calibration with M = 21, N = 10
5
, and
f = 25 MHz, takes 84.0 ms. Of course, additional time is
needed to perform the curve-tting procedure.
Since the calibration technique is based on a statistical
method, decreasing the test time by reducing N will also
reduce the accuracy in nding t
os
. This fact is revealed in
Table 2, in which the mean of the absolute value of the per-
centage errors from the simulated calibration of a ip-op
having t
os
= +2.0 ps is determined for N varying from 10
6
down to 10
3
.
4.2. Preliminary Experimental Results
To gain preliminary experimental evidence in support of
the proposed calibration technique, one level of an SOTDC
was synthesized using an Altera EPM7128SLC84-7 com-
plex programmable logic device (CPLD). As shown in the
circuit schematic in Fig. 15, the leftmost ip-op performs
the timing measurement by comparing the highly accurate
reference
clock
with the signal under test
data
. The two
additional ip-ops attached in series to the main ip-op
are used to reduce the probability that a metastable value is
latched by the counter. The 20-bit counter is enabled when
the output from the third ip-op is high.
To perform the direct calibration discussed in Section
3.3, the apparatus shown in Fig. 16(a) was constructed. The
Paper 40.2
1153
data
clock
Enable
CountOut 20-Bit Counter
Fig. 15. Single-level SOTDC synthesized on a CPLD.
CPLD containing the synthesized TDC resided on a multi-
layer Altera UP1 development board. This was interfaced
with an Agilent 81334A dual-channel pulse/pattern gener-
ator having a delay resolution of 1 ps, a delay accuracy of
20 ps, and a total jitter of 2 ps rms [12] (although the lat-
ter specication was empirically veried to be lower). The
generator was used to produce two calibration clocks and
control their phase relationship in order to generate the nec-
essary T.
Calibration involving added noise was performed using
the experimental setup in Fig. 16(b). This is similar to that
in (a), however an Agilent 33120A function generator, set in
noise mode, was connected to the delay control input of the
pulse generator. This allowed the phase of the clock signal
from one channel to be varied according to the amplitude of
a band-limited Gaussian noise signal.
CPLD
Delay Control In
data
clock
Pulse/Pattern
Generator
Ch. 1
Ch. 2
(a)
CPLD
Delay Control In
data
clock
Pulse/Pattern
Generator
Ch. 1
Ch. 2
Function
Generator
Out
(b)
Fig. 16. Experimental setups to perform TDC calibration.
(a) Basic direct calibration technique. (b) Calibration tech-
nique based on added noise.
Under both calibration techniques, the clock and data
frequencies were set to 20 MHz. The number of cycles con-
sidered for each value of T was N =1,048,575. In the
direct calibration technique, T was adjusted in 1-ps incre-
ments in order to nd the ip-op offset. In the technique
based on added noise, T was adjusted in increments of
40 ps. Finally,
added
was found to be around 250 ps ac-
cording to an external oscilloscope.
Results from the calibration techniques are shown in
Fig. 17. A t
os
of 81 ps was found using the basic direct
calibration while an offset of 71 ps was determined from
the technique based on added noise. This results in an er-
ror of 12.3%. The larger error compared to the simulation
results is likely due to nonlinearities in the delay control cir-
cuitry of the pulse generator. Such nonlinearities can cause
the variation in T to be less Gaussian, which in turn can
produce a bias error in the results. The tted value of
added
was 264 ps, which is within the expected range. In addition,
the tted value of
FF
was approximately 0.75 ps.
-3 -2 -1 0 1 2 3 4
x 10
-10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Data point from cal. w/ added noise
Fitted curve from cal. w/ added noise
Data point from trad. direct cal.
Fitted curve from trad. direct cal.
P
(
T
)
T (s)
Fig. 17. Experimental results of calibration of a single ip-
op.
5. Custom IC Implementation
To obtain better timing resolution than what can be achieved
using a CPLD, a 64-level SOTDC was designed and fabri-
cated in a standard 0.18-m CMOS process. Each level of
the SOTDC was built as shown in Fig. 18 and consists of an
arbiter, ip-ops to latch the arbiter output, and a counter.
Some additional circuitry to take the contents of the counter
off chip was also implemented, but this is not shown for
simplicity.
data
FF
Enable
CountOut
20-Bit LFSR Counter
ref
1
2
Q
Arbiter
Fig. 18. Single level of custom ash SOTDC.
The arbiter displayed in Fig. 19 is used to compare the
rising edge of the highly accurate reference signal
ref
to
Paper 40.2
1154
that of
data
[6]. If
data
arrives before
ref
, positive feed-
back causes the output Q to go to 1; otherwise it goes to
0. Also, this arbiter has the property that its output is not
held throughout the entire period of
ref
. As a result, the
periodic signal
FF
in Fig. 18 is required so that the syn-
chronizing ip-ops and counter following the arbiter can
successfully latch the data after each rising edge of
ref
. Al-
ternatively,
FF
could be eliminated and a buffer-delayed
ref
used to clock the ip-ops. However, the greater input
capacitance seen by
ref
compared to
data
could skew the
timing measurements somewhat.
Q
1 2
Q
Fig. 19. Arbiter used in SOTDC.
The 20-bit counter is implemented as a two-tap, max-
imal-length linear feedback shift register (LFSR). Such an
architecture employs fewer logic gates and has a simpler
routing complexity than a regular ripple-carry counter. In
addition, the 20-bit LFSR can be operated at a higher speed
than a ripple counter because its critical path consists of
only a single XOR gate.
The fabricated SOTDC chip is displayed in Fig. 20.
The IC contains two identical sections, each consisting of
32 converter levels. These are distinguished by the dashed
outlines in the gure. Since the SOTDC was built using
relatively large fully-static CMOS ip-ops, each level oc-
cupies an area of approximately 0.024 mm
2
. However, in
a separate layout of the SOTDC comprised of proprietary
standard-cell ip-ops (not shown), this area was reduced
to only 0.0032 mm
2
.
5.1. Calibration of the Custom IC
The custom IC was mounted on a two-layer printed-circuit
board (PCB) and was calibrated using a test apparatus simi-
lar to that shown in Fig. 16. A Teradyne A567 mixed-signal
production tester was used to assert digital control signals
and store output from the IC.
For the calibration based on added noise, T was in-
creased from 100 ps to +100 ps in steps of 20 ps. This
was done by controlling the phase difference between two
clocks running at 25 MHz. The standard deviation of added
1 Level
1 mm
32 Levels
32 Levels
Fig. 20. A 64-level SOTDC implemented in a 0.18-m
CMOS process. Each section consists of 32 levels.
noise was approximately 29.8 ps (as measured using an ex-
ternal oscilloscope) and N = 10
5
. Both the step size of T
and
FF
were reduced compared to the test setup in Sec-
tion 4.2 because the linear range of the delay control cir-
cuitry in the current apparatus was found to be smaller.
Fig. 21 shows the calibration results for one level of
the SOTDC. The traditional calibration, in which T was
incremented in steps of 5 ps, gives a t
os
of 9.78 ps while
the proposed method produces a t
os
of 9.80 ps. Best-t
using the former method is 9.28 ps and that for the latter is
30.38 ps. Note that the larger present in the traditional
calibration in the current test setup, compared to the CPLD
results, is due to the presence of noise and interference on
the PCB. These should be signicantly reduced when the IC
is tested on a multi-layer board (as in Section 4.2), in which
the signal, supply, and ground planes are isolated.
Fig. 22 displays the calibrated offsets for 32 levels in
one section of the custom IC. Results from both calibration
methods are included and these are ordered from smallest
to largest. From the technique based on added noise, the
offsets are distributed from about +3 ps to +16 ps, giving a
dynamic range of 13 ps.
The percentage error between each offset, calibrated in
the traditional way and using the proposed technique, is
shown in Fig. 23. The error on only two offsets exceeds
30% and the average of the absolute value of the percent-
age errors is 14%. Such an error is reasonable considering
the fact that direct measurements using a source without pi-
cosecond resolution would produce much higher errors.
It would have been desirable to have the arbiter offsets
distributed around zero. This is so that deviations in the
edge placement of
data
on both sides of the
ref
edge could
be detected by the SOTDC. Unfortunately, asymmetries in
Paper 40.2
1155
-1 -0.5 0 0.5 1
x 10
-10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Data point from cal. w/ added noise
Fitted curve from cal. w/ added noise
Data point from trad. direct cal.
Fitted curve from trad. direct cal.
P
(
T
)
T (s)
Fig. 21. Calibration of a single level of the custom SOTDC.
0 5 10 15 20 25 30 35
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
x 10
-11
Calibration with added noise
Traditional direct calibration
SOTDC Level (Ordered)
O
I
I
s
e
t
(
s
)
Fig. 22. Ordered offsets from one section of the custom IC
determined using traditional and proposed calibration meth-
ods.
the original arbiter layout, produced while designing the IC,
likely caused all the offsets to favor the same input.
5.2. Jitter Measurement using the Custom IC
The custom SOTDC was used to measure Gaussian jitter.
Jitter was produced by varying the phase difference between
two 25-MHz clocks according to a Gaussian distribution
having a mean of 9.4 ps and a peak-to-peak value of 79.2 ps.
These measurements were veried by rst connecting the
clock generator directly to a LeCroy SDA 6000 serial data
analyzer having a jitter noise oor of 1 ps rms [13].
The rms value of the jitter measured by the analyzer
was 9.8 ps, however, as discussed in Section 5.1, noise and
interference on the PCB adds a jitter component to this. As-
suming that this contribution has a mean of zero and adds
0 5 10 15 20 25 30 35
-50
-40
-30
-20
-10
0
10
20
30
SOTDC Level (Ordered)
E
r
r
o
r
(
)
Fig. 23. Percentage error for each offset.
directly to, and is uncorrelated with, the jitter produced by
the pulse generator, the jitter under test has an actual of
9.8
2
+9.28
2
= 13.5 ps.
Fig. 24 shows the jitter histogram determined using the
custom SOTDC. The measured mean of 10
5
samples was
11.0 ps, while the rms value was 14.5 ps. These values are in
agreement with those measured by the serial data analyzer.
-0.5 0 0.5 1 1.5 2 2.5
x 10
-11
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Fitted Gaussian curve
Gaussian jitter cdf measured by SOTDC
T (s)
P
(
T
)
Fig. 24. Gaussian jitter histogram measured using the cus-
tom SOTDC. A Gaussian cdf has been t to the data.
Accurate measurement of the peak-to-peak jitter was
not possible because the dynamic range of the SOTDC was
limited to only 13 ps. This is the main drawback of the
SOTDC architecture in its current form.
5.3. Test Time
Test time for jitter measurement is equal to N/ f . There-
fore, the measurement carried out in Section 5.2 took only
4.0 ms. This short test time is characteristic of ash TDCs.
Paper 40.2
1156
6. Conclusions and Future Work
A high-resolution ash TDC for on-chip timing measure-
ment has been presented. A novel technique to calibrate this
converter using additive temporal noise has also been de-
scribed. Simulation results and experimental data obtained
from a programmable logic device and custom IC indicate
that this method can be used to calibrate the measurement
device down to picoseconds. Gaussian jitter measurement
was also veried experimentally using a ash SOTDC im-
plemented in a 0.18-m CMOS process.
6.1. Future Work
The calibration technique based on added noise reduces the
resolution requirements on the timing generator needed to
calibrate the SOTDC. This feature can be readily applied to
production testing of mixed-signal ICs in which the off-chip
production tester or on-chip DLL in use cannot produce
phase differences with picosecond resolution. To alleviate
this shortcoming, two voltage-controlled delay buffers, sim-
ilar to those used in [8], can be placed on the IC as shown
in Fig. 25. With this setup, the delay of clock
ref
is modu-
lated according to a voltage signal having Gaussian ampli-
tude statistics V
noise
while the delay of
data
is held constant
by dc voltage V
dc
. As a result, the phase difference between
buffer outputs
ref
and
data
can be made to have a Gaussian
statistical variation.
SOTDC
data
ref
J
noise
J
dc
data
ref
Production
Tester or
On-Chip
DLL
On-Chip Variable
Delay BuIIers
Fig. 25. Proposed hardware implementation of a system to
calibrate an SOTDC.
Of course, calibration of the delay buffers is necessary
for determining the relationship between the applied control
voltage and delay. Although a nonlinear relationship exists
between these two variables [8], a region exists where the
voltage and delay vary in a linear way. Operation in this
region is necessary so that the Gaussian characteristics of
the control voltage translate linearly to the resulting delay.
Another issue that must be considered in the proposed
system is the additional skew generated by the delay buffers
themselves. Since process variation could induce skews in
the order of several picoseconds on
ref
and
data
, matching
between both buffers is extremely important. Fortunately,
the use of larger transistors and careful layout techniques
can help ensure a small degree of mismatch. This system
has yet to be experimentally veried and is a topic of future
work by the authors.
7. Acknowledgements
This work was supported by the Canadian Microelectronics
Corporation and Micronet, a Canadian Network of Centres
of Excellence focused on microelectronic devices, circuits,
and systems.
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SDA Datasheet.pdf
Paper 40.2
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