Alexandria University
Faculty of Engineering
Electrical department
2nd year - 2014
VHDL Report
VHDL Project
Serial Data Receiver
Prepared By:
Mohamed Khaled Aly
Mohamed Said
Mohamed Salah Bassuny
Mahmoud Gaber
Marwan Salem
April, 2014
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VHDL Project
Serial Data Receiver
Steps of Design:
Our aim is to receive a serial data input from the transmitter and
put it in a frame of 10 timeslots .
the first time slot is the start bit , the data input will be transmitted
to the receiver when start = '1' , otherwise it will stop receiving
bits.
the ninth bit is the parity checking bit , which = '1' when number of
ones in the data out is odd , if the parity checked from the receiver
don't match the parity supposed from the transmitter it will cause
an error called parity_err .
the tenth bit is the stop bit , when stop = '0' , error = '1'.
if there is no error , then data_valid = '1
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VHDL Project
Serial Data Receiver
VHDL Code (Method 1)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sdr is
Port ( din,start,stop,clk: in STD_LOGIC;
data_valid: out STD_LOGIC);
end sdr ;
architecture Behavioral of sdr is
signal p : std_logic_vector (5 downto 0) ;
signal dout: std_logic_vector (6 downto 0) := "0000000" ;
--Initializing
signal parity,err,parity_err : std_logic ;
signal parity_supposed : std_logic := '0' ;
begin
process (clk)
begin
if (start='1')then
if (clk'event and clk='1')then
dout(5 downto 0) <= dout(6 downto 1);
--Data shifting
dout(6)<= din ;
--New bit Assigning
end if ;
end if;
end process;
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VHDL Project
Serial Data Receiver
parity_err <= parity xor parity_supposed ;
--Error checking
err <= '0' when (stop = '1' and (parity_err = '0') )
else '1' ;
data_valid <= not err ;
p(5) <= dout(5) xor dout(6) ;
--Parity checking
generatePARITY: for i in 4 downto 0 generate
p(i) <= p (i+1) xor dout(i);
end generate;
parity <= p(0);
end Behavioral;
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VHDL Project
Serial Data Receiver
Schematics
Top-level Block
4|Page
VHDL Project
Serial Data Receiver
Simulation
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VHDL Project
Serial Data Receiver
VHDL Code (Method 2)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
entity basic is
Port ( data_in : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (6 downto 0);
err : out STD_LOGIC;
clk : in STD_LOGIC;
data_valid : out STD_LOGIC);
end basic;
architecture Behavioral of basic is
signal counter : integer := 0 ;
signal temp : STD_LOGIC_vector(9 downto 0);
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VHDL Project
Serial Data Receiver
begin
process(clk)
begin
if(clk='1' and clk'event) then
if ( counter=0 and data_in = '1') then
counter <= counter+1;
elsif (counter<11 ) then
temp(counter-1) <= data_in;
counter <=counter+1;
elsif(temp(8)=(temp(7) xor temp(6) xor temp(5) xor temp(4) xor temp(3) xor
temp(2) xor temp(1)) and temp(9)='1') then
data_out <= temp ( 7 downto 1 );
counter <=0 ;
data_valid <='1';
err <='0';
else
counter <=0;
data_valid <='0';
err <='1';
end if;
end if;
end process;
end Behavioral;
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VHDL Project
Serial Data Receiver
Schematic
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VHDL Project
Serial Data Receiver
Simulation
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