NATIONAL UNIVERSITY of SINGAPORE
Department of Electrical and Computer Engineering
EE2005 Electronics
Homework Assignment #7 Solution
(No need to hand in homework assignment)
1. Consider the current mirror shown in Fig. 7-1. The transistors have Kp=100A/V2,
VTHP=-0.5V, p=0.01 and no body effect.
(a) Select R1 such that the output current Iout is 0.2mA.
(b) Find maximum output DC voltage (VD) for all transistors to still operate in saturation
region and the corresponding AC small signal parameters of the transistors.
(c) Find the small-signal AC output resistances (Rout).
(d) Write down the netlist for the schematic in Fig. 7-1.
(e) What is the simulated AC output resistance (Rout)?
(Hints: Treat VD as voltage source that has DC bias of 0V and AC amplitude of 1V. You can
then obtain output resistance by doing ac analysis and find out the small signal vd/i(vd).)
You may assume the following model for the PMOSFET :
.model Psimple_mos PMOS level=1 w=289u l=30u vto=-0.5 tox=100n lambda=0.01
+cgdo=1.73n
10V
10V
M1A
M1
M2A
M2
M3A
VR1
M3
Rout
Iout
R1
VD
Fig. 7-1
(a)
I D , M 1 A = I D , M 2 A = I D , M 3 A = I D ,M 1 = I D , M 2 = I D , M 3 = I out = 0.2mA
I D , M 1 A = K p VGS , M 1 A VTHP
= 0.2mA VGS ,M 1 A = 1.914
VGS , M 1 A = VGS ,M 2 A = VGS , M 3 A = 1.914
I D,M 1A =
V R1 10 VGS , M 1 A VGS , M 2 A VGS , M 3 A
=
= 0.2mA R1 = 21.3k
R1
R1
(b)
In order for all transistors to operate at saturation
V D < 10 VGS , M 1 A VGS , M 2 A VGS , M 3 A + VGS , M 3 VDSSAT ,M 3
V DSSAT , M 3 = VGS , M 3 VTHP = 1.414
V D < 4.76
g m , M 1 A = g m , M 2 A = g m , M 3 A = g m , M 1 = g m , M 2 = g m , M 3 = 4 K p I out = 283A / V 2
ro , M 1 A = ro , M 2 A = ro , M 3 A = ro ,M 1 = ro ,M 2 = ro , M 3 =
(c)
1
= 500k
p I out
Rx1
Rx1
M1A
M2A
M3A
VR1
Rx2
Rx3
M1
Rx2
M2
Rx3
M3
R1
M1
M2
M2
M3
M3
Rout
Iout
Rout
Iout
M1
VD
VD
Ry2
Ry1
Rout
VD
Table 2 Configuration B R y 2 = ro , M 1 = 500k
Table 2 Configuration G R y1 = ro , M 2 (1 + g m , M 2 R y 2 ) = 71.25M
Table 2 Configuration G Rout = ro , M 3 (1 + g m , M 3 R y1 ) = 10G
(d)
*Cascode Current Source
vdd vdd 0 10
M1A A A vdd vdd Psimple_mos
M2A B B A A Psimple_mos
M3A C C B B Psimple_mos
M1 D A vdd vdd Psimple_mos
M2 E B D D Psimple_mos
M3 vd C E E Psimple_mos
R1 C 0 21.3k
Vd vd 0 0 ac 1
.model Psimple_mos PMOS level=1 w=289u l=30u vto=-0.5 tox=100n lambda=0.01 cgdo=1.73n
.ac dec 10 0.1 100
.probe
.end
(e)
Simulated Rout=11.562G.
2. Consider the CS amplifier shown in Fig. 7-2.
and no body effect.
The transistors have K=100A/V2, VTH=0.5V
(a)
Design R1 and RB such that M1 has drain current (ID,M1) of 500A and the amplifier has
an input resistance (Rin) greater than 100k.
(b) Identify the source, load and the two-ports network. Estimate the two-ports equivalent
parameters, Rin, Rout, Gm.
(c) Estimate the overall gain (AV=vo/vs).
(d) Verify your gain through PSPICE simulation.
You may assume the following model for the NMOSFET :
.model Nsimple_mos NPMOS level=1 w=289u l=30u vto=0.5 tox=100n lambda=0.01
+cgdo=1.73n
10V
RD
R1
10k
vo
RB
M
M1A
1
RS
vs
1k
Cin
1
Fig. 7-2
(a)
I D , M 1 A = I D , M 1 = 500 = K (VGS , M 1 A VTH ) VGS , M 1 A = 2.74
2
I D,M 1A =
V DD VGS , M 1 A
R1
= 500 R1 = 14.5k g m , M 1 A = 4 KI D , M 1 A = 447 A / V 2
Rin = RB +
// R1 = R B + 1.9k > 100k
g m,M 1A
Choose RB = 100k
(b)
10k
RB
RL
Rin
RS
1k
vo
M1
M1A
Two-Ports
Network
vs
Load
RD
R1
Rout
Source
g m , M 1 = 4 KI D , M 1 = 447
ro , M 1 =
I D , M 1
= 200k
Amplifier Configuration is CS G m = g m , M 1 = 447
1
Rin = R B +
// R1 = 101.9k
g m,M 1A
Rout = R D // ro , M 1 = 9.5k
(c)
Source
Rin
vi = v s
vs
Rin + RS
vo = Gm vi Rout
= g m , M 1 Rout v s
vi
RS
vs
1k
vo
= g m , M 1 Rout
vs
= 4.25
(d)
vo
Rin
Gmvi
Rout
102k
447vi
9.5k
*CS Amplifier
vdd vdd 0 10
M1A A A 0 0 Nsimple_mos
R1 vdd A 14.5k
RB A B 100k
M1 out B 0 0 Nsimple_mos
RD vdd out 10k
vs vs 0 ac 1
RS vs C 1k
Cin C B 1u
.model Nsimple_mos NMOS level=1 w=289u l=30u vto=0.5 tox=100n lambda=0.01 cgdo=1.73n
.ac dec 10 100 1g
.probe
.end
(e)
Simulated AV=-4.37
3. Analyze the following circuit. Find out all the driving point resistance.
effect.
Neglect body
R6
M2
M3
R5
M1
VB2
Rin
Q4
R4
R3
VB1+vs
R1
RL
I
R7
VB1
Q1 Q2
vout
Q3
R8
R9
R2
Rout
R10
2I
Fig. 7-3
R6
M3
M2
M1
Rin
Q4
RL
R4
R3
R7
Q1 Q2
R1
R8
R9
R2
R10 = r ,Q 4 (1 + g m ,Q 4 RL )
[Table
R8 = r ,Q 3 (1 + g m ,Q 3 R10 ) [Table
vout
Q3
R5
Rout
R10
1 Configuration E ]
1 Configuration E ]
= r ,Q 3 1 + g m ,Q 3 r ,Q 4 (1 + g m ,Q 4 RL )
[Table
R7 = ro ,M 3
R9 =
1
g m ,Q 3
Rout =
R1 =
1
g m ,Q 4
1
g m ,Q1
2 Configuration B ]
ro , M 3
R7
1
=
+
+ 1 g m ,Q 3 + 1
[Table
1 Configuration F ]
ro ,M 3
R9
1
1 1
+
=
+
+ 1 g m,Q 4 + 1 g m,Q 3 + 1
[Table
[Table
1 Configuration F ]
1 Configuration C ]
] [Table
R3 = ro ,Q 2 1 + g m ,Q 2 (r ,Q 2 // R1 )
1 Configuration G ]
1
= ro ,Q 2 1 + g m ,Q 2 r ,Q 2 //
2ro ,Q 2
g m ,Q1
[Q g
m ,Q1
= g m ,Q 2
R5 = ro , M 1 (1 + g m , M 1 R3 ) = ro , M 1 (1 + 2 g m , M 1 ro ,Q 2 ) [Table 2 Configuration G ]
R6 =
R4 =
R2 =
1
g m,M 2
1
g m,M 1
// R5
ro , M 1 +
1
g m,M 2
[Table
2 Configuration D ]
1
g m,M 2
ro , M 1
ro ,Q1 + R4
g m ,Q 2
ro ,Q1
1
g m,M 1
1
g m ,Q 2
[Table
2 Configuration H ]
[Table 1 Configuration
H]
Rin = r ,Q1 (1 + g m ,Q1 R2 ) 2r ,Q1 [Table 1 Configuration E ]
