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Cadence-Rtl-Compiler-With-Vcd-File: Saturday, July 30, 2016 L&T Infotech Proprietary Page 1 of 2

The document discusses estimating power consumption using an RTL compiler with a VCD file. The user generated a VCD file from a testbench simulation in ModelSim but found that including the VCD file did not change the power numbers reported by the RTL compiler. The user notes that the "Nets asserted" field in the power report is 0, suggesting this may be why including the VCD file had no effect.

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RamakrishnaRao Soogoori
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24 views2 pages

Cadence-Rtl-Compiler-With-Vcd-File: Saturday, July 30, 2016 L&T Infotech Proprietary Page 1 of 2

The document discusses estimating power consumption using an RTL compiler with a VCD file. The user generated a VCD file from a testbench simulation in ModelSim but found that including the VCD file did not change the power numbers reported by the RTL compiler. The user notes that the "Nets asserted" field in the power report is 0, suggesting this may be why including the VCD file had no effect.

Uploaded by

RamakrishnaRao Soogoori
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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http://electronics.stackexchange.

com/questions/63698/estimating-power-consumption-incadence-rtl-compiler-with-vcd-file

I need to analyze the power consumption using RTL Compiler based on the VCD file generated
by ModelSim. I have two files:
gcm.v (This is the main circuit. Module name is "gcm")
tb.v (This is the testbench. Module name is "tb", and "gcm" is instantiated as "gcm_tb")
The command to generate vcd file is in tb.v as below:
$dumpfile ("testb. vcd"); $dumpvars (1, testbench.gcm_tb);
Here is my script for RTL compiler:
set_attribute lib_search_path /opt/cadence/local/FreePDK45/osu_soc/lib/files
set_attribute library {gscl45nm.lib}
read_hdl -v2001 tb.v
elaborate
read_vcd -vcd_module gcm_tb -module gcm -static testb.\ vcd
synthesize -to_mapped
write -mapped > gcm_synth.v
report power -tcf_summary > power.txt
exit

RTL compiler gives me the same power numbers with and without the VCD file. Here is my
power summary in power.txt:
============================================================
Generated by:

Encounter(r) RTL Compiler v07.10-p004_1

Generated on:

Mar 28 2013 03:47:17 PM

Module:
Technology library:

ccm
gscl45nm

Saturday, July 30, 2016


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Operating conditions: typical (balanced_tree)


Wireload mode:

enclosed

============================================================

Leakage

Dynamic

Total

Instance Cells Power(nW) Power(nW) Power(nW)


--------------------------------------------------ccm

2963 71474.787 535247.155 606721.942

add_147_11 127 6038.327 11984.664 18022.991


a_aes

0.000 19505.200 19505.200

e_aes

0.000 26450.600 26450.600

------------------------------------------------------Total nets in design


Nets asserted

: 3865 (100.00%)
: 0 (0.00%)

Nets computed

: 3862 (99.92%)

Default nets

: 0 (0.00%)

Clock nets

: 0 (0.00%)

Constant nets

: 3 (0.08%)

Net does not have TCF asserted : 3865 (100.00%)


-------------------------------------------------------

I see the nets asserted is 0. Is this the reason why the power consumption did not change?

Saturday, July 30, 2016


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