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Roll#: ___________________
Name: ___________________
Section:___________________

Due Date: 25th Nov, 2016 (In class)

Question #1:
On a typical microprocessor, a distinct I/O address is used to refer to the I/O data registers and a
distinct address for the control and status registers in an I/O controller for a given device. Such
registers are referred to as ports. In the Intel 8088, two I/O instruction formats are used. In one
format, the 8-bit opcode specifies an I/O operation; this is followed by an 8-bit port address. Other
I/O opcodes imply that the port address is in the 16-bit DX register. How many ports can the 8088
address in each I/O addressing mode?

Question #2:
A similar instruction format is used in the Zilog Z8000 microprocessor family. In this case, there
is a direct port addressing capability, in which a 16-bit port address is part of the instruction, and
an indirect port addressing capability, in which the instruction references one of the 16-bit general
purpose registers, which contains the port address. How many ports can the Z8000 address in each
I/O addressing mode?

Question #3:
The Z8000 also includes a block I/O transfer capability that, unlike DMA, is under the direct
control of the processor. The block transfer instructions specify a port address register (Rp), a
count register (Rc), and a destination register (Rd). Rd contains the main memory address at which
the first byte read from the input port is to be stored. Rc is any of the 16-bit general purpose
registers. How large a data block can be transferred?

Question #4:
Consider a microprocessor that has a block I/O transfer instruction such as that found on the Z8000.
Following its first execution, such an instruction takes five clock cycles to re-execute. However,
if we employ a nonblocking I/O instruction, it takes a total of 20 clock cycles for fetching and
execution. Calculate the increase in speed with the block I/O instruction when transferring blocks
of 128 bytes.

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Question #5:
For programmed I/O, Figure 7.5(Book by William Stallings) indicates that the processor is stuck
in a wait loop doing status checking of an I/O device. To increase efficiency, the I/O software
could be written so that the processor periodically checks the status of the device. If the device is
not ready, the processor can jump to other tasks. After some timed interval, the processor comes
back to check status again.
a. Consider the above scheme for outputting data one character at a time to a printer that
operates at 10 characters per second (cps).What will happen if its status is scanned every
200 ms?
b. Next consider a keyboard with a single character buffer. On average, characters are entered
at a rate of 10 cps. However, the time interval between two consecutive key depressions
can be as short as 60 ms. At what frequency should the keyboard be scanned by the I/O
program?

Question #6:
A microprocessor scans the status of an output I/O device every 20 ms. This is accomplished by
means of a timer alerting the processor every 20 ms. The interface of the device includes two ports:
one for status and one for data output. How long does it take to scan and service the device given
a clocking rate of 8 MHz? Assume for simplicity that all pertinent instruction cycles take 12 clock
cycles.

Question #7:
A particular system is controlled by an operator through commands entered from a keyboard. The
average number of commands entered in an 8-hour interval is 60.
a. Suppose the processor scans the keyboard every 100 ms. How many times will the
keyboard be checked in an 8-hour period?
b. By what fraction would the number of processor visits to the keyboard be reduced if
interrupt-driven I/O were used?

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Question #8:
Consider a system employing interrupt-driven I/O for a particular device that transfers data at an
average of 8 KB/s on a continuous basis.
a. Assume that interrupt processing takes about 100 s (i.e., the time to jump to the interrupt
service routine (ISR), execute it, and return to the main program). Determine what fraction
of processor time is consumed by this I/O device if it interrupts for every Byte.
b. Now assume that the device has two 16-byte buffers and interrupts the processor when one
of the buffers is full. Naturally, interrupt processing takes longer, because the ISR must
transfer 16 bytes. While executing the ISR, the processor takes about 8 s for the transfer of
each byte. Determine what fraction of processor time is consumed by this I/O device in
this case.
c. Now assume that the processor is equipped with a block transfer I/O instruction such as
that found on the Z8000.This permits the associated ISR to transfer each byte of a block in
only 2 s. Determine what fraction of processor time is consumed by this I/O device in this
case.

Question #9:
A DMA module is transferring characters to memory using cycle stealing, from a device
transmitting at 9600 bps. The processor is fetching instructions at the rate of 1 million instructions
per second (1 MIPS). By how much will the processor be slowed down due to the DMA activity?

Question #10:
Consider a system in which bus cycles takes 500 ns. Transfer of bus control in either direction,
from processor to I/O device or vice versa, takes 250 ns. One of the I/O devices has a data transfer
rate of 50 KB/s and employs DMA. Data are transferred one byte at a time.
a. Suppose we employ DMA in a burst mode. That is, the DMA interface gains bus
mastership prior to the start of a block transfer and maintains control of the bus until the
whole block is transferred. For how long would the device tie up the bus when transferring
a block of 128 bytes?
b. Repeat the calculation for cycle-stealing mode.
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Question #11:
Examination of the timing diagram of the 8237A indicates that once a block transfer begins, it
takes three bus clock cycles per DMA cycle. During the DMA cycle, the 8237A transfers one
byte of information between memory and I/O device.
a. Suppose we clock the 8237A at a rate of 5 MHz. How long does it take to transfer one
byte?
b. What would be the maximum attainable data transfer rate?
c. Assume that the memory is not fast enough and we have to insert two wait states per
DMA cycle. What will be the actual data transfer rate?

Question #12:
A 32-bit computer has two selector channels and one multiplexor channel. Each selector channel
supports two magnetic disk and two magnetic tape units. The multiplexor channel has two line
printers, two card readers, and 10 VDT terminals connected to it. Assume the following transfer
rates:
Disk drive -------800 KBytes/s
Magnetic tape drive -------200 KBytes/s
Line printer -------6.6 KBytes/s
Card reader -------1.2 KBytes/s
VDT -------1 KBytes/s
Estimate the maximum aggregate I/O transfer rate in this system.

Question #13:
Assume that one 16-bit and two 8-bit microprocessors are to be interfaced to a system bus. The
following details are given:
1. All microprocessors have the hardware features necessary for any type of data transfer:
programmed I/O, interrupt-driven I/O, and DMA.
2. All microprocessors have a 16-bit address bus.
3. Two memory boards, each of 64 KBytes capacity, are interfaced with the bus. The designer
wishes to use a shared memory that is as large as possible.

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4. The system bus supports a maximum of four interrupt lines and one DMA line. Make any
other assumptions necessary, and
a. Give the system bus specifications in terms of number and types of lines.
b. Describe a possible protocol for communicating on the bus (i.e., read-write, interrupt, and
DMA sequences).
c. Explain how the aforementioned devices are interfaced to the system bus.
References:
Chapter 7
Computer Organization and Assembly language By William Stallings, 8th Edition

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