IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO.

9, SEPTEMBER 2012 1715

Testing Methodology of Embedded DRAMs

Hao-Yu Yang, Chi-Min Chang, Mango C.-T. Chao, Rei-Fu Huang, and Shih-Chin Lin

AbstractThe embedded-DRAM (eDRAM) testing mixes up the SoC testing due to the difficulty of test isolation and test
techniques used for DRAM testing and SRAM testing since an accessibility [8]. By reducing the tester requirement and en-
eDRAM core combines DRAM cells with an SRAM interface (the abling the parallel testing of different memory cores, memory
so-called 1T-SRAM architecture). In this paper, we first present
our test algorithm for eDRAM testing. A theoretical analysis to the built-in-self-test (BIST) circuit is the best solution to the em-
leakage mechanisms of a switch transistor is also provided, based bedded memory testing in common consensus today [9][11].
on that we can test the eDRAM at a higher temperature to reduce Several BIST schemes are proposed for the embedded DRAM
the total test time and maintain the same retention-fault coverage. testing [12][15]. However, these previous works mainly
Finally, we propose a mathematical model to estimate the defect focus on the architecture and the automatic generation of the
level caused by wear-out defects under the use of error-correc-
tion-code circuitry, which is a special function used in eDRAMs BIST circuitry. Few discussions on the test algorithms and the
compared to commodity DRAMs. The experimental results are col- test-time overhead resulted from the retention test can be found
lected based on 1-lot wafers with an 16 Mb eDRAM core. in the literature for the eDRAM testing.
Index TermsEmbedded-DRAM (eDRAM), fault model, reten- The conventional DRAM testing contains two main tasks:
tion, error-correction-code. the retention testing and the functional testing. In the reten-
tion testing, we test whether the data retention time of each
DRAM cell can meet its specification. In the functional testing,
I. INTRODUCTION we test whether the DRAM-cell array and its peripheral cir-
cuits can function correctly at different operating modes, which

D UE to the advantages of high density, structure simplicity,

low-power consumption, and low cost, DRAM has been
the mainstream of the commodity-memory market since its
combine different cycle latencies with different clock frequen-
cies for special applications, such as the burst mode and page
read/write. To cover various fault models for the DRAM array,
invention by Dr. Dennard [1]. With the continually growing several test algorithms, such as checkerboard, address comple-
need to an effective and economic embedded-memory core in ment, March, row/column disturb, self-refresh, XMOVI, and
the SoC era, researchers attempt to carry DRAMs advantages butterfly, need to be applied. Applying all the above algorithms
from a commodity memory into a SoC. In the past decade, at different operating modes is time-consuming, and hence, in
a lot research effort has been put into the embedded-DRAM reality, most DRAM companies prize their DRAM chips dif-
(eDRAM) technologies, such as deep-trench capacitor with ferently according to the length of the applied test. With this
bottle etch [2], planar capacitor [3], [4], shallow trench capac- price model, DRAM companies need to analyze their process
itor [4], and metal-insulator-metal (MIM) capacitor [3], [5], as well as their memory design to rank the fault models by their
to reduce the process adders to the CMOS process, where the possibility of occurrence. Then, the test engineers can choose a
eDRAM is embedded in. The eDRAM technologies are now proper combination of test algorithms to cover the high-ranked
available in the IC-foundry industry [6], [7] and its applications faults as much as possible when the length of the applied test is
include the products of networking, multimedia handheld de- limited.
vices, gaming consoles, high definition television, and so forth. In fact, testing eDRAMs is quite different from testing
Unlike integrating a bare DRAM die within a system-in- commodity DRAMs due to the following reasons. First of all,
package or a packaged DRAM on a system board, where most eDRAM macros use the SRAM interface (the so-called
the responsibility of testing the commodity DRAM itself is 1T-SRAM architecture), which consists of no address multi-
on the memory design company, the responsibility of testing plexer (no CAS, RAS) and can auto-refresh. Second, unlike
the eDRAM is transferred to the system integrator. Testing commodity DRAM, whose application might be unknown
large embedded-memory cores has been a big challenge for before the fabrication, eDRAM macros are more applica-
tion-specific and hence have only one operating mode, meaning
Manuscript received October 22, 2010; revised February 27, 2011; accepted that one cycle latency at only one operating frequency needs
June 13, 2011. Date of publication August 12, 2011; date of current version July to be tested. Due to the use of a simple SRAM interface
05, 2012.
in eDRAMs, testing eDRAMs is more like testing SRAMs
H.-Y. Yang, C.-M. Chang, and M. C.-T. Chao are with the Department of
Electronics Engineering and Institute of Electronics, National Chiao Tung and requires a shorter test algorithm than testing commodity
University, Hsinchu 300, Taiwan (e-mail: max0327.eecs94@nctu.edu.tw; DRAMs. However, testing eDRAM is not as simple as testing
cmc.ee95g@nctu.edu.tw; mango@faculty.nctu.edu.tw).
SRAMs since some fault models which may not occur in
R.-F. Huang is with the MediaTek Inc., Hsinchu 300, Taiwan (e-mail:
rf.huang@mediatek.com). SRAMs, such as retention faults and coupling faults, may
S.-C. Lin is with the United Microelectronics Corporation, Hsinchu 300, occur in eDRAM. Third, the process of eDRAMs is different
Taiwan (e-mail: shih_chin_lin@umc.com).
from that of commodity DRAMs, meaning that their storage
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. capacitors, bit lines, word lines, transistors models, number
Digital Object Identifier 10.1109/TVLSI.2011.2161785 of metal layers, and wire models are all different. As a result,

1063-8210/$26.00 2011 IEEE

1716 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2012

Fig. 1. Relation between and associated with different temperatures

[17].

the possibility of a faults occurrence for eDRAMs is different

from that for commodity DRAMs as well.
Similar to commodity DRAMs, eDRAMs require a retention
test as well. The specification of eDRAMs data-retention time Fig. 2. Embedded-DRAM architecture.

is a constant and usually in the order of milliseconds. As a result,

the ratio of this retention test time over the eDRAM test time in-
creases when the clock frequency of the eDRAM increases. It and then develop an efficient mathematical model to estimate
implies that the retention-test time may dominate the eDRAM the defect level resulting from the wear-out defects based on
test time for high-performance eDRAM designs. The data-re- the use of ECC, which is a special function used in eDRAMs
tention time of an eDRAM cell depends on the leakage cur- compared to commodity DRAMs.
rent of the switch transistor in the cell, which is sensitive to the The remainder of this paper is organized as follows.
temperature [16], [17]. Fig. 1 shows that a transistors leakage Section II first introduces the embedded DRAM architecture
current increases dramatically with the increase of temperature in use. Section III presents a reduced, effective test algorithm
[17]. Therefore, by properly increasing the test temperature, the for eDRAMs. Section IV discusses the leakage mechanism
retention test time can be significantly reduced. of a switch transistor and analyzes the retention-test time at
Furthermore, unlike commodity DRAM utilizing spare rows different temperatures. Section V discusses the defect level
and columns for repair, most eDRAM macros utilize error cor- resulting from the wear-out defects when ECC is used. The
rection code (ECC) circuitry to improve their yield as well as its conclusion is given in Section VI.
reliability since eDRAMs storage capacitor is small and thus
more susceptible to the noise, soft errors, or wear-out defects. II. BACKGROUND
Because some wear-out defects might be masked by the ECC
circuitry, we need to turn off the ECC circuitry and collect the A. Overview of Embedded DRAM
raw defect statistics of the eDRAM macros when applying the Fig. 2 shows the block diagram of a 16 Mb eDRAM macro
reliability testing, such as temperature, humidity, bias (THB) used in our SoC design. This eDRAM macro utilizes deep trench
test [18], highly-accelerated temperature and humidity stress capacitors and is implemented in a UMC 65 nm low-leakage
(HAST) test [19], and high temperature operating life (HTOL) logic process. Fig. 3 shows a cross-section view of an eDRAM
test [20]. Then, how to estimate the defect level based on the cell in our design. The word size on the interface of this eDRAM
collected raw defect statistics becomes an interesting but prac- macro is 32 bits. Due to the use of ECC, we need to add 6-bit
tical problem for eDRAMs. more memory cells to the physical array for each word, and
In this paper, we would like to share our experience in testing hence the physical data stored in the memory array is 38 bits
an UMC 65 nm eDRAM macro. We first discuss the test al- per word. A physical 38-bit word is read out from or written into
gorithms used for the eDRAM testing and compare the corre- the memory array through the ECC circuitry, which encodes a
sponding yields of different test algorithms through silicon re- 32-bit word into a 38-bit word or decodes a 38-bit word to a
sult. We then analyze the test time of eDRAM retention test and 32-bit word. The size of the eDRAM macro is around 4 mm ,
its ratio to total eDRAM test time. Next, we study the leakage which contains two symmetric eDRAM arrays. Each array con-
mechanisms of a switch transistor and theoretically compute tains 128 banks, and each bank contains 64 word-lines and its
the leakage-charge equivalence between different temperatures. own local sense amplifier. Each word-line on each array is con-
Based on this leakage-charge equivalence, we can obtain the nected to 64 half-words, and the data-width of each half-word
equivalent retention time used for retention test at different tem- is 19 bits. Note that the layout topology of the eDRAM array
peratures. We also report the test-time reduction by increasing utilizes the distributed folding scheme, where the th bit of the
testers temperature and validate the equivalent retention-fault th word is adjacent to the th bit of the th word, not the
coverage through silicon result. In addition, we further discuss th bit of the original th word. Between the two eDRAM
how reliability testing can help to identify the wear-out defects arrays is the address decoder including word-line drivers. The
YANG et al.: TESTING METHODOLOGY OF EMBEDDED DRAMS 1717

TABLE I
WRITE-OPERATION SEQUENCE AND CORRESPONDING FUNCTIONAL INPUTS
FOR FILLING THE CHECKERBOARD BACKGROUND IN FIG. 4

Fig. 3. Illustration of an eDRAM cell.

As a result, the physical value of those cells connected to a

bit-line-bar is inverse to their logical value. In addition, the
bit-line twist for a column reverses the physical-value/log-
ical-value relation of the cells below that twist.
During the eDRAM testing, the data background written
into or read from the memory macro should represent cells
physical value instead of its logical value. Therefore, when
Fig. 4. Exemplary array scrambling.
designing the BIST circuitry, we need to build a scramble table
to map the physical value described in the test algorithm to
control circuit (CTL) and global sense amplifier (GSA) are on its corresponding logical value for a given address [21], [22].
the bottom of the eDRAM core. Those logical values then form the functional test patterns or
The CTL controls all operations of eDRAM, including read, expected responses during testing. This scramble table can
write, self-refresh, auto-refresh, and any application-dependent be implemented by a simple two-level logic, whose inputs
operation such as burst-mode read/write or byte read/write. contain few least significant bits and most significant bits of
After precharge and charge redistribution, the data is first dif- an address. In addition, when performing March algorithm,
ferentiated by LSA, then passed to GSA, and read out through the sequence of the activated word-lines also needs to follow
the read/write path. The refresh operation in this eDRAM core the physical sequence, not logical address sequence. Thus, the
can be finished by using the LSA so that refreshing all the BIST requires another physical-address-mapping circuitry to
words on one word-line (64 words in total) requires only one handle this address scrambling. For instance, Fig. 4 shows a
cycle. Therefore, total 64 128 cycles are required for one checkerboard background for cells physical values. To fill
refresh operation. When operating at 100 MHz, the bandwidth such a background with an -direction March algorithm, the
of this eDRAM core is 3.125 Gb/s (32 bits 100 MHz). sequence of write operations and the corresponding functional
In modern memory designs, scrambling techniques are com- inputs are listed in Table I.
monly used to optimize memorys layout geometry, address
decoder, cell area, performance, yield, and I/O pin compatibility B. Difference Between eDRAM and Commodity DRAM
[21]. The types of scrambling include folding, address decoder
scrambling, contact and well sharing, and bit-line twisting. Table II compares the eDRAMs with the commodity
Fig. 4 shows an exemplary scrambling used in our eDRAM DRAMs. First of all, the array structure and the peripheral
design, where the ordering of word-lines in this example is circuits of commodity DRAMs are both simple and hence
arranged according to the least significant bits of the address. a commodity-DRAMs process usually requires two or three
With an SRAM interface, eDRAM utilizes both bit-lines and metal layers. On the other hand, eDRAMs are integrated into
bit-line-bars to distinguish the data value stored in an eDRAM a logic process, which usually uses five or more metal layers.
cell, but a cells data is only connected to either one of the Second, the storage capacitor in commodity DRAMs
corresponding bit-line and bit-line-bar. In this example, each is larger than that of eDRAMs since a commodity-DRAM
word-line connects to two 4-bit words. The first word on a process is developed specifically for DRAM cells. Third, the
word line uses the 0th, 2nd, 4th, and 6th pairs of the bit-line read mechanism of DRAMs is based on the charge sharing
and bit-line-bar, and the second word uses the 1st, 3rd, 5th, between the storage capacitor and the bit-lines capacitor
and 7th pairs. By proper arrangement, half of eDRAM cells . Thus, the length of the bit-line is limited by the ratio
are connected to bit-line, and the other half to the bit-line-bar. of over such that the is small enough to guarantee
1718 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2012

TABLE II timate the defect level caused by the wear-out defects. We will
COMPARISON BETWEEN COMMODITY DRAMS AND EMBEDDED DRAMS discuss this issue later in Section V.

C. Difference Between eDRAM and SRAM

eDRAM design is also called 1T-SRAM because it utilizes
the DRAM cells with SRAM interface. The SRAM interface
for eDRAMs means that the eDRAM designs can auto refresh,
use bit-line pairs (bit-line and bit-line-bar) for sensing, and do
not contain any address multiplex (no CAS, RAS). With this
architecture, the operations of eDRAM macros are much like
that of SRAM than commodity DRAM. However, from testings
point of view, several different aspects exist between eDRAM
a successful read operation through the sense amplifier. In and SRAM.
our eDRAM design, this ratio is set to 15 . Since the of 1) Retention Fault: SRAM stores the data by using
commodity DRAMs is larger than that of eDRAMs, the bit-line cross-coupled inverters but eDRAM stores the data in capac-
in commodity DRAMs is also longer, meaning more bit cells itors, which can be leaked out over time due to the leakage
per bit-line for commodity DRAMs. Also, the refresh period current of the pass transistor. To prevent this data loss caused
for commodity DRAMs is longer since a larger can tolerate by leakage, eDRAM needs to refresh its own data after a certain
more leakage. In addition, the word-line, which is implemented period of time, while SRAM does not require this refresh
by polysilicon, is longer in eDRAMs because the extra metal mechanism. Testing the functionality of eDRAMs refresh
layers in the logic process can be used to reduce word-lines mechanism is called the retention test, which is a time-con-
resistance by connecting the word-line in parallel. suming process for eDRAM testing and is usually not included
From testings point of view, the eDRAM testing is simpler in conventional SRAM testing.
than the commodity-DRAM testing. First, the data size of Note that SRAM may also suffer a data-retention problem if
eDRAM is smaller, and hence requires shorter test application an open defect occurs at the source/drain of a pull-up transistor,
time. Second, commodity DRAMs have multiple operating which is also referred as the stability fault [25]. If the resistance
modes, i.e., several difference latency cycles mix with several of the open defect is large enough, the data stored in the de-
clock frequencies. All operating modes need to be tested for fective cell may be flipped after a certain period of time [26],
commodity DRAMs. On the other hand, eDRAMs uses SRAM [27]. If the resistance of the open defect is small, the defective
interface which contains no address multiplexors and only one cell may still pass the regular operations even with a long pause
operating mode. Also, commodity DRAMs need to test their but may fail under certain adverse conditions afterward, such
IO pads and package pins, such as the ESD testing and the as serious IR drop, increased coupling noise, elevated tempera-
DC testing (open, short, static current, etc.), whereas eDRAMs ture, soft errors, or NBTI, which can be a potential source of a
need not. products defect level [25], [28].
Even though testing a single eDRAM macro is much faster The data-retention fault in SRAM is different from the
than testing a commodity DRAM, the test application time for eDRAM retention fault mentioned in this subsection due to
an eDRAM macro is still a big concern when testing the whole the following reasons. First, the data stored in an eDRAM
SoC chip. A lot SoC designs using eDRAM macros are actu- cell is supposed to leak and should be recovered by its refresh
ally simple applications and do not contain too many IP cores. mechanism after a pre-defined period. Thus, testing data reten-
Based on our experience, if all the conventional DRAM test al- tion in eDRAM is subject to the pre-defined period between
gorithms are applied to an eDRAM macro, its testing application two refreshes, while testing data retention in SRAM is not
time may take much longer than testing SoCs logic circuits and related to any pre-defined time. Second, testing data retention
dominates the total testing time of the SoC testing. Therefore, a in eDRAM also examines the correctness of its refresh mech-
minimal eDRAM testing algorithm is still highly demanded in anism, which is a function not included in SRAM. Third, the
industry, especially for the eDRAM providers. pause used in SRAM testing can only detect the stability fault
Another important difference between eDRAMs and com- with a large defective resistance. Several techniques, such as
modity DRAMs is that eDRAM macros usually use an ECC severe write [25], [27], read equivalent stress [26], [29], or
circuitry to repair the defects and tolerate soft error whereas low-V-write/high-V-read [30], were proposed in the past to
commodity DRAMs use spare rows or/and columns to repair detect the stability fault with a small defective resistance. As a
the defects. It is because the cost of using spare rows/columns result, using long pause (retention test) in SRAM testing is not
to repair defective cells is lower than that of using ECC and the as effective as the above techniques and hence is not mandatory
commodity DRAMs capacitor is large enough to tolerate noise item in todays SRAM testing. On the other hand, retention test
and soft errors. However, eDRAMs storage capacitor is small is a mandatory item in eDRAM testing.
and hence an eDRAM macro requires an ECC circuitry to en- 2) Coupling-Capacitance Fault: SRAM usually uses the
hance its reliability. The use of ECC in eDRAM further induces power/ground shielding skills to prevent the noise induced by
an interesting issue when we apply the reliability testing to es- large coupling capacitance. However, eDRAM seldom uses the
YANG et al.: TESTING METHODOLOGY OF EMBEDDED DRAMS 1719

III. EDRAM TEST APPROACH

A. Current SRAM Test Approach

In this section, we use the March C- algorithm as the basic
skeleton of our eDRAM-testing algorithm. March C- algorithm
is currently the most widely used test algorithm for SRAM in in-
dustry, which can detect stuck-at faults (SAFs), transition faults
(TFs), address decoder faults (AFs), inversion coupling faults
(CFins), idempotent coupling faults (CFids), and state coupling
faults (CFst) [1]. The following shows the element sequence of
the March C- algorithm. The complexity of the March C- algo-
rithm is 10 , where is the density of the array.

March C- (10N):

Fig. 5. Behavior of a transistor open fault on the pass transistor during a read
operation for: (a) SRAM and (b) eDRAM.
The notations are defined as follows.

address direction do not care;

address increase;
power/ground shielding skills because the eDRAM is usually
designed to be dense. Therefore, eDRAM is more sensitive address decrease;
to the coupling noise, such as word-line coupling and bit-line data background;
toggling, than SRAM. Consequently, for eDRAM testing, we
need to focus more on the faults induced by coupling noise complement data background;
than that for SRAM testing. read;
3) Stuck-Open Fault: A major difference between SRAM
write.
and eDRAM in sensing is that the bit-line pair of most
SRAM designs is precharged to Vdd for read operations
B. e-DRAM Test Strategies
while the bit-line pair of eDRAM is precharged to Vdd/2. The
precharged-to-Vdd mechanism in SRAMs read operations is Even though the interface of our eDRAM is the same as that
used to prevent the data stored in the cross-coupled inverters of SRAM, applying only the SRAM test algorithm for eDRAM
from being attacked by the floating bit-lines, since the pass testing is not sufficient. Therefore, on top of this March C-
transistors in SRAM are all n-type MOSFETs and difficult algorithm, we need to add more elements to cover the faults
to pull up the stored 0 value with a floating-1 bit-line. The which may not be considered in current SRAM testing but
precharged-to-Vdd/2 mechanism in eDRAMs read operations should be considered in the eDRAM testing, such as data-reten-
is used to help its differential sensing, since only one-end of tion faults, word-line coupling faults, bit-line toggling faults,
eDRAMs bit-line pair is connected to the capacitor and per- and stuck-open faults. We also need to test the functionality
which eDRAM has but SRAM does not, such as auto-refresh
form charge-sharing at the bit-line. Precharging the bit-lines to
and self-refresh. In the following subsections, we provide the
Vdd or Gnd will limit the differential sensing in one direction
corresponding test strategy for each of the above uncovered
for eDRAM.
faults and functions in the March C- algorithm.
Due to the difference of their precharge mechanisms, the im-
1) Auto-Refresh and Self-Refresh: Auto-fresh and self-re-
pact of the stuck-open fault occurring on a pass transistor is dif-
fresh are two functionalities which eDRAM has but SRAM does
ferent for SRAM and eDRAM as well. Fig. 5 illustrates this dif- not. When the auto-refresh is activated, all eDRAM cells are re-
ference. When the stuck-open fault occurs on the pass transistor, freshed after every period of retention-time specification. When
it will introduce a floating node (WLx) at the gate of the pass the self-refresh is activated, all eDRAM cells are refreshed and
transistor. The voltage of WLx will depend on the intrinsic cou- the retention-time counter for auto-refresh is reset. Therefore, in
pling capacitor between the pass transistors gate and the bit-line the eDRAM testing, the auto-refresh must be always on since
(BL). If BL is precharged to Vdd like SRAM, the voltage of the beginning and a self-refresh operation must be performed
WLx will be raised to roughly the middle of Vdd and hence the right before a ra element and a rb element individually to
pass gate will be half turn-on as shown in Fig. 5(a). If BL is check the correctness of refreshing both 0 and 1.
precharged to Vdd/2 like eDRAM, the voltage of WLx will not 2) Retention Faults: The retention faults are caused by the
be raised too much (more close to Gnd) and hence the pass gate cells which can not hold their charge for the specification-de-
can be reviewed as turn-off as shown in Fig. 5(b). As a result, fined retention time. To test retention faults, we need to perform
the behavior of a transistor open fault is completely different a self-refresh followed by a delay element, which will delay the
between SRAM and eDRAM. next operation for the specification-defined retention time. At
1720 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2012

the same time that the self-refresh is performed, the counter of and storage capacitor, or storage capacitor and ground is large.
the auto-refresh is reset. So after the delay element ends, the In this case, the data is hard to write into or read out from
data will be auto-refreshed again. Then a read operation is per- cells. Modern SRAM designs do not have this problem but some
formed to check if any retention fault occurs during the delay el- eDRAM cores do. SOFs can be detected at the same time as
ement. During this retention test, the checkerboard background SAFs are detected when the sense amplifier is transparent to
should be applied because this background can exacerbate the stuck-open faults. It means that the second element in March
leakage and help to catch a retention fault. Note that the checker- C- algorithm, (ra, wb), can already detect the SOFs in this case.
board background here refers to datas physical values, not log- When the sense amplifier is latch-based and thus not transparent
ical values. Also, we need to perform this retention test to both to stuck-open faults due to the presence of the data latch, the test
the data-background and its complement. algorithm requires an element of (read, write, read) to detect the
3) Word-Line-Coupling Faults: In modern SRAM designs, SOFs [1]. Therefore, we change the second element in March
the power/ground shielding technique is used to eliminate the C- algorithm from (ra, wb) to (ra, wb, rb), which becomes the
signal disturbance between word-lines or bit-lines, and hence extended March C- algorithm.
we seldom consider the word-line-coupling faults in SRAM
testing. However, for eDRAM design, such technique cannot C. Proposed Embedded-DRAM Test Approach
be applied due to its high-density requirement. In addition, the
capacitive loading of a word-line in eDRAM is relatively large In this section, we summarize the test strategies discussed
because more words are connected to a word-line in eDRAM in Section III-B to form the final test approach for an eDRAM
than in SRAM. Word-lines are made of polysilicon that has core. This test approach applies an -direction extended March
much higher resistance than metal line. When a word-line is C- algorithm with solid data-background as well as a -di-
turned off too slowly due to its large RC delay, the voltage of rection MATS algorithm with checkerboard data-background.
the neighboring word-line might couple capacitively a voltage Also, we test the self-refresh operation in the extended March C-
to the original word-line, resulting in a wrong state on the orig- algorithm and the retention faults in the MATS algorithm. The
inal word-line. In this case, a wrong data would be read from auto-refresh is always on in both algorithms. The detail steps of
or write into the cells if a cells data on the original word-line the March C- and MATS algorithms are described as follows.
is different from that of its adjacent word-line, such a scenario
is easier to happen and test by the checkerboard background. -direction Extended March C- with solid background:
Therefore, to detect word-line-coupling faults, a -direction EMC-:
MATS algorithm with a checkerboard background may be uti- ;
lized. The sequence of a MATS algorithm is shown as follows.
Its complexity is 4N. (SR); .

MATS (4N): -direction MATS with checkerboard background:

MATS: .

Note that the -direction sequence refers to the physical

word-line sequence, not the logical address sequence. For SR self-refresh;
example in Fig. 4, the physical word-line sequence is WL 0,
2, 1, 3, 4, 6, 5, 7, not WL 0, 1, 2, 3, 4, 5, 6, 7. This address del delay element which stops for the period of the retention
scrambling in -direction needs to be considered in the BIST time defined in the specification.
circuitry. The test time (in terms of cycles) of the above EMC- and
4) Bit-Line-Toggling Faults: Testing SRAM needs not con- MATS algorithms are listed in (1) and (2)
sider the bit-line toggling because of its power/ground shielding
mechanism. A bit-line-toggling fault occurs when the bit-line
(1)
or bit-line-bar of a cell is close to the bit-line or bit-line-bar
of its adjacent cell, and these two adjacent lines have oppo-
(2)
site data values. Because of higher density, one cells bit-line or
bit-line-bar is closer to its adjacent cells bit-line or bit-line-bar
than that in SRAM, eDRAM has higher probably of bit-line where
toggling fault. In order to create this scenario for each pair of
adjacent cells, we need to perform the solid data-background total number of words;
because of the array scrambling as shown in Fig. 4. There- retention time;
fore, the testing algorithm for eDRAM testing needs to cover
test frequency.
bit-line-toggling faults, meaning that the proposed algorithm
have to apply the solid data-background. Note that, in the above equations, the number of cycles spent
5) Stuck-Open Faults (SOFs): SOF occurs when the resis- on self-refresh is since the 64 words at the same word-
tance between bit-line and switch transistor, switch transistor line will be refreshed at the same time. Also, the number of
YANG et al.: TESTING METHODOLOGY OF EMBEDDED DRAMS 1721

cycles spent on one delay element is the specified retention time TABLE III
times the frequency . YIELD OF DIFFERENT TEST APPROACHES
The above -direction extended March C- algorithm covers
the stuck-open faults by the element (ra, wb, rb). It also tests the
functionality of self-refresh and auto-refresh. The above -di-
rection MATS algorithm tests the word-line-coupling faults by TABLE IV
TEST ALGORITHM OF A1, A2, AND A3
the -direction elements and checkerboard data-background. It
also tests the retention faults by inserting the sequence of SR and
del twice. The bit-line-toggling faults are covered by the solid-
background operations in the extended March C- algorithm.
From coverages point of view, the two self-refresh opera-
tions in the extended March C- algorithm seem redundant since
two self-refresh operations are also performed in the MATS al- TABLE V
gorithm for the retention test. However, we keep the first two IMPACT OF USING DIFFERENT MARCH ELEMENTS AND TRAVERSING
DIRECTIONS FOR THE FIRST PART OF OUR PROPOSED TEST APPROACH
self-refresh operations in our first tape-out to differentiate the
detection of self-retention faults from that of the data-retention
faults. These two self-refresh operations in the extended March
C- algorithm can be further removed to speed up the test time if
the diagnosis requirement is low. March algorithm generated by a commercial tool, March C
(14N), is redundant in our eDRAM testing.

D. Experimental Results With ECC-On E. Experimental Results With ECC-Off

In this subsection, we would like to share some internal exper-
In this subsection, we will perform different test approaches
imental results which helped us to design the march elements,
to the same eDRAM cores with the ECC circuitry turning on
traversing direction, and data background used in our proposed
and without the retention tests, then compare the yield of each
test approach during the development stage. Those experiments
test approach. The test patterns are applied through external
are conducted by applying several similar march algorithms to
testers, not BIST circuitry. The reported results are collected
the same eDRAM macros and comparing their resulting yields.
from 1-lot wafers for this experiment. Following are the three
Note that all the experiments in this section are performed with
test approaches to be applied individually:
the ECC circuitry turning off, such that the impact of the de-
1) the proposed test approach;
tected defects will not be masked by the ECC circuitry and the
2) -direction March C- with solid background plus -di-
yield difference between those test approaches can be more sig-
rection MATS with CHK background;
nificant. Also, all the experiments in this subsection are con-
3) -direction March C+ with solid background plus -di-
ducted based on a different lot of wafers as used in Section III-D.
rection MATS with CHK background.
Besides, all reported yields are represented as the difference to
The detail of March C+ (14N) is as follows:
a base yield due to the confidential issue.
Table IV lists the march elements, data background, and
traversing direction of three 4N march algorithms, denoted as
A1, A2, and A3. As Table IV shows, A1 is the -direction
MATS algorithm with checkerboard background, which is ac-
The difference between proposed approach and the others is tually the same algorithm used in the first part of our proposed
on their March algorithms in use. Approach 2 uses the basic test approach in Section III-C. Similar to A1, A2 is also a
March algorithm described in Section III-A and approach 3 MATS algorithm with checkerboard background but traverses
uses the default March algorithm generated by a commercial in the -direction. A3 is another 4N algorithm, performing a
memory-BIST tool, Memory BIST Architecture [23]. Note that read operation right after a write operation and traverses twice.
we turn off the retention test in this experiment to save its test Table V shows the relative yield after applying each of A1,
time. The experimental results containing the retention test will A2, and A3 with the same extended March C- (EMC-) algo-
be discussed later in the Section IV. rithm of the second part of our proposed approach (as shown in
Table III lists the yield of the above three test approaches. Section III-C). Note that the retention test is turned off in this
Our proposed approach and Approach 3 result in the same yield experiment as well. In Table V, we can first find that A1 plus
while the Approach 2 results in a higher yield. This result im- EMC- can result in a lower yield and capture more detects than
plies that only applying March C- may miss certain faults and A2 plus EMC-, which demonstrates the effectiveness and ne-
lead to higher test escape. The proposed approach can achieve cessity of using a -direction MATS algorithm rather than an
the same level of fault coverage with Approach 3. However, the -direction one in our proposed test approach. Compared to
proposed approach only requires a 11N extended March C- al- an -direction MATS algorithm, the additional faults detected
gorithm but Approach 3 requires a 14N March C algorithm. by a -direction MATS algorithm are the word-line coupling
This result shows that the general SRAM algorithm, March C- faults (as discussed in Section III-B3), which is the source of
(10N), cannot provide sufficient fault coverage, and the default the 6.2% yield difference between A1 and A2. Next, we can
1722 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2012

TABLE VI TABLE IX
TEST ALGORITHM OF B1 AND B2 IMPACT OF APPLYING RETENTION TEST AND BYTE-WRITE TEST

TABLE X
TEST TIME DISTRIBUTION OF THE PROPOSED TEST APPROACH
TABLE VII
IMPACT OF USING DIFFERENT BACKGROUND FOR THE
SECOND PART OF OUR PROPOSED TEST APPROACH

ality of byte-write. Hence the byte-write test can be omitted

based on the application.
TABLE VIII
TEST ALGORITHM OF C1, C2, AND C3
F. Test Time Analysis for Proposed Test Approach
The total test time of the proposed test approach is the
summation of the test time on retention test , read/write
operations , self-refresh , and auto-refresh

(3)
also find in Table V that A2 plus EMC- can capture more de- where
fects than A3 plus EMC-, which further demonstrates the ad-
vantage of using a MATS algorithm rather than another simple (4)
4N march algorithm. (5)
Table VI lists the march elements, data background, and
(6)
traversing direction of two EMC- algorithms, denoted as B1
and B2. As Table VI shows, B1 uses a solid background while (7)
B2 uses a checkerboard background. Both B1 and B2 traverse
in -directional. Table VII reports the yield after applying each time of one (del) element;
of B1 and B2 with the -direction, checkerboard-background
cycle time;
MATS algorithm (A2) but without the retention test. The result
shows that B1 can detect 0.7% more defective parts than B2. number of words;
This result demonstrates the advantage of using a solid-back- number of reads and writes;
ground EMC- algorithm rather than checkerboard-background
one in our proposed test approach. The additional faults de- number of word-lines;
tected by the solid background are bit-line-toggling faults (as number of self-refreshes;
discussed in Section III-B3). Compared to the result shown in
number of total auto-refreshes.
Table V, we can also find that the occurrence of bit-line-toggling
faults is less frequent than the occurrence of word-line-coupling is equal to the retention-time specification, and is
faults for this eDRAM macro. equal to the runtime divide by the specified retention time.
In the following experiment, we attempt to observe the impact Table X lists the test time spent in each component of the
of applying the retention test and the byte-write test. Table VIII proposed approach, given a 50 MHz clock frequency and a 16
lists description of three different MATS algorithms, denoted ms retention-time specification. In this case, the ratio of reten-
as C1, C2, and C3. C1 is the -direction checkerboard-back- tion-test time to total test time is 17.4%.
ground MATS algorithm and does not include the retention test We only assert auto-refresh signal when the run time of an
(same as A2). C2 is C1 plus retention test. C3 is C1 with all its element is longer than retention time. If the test clock is fast
write operations performed by byte-write, i.e., writing a byte (8) enough, the auto-refresh can be removed because elements are
of bit-cells at a time instead of a word (32). Table IX shows the quickly done within retention time, but we still need one AR to
relative yield after applying each of C1, C2, and C3 with the verify the correctness of auto-refresh operation. The refresh can
same extended March C- (EMC-) algorithm used for Table V. be done using a clock rate faster than test clock rate, here we
As Table V shows, adding the retention test can detect 5.6% still use the test clock rate to calculate refresh time.
more defective parts, which demonstrates the effectiveness and In current eDRAM designs, the target clock frequency can
necessity of applying the retention test in eDRAM testing. As to be higher than the 50 MHz used in Table X. Table XI shows the
the byte-write test, only 0.2% more defective parts are detected, ratio of the retention-test time to total eDRAM-test time for dif-
but its test application time is much larger since only 8 bits are ferent clock frequencies and different retention-time specifica-
written at one write operation. In addition, the application of the tions. As the results show, the ratio of the retention-test time in-
manufactured eDRAM macro is usually known when designing creases when the clock frequency increases, and gradually dom-
the SoC, and not all eDRAMs applications need the function- inates the total eDRAM-test time. If the retention time is defined
YANG et al.: TESTING METHODOLOGY OF EMBEDDED DRAMS 1723

TABLE XI
RATIO OF RETENTION-TEST TIME TO TOTAL TEST TIME W.R.T.
EACH RETENTION-TIME SPECIFICATION AND CLOCK RATE

longer in the specification, this ratio would be even higher. For Fig. 6. Main leakage sources of a eDRAM cell.
the case that clock frequency is 200 MHz and the defined re-
tention time is 32 ms, this retention-test-time ratio can be up to
62.9%. Therefore, reducing the retention-test time can signifi- A. Leakage Mechanisms
cantly reduce the total eDRAM-test time. In Section IV, we will The leakage mechanisms of a deep-sub-micron transistor
attempt to increase the temperature to further reduce the reten- include reverse-bias pn junction leakage, subthreshold leakage,
tion-test time. oxide tunneling current, gate current due to hot-carrier injection,
Another way to further reduce the total test time is to apply the gate-induced drain leakage (GIDL), and channel punchthrough
burst mode operation, if the eDRAM core supports, for a single- current [17]. Among these six leakage mechanisms, the re-
operation March element, such as the (wa) and (ra) in the verse-bias junction band-to-band-tunneling (BTBT) leakage,
extended March C- algorithm. However, this reduction is still subthreshold leakage, and direct tunneling current are the
limited since most elements contain more than one operations. main leakage sources in current advanced process technologies
[16]. Fig. 6 illustrates these three main leakage sources in
the cross-section view of a cell in our eDRAM. The detail
IV. REDUCING RETENTION-TEST TIME BY analysis for each of the above leakage sources and its relation
INCREASING TEMPERATURE to temperature are presented as follows.
For an eDRAM cell, its data-retention time is determined by 1) Reverse-Bias Junction BTBT Leakage: Drain and source
the leakage of its switch transistor, which increases along with to well junctions are commonly reverse-biased for preventing
the increase of the temperature. In the eDRAM testing, we at- forward-biased current. If both and region are heavily
tempt to raise the temperature to increase transistors leakage doped, band-to-band tunneling dominates the junction
current, which shortens the data-retention time of a cell. There- leakage. The BTBT current involves the emission or absorption
fore, at a higher temperature, the delay element used for reten- of phonons, since silicon is an indirect band gap semiconductor.
tion test can be specified shorter since a retention fault can be The tunneling current density is as follows [24]:
detected within a shorter period of time than that at the original
reference temperature. However, if the new specified retention (8)
time is too low, some retention faults may be able to escape, re-
sulting in a higher defect level. On the contrary, if it is too high,
where , and
the retention time of an eDRAM cell is over-tested, resulting in
is the effective mass of electron; is the energy-band gap;
a yield lost.
is the applied reverse bias; is the electric field at the
In order to specify an appropriate retention time for the delay
junction; is the electronic charge; and is the reduced Plancks
element at a higher temperature, we need to calculate the time at
constant. The electric field at the junction is
a given temperature during that the leakage of a switch transistor
is equivalent to the leakage during the specified retention time
at the reference temperature, which is defined as 85 C in our (9)
specification. This time is defined as the equivalent retention
time for a given temperature, which implies that a eDRAM cell where and are the doping in the and side, respec-
loses its data after the specified retention time at 85 C if and tively; is permittivity of silicon; is the built in voltage
only if this cell will lose its data after the equivalent retention across the junction.
time at the given temperature. 2) Subthreshold Leakage: Subthreshold leakage occurs
In the following of this section, we first study different when gate voltage is below . In the weak inversion, the
leakage mechanisms of a switch transistor and their sensitivity diffusion current occurs in the subthreshold conduction when
to the temperature. Based on this leakage analysis, we then the minority carriers are conducted from channel region and
calculate the equivalent retention time. Last, the experimental exist in channel depletion layer. This subthreshold current can
results of using different equivalent retention time at different be expressed as follows [24]:
temperatures are presented. We will also compare the total
test-time reduction by increasing the temperature. (10)
1724 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2012

where 4) Thermal Voltage : The thermal voltage is linearly pro-

portional to the temperature, which results in an exponential
(11) growth of the subthreshold leakage.
5) Threshold Voltage : The increase of temperature
where is the threshold voltage; is the thermal causes more carriers on the channel, which reduces the threshold
voltage, is temperature; is the gate-oxide capacitance; voltage and hence increases the subthreshold leakage.
is the zero-bias mobility; is the subthreshold swing coefficient 6) Barrier Height : The barrier height decreases when
(also called body effect coefficient); is the maximum de- temperature increases, which is proportional to .
pletion-layer width; is the gate-oxide thickness. In summary, the direct-tunneling current is invariant to the
3) Gate Tunneling Current: The high electric field coupled temperature since the barrier height and potential drop across
with low oxide thickness causes tunneling of electrons both oxide are invariant to the temperature. The BTBT leakage may
from substrate to gate and from gate to substrate, resulting in the vary with the temperature but only in a small order. The sub-
gate-oxide-tunneling current. The direct tunneling mechanism threshold leakage increases significantly along with the increase
occurs in more advanced devices because the potential drop of the temperature due to the decrease of and the increase
across the oxide is smaller than the barrier height of Si-SiO . of thermal voltage. Even though the direct-tunneling current and
The current density of direct tunneling can be expressed as fol- BTBT current are not sensitive to the temperature, both of them
lows [24]: should still be considered in our leakage analysis since they con-
tribute a significant portion of the total leakage at the normal
temperature especially in advanced process technologies [16].
(12) C. Analysis of Equivalent Retention Time
To calculate the equivalent retention time for a target tem-
perature, we first calculate the total amount of charge
where and leaked from the storage capacitor during the retention-time
is the electric field across the oxide. specification at the reference temperature , i.e.,
When a DRAM cell stores 1, its bias condition is illustrated 85 C. Then the leakage during the equivalent retention time
in Fig. 6. and induce a subshreshold cur- at the target temperature has to be equivalent to
rent. means that drain-substrate is reverse-biased, , which is expressed in (14)
which induces BTBT leakage. In addition, the direct tunneling
current also may occur because the voltage across the intersec- (14)
tion of drain and gate is equal to . Hence, the total leakage
current of the switch transistor for a given temperature Therefore, the equivalent retention time at the target
can be expressed as temperature can be obtained by (15)

(13) (15)

where and is the tunneling area of direct tunneling The parameters used in the leakage calculation are listed as
and BTBT. follows, which are provided by the IC foundry and may vary
Note that this leakage is actually a function of temperature. from the following different process technologies.
The following subsection discusses those temperature-depen- Mobility : (m /V s).
dent parameters in the above leakage equations. In addition, the Oxide Capacitance : (F/m ).
leakage for the storage capacitor itself is small when using a Oxide Thickness : (m).
high- material and hence can be omitted in our analysis. Channel Width : (m).
Channel Length : (m).
B. Temperature-Dependent Parameters in Leakage
Subthreshold Swing : 1.11.5.
Different leakage-current sources have different temperature Thermal Voltage : (V).
dependence. In the following, we list the temperature-depen- Threshold Voltage : 0.40.6 (V).
dent parameters in above three leakage equations and discuss Supply Voltage : 1.2 (V).
the magnitude of their dependency to the temperature . Barrier Height : 3.13.2 (eV).
1) Energy-Band Gap : The energy-band gap may be Energy Band-gap :
narrowed by the increase of temperature within an order of (eV).
. Doping Concentration: about (m ).
2) Junction Electric Field : The junction electric field Table XII lists the calculated equivalent retention time and
coupled with the doping concentration may be influenced by the its reduction ratio to the original specification-defined retention
temperature, but it is more dependent on the junction voltage. time associated with each given temperature. The retention-time
3) Mobility : The increase of temperature results in the specification is 16 ms at the reference temperature
reduction of mobility. The degradation of mobility is direct pro- 85 C. As the results shows, the retention-time reduction is close
portional to . to 50% when raising the temperature to 105 C, and 65% when
YANG et al.: TESTING METHODOLOGY OF EMBEDDED DRAMS 1725

TABLE XII TABLE XIV

CALCULATED EQUIVALENT RETENTION TIME AND ITS REDUCTION TO THE TEST TIME REDUCTION W.R.T. EACH RETENTION-TIME SPECIFICATION,
RETENTION-TIME SPECIFICATION 16 MS AT 85 C CLOCK RATE, AND TEMPERATURE

TABLE XIII
YIELD W.R.T. EACH TEMPERATURE AND RETENTION-TIME SPECIFICATION

120 C, respectively. It implies that the retention-test time can

be significantly reduced by raising the temperature.

D. Experimental Results
In the following experiment, we apply our proposed test algo-
rithm (described in Section III) on the eDRAM cores of 1-lot test
wafers repeatedly with different retention-time specifications
at different temperatures. In each time of the eDRAM testing, retention time, retention-test time, and total eDRAM-test time,
the delay element needs to match the retention-time specifica- respectively, associated with each retention-time specification
tion. Table XIII shows the corresponding yield for each reten- at 85 C, clock frequency, and temperature. Column 7 list the
tion-time specification and temperature. As the results show, the total eDRAM-test-time reduction achieved by using the equiva-
yield reaches 86.5% with 16 ms retention time at 85 C. Also, lent retention time at each temperature compared to the total test
the same yield is first-reached with 12 ms retention time at 95 time at 85 C. As the results show, this total eDRAM-test-time
C and 8 ms retention time at 105 C. This result implies that reduction increases when the temperature, clock frequency, or
the eDRAM cells which hold their charge for 16 ms at 85 C retention-time specification increases. The reduction ratio can
can hold their charge for 12 ms at 95 C and for 8 ms at 105 C, be up to 38.2% by increasing 30 C at temperature when the
respectively. This result approximately matches the calculated retention-time specification and clock frequency are 32 ms and
equivalent retention time listed in Table XII, where the equiva- 200 MHz, respectively.
lent retention time for 95 C and 105 C is 11.55 and 8.49 ms, Note that at a higher temperature, its equivalent retention time
respectively. decreases, which results in more frequent auto-refresh opera-
Note that we are not suggesting to directly use the calculated tions. Fortunately, the time consumed by a refresh operation is
equivalent retention time during the eDRAM testing. The equiv- short and does not affect test-time reduction too much. In ad-
alent retention time used in practice should be verified through dition, the temperature discussed here is for wafer testing. If
real silicon experiments. For the IC foundry providing eDRAM we want to test the data retention after package, the tempera-
cores, a table of equivalent retention time associated with dif- ture under consideration should be the temperature inside the
ferent temperatures can be built through a similar experiment package, not just testers temperature. The temperature inside
as shown in Table XIII. However, it may take weeks or even the package is higher than that outside the package. The table to
longer to build a complete yield table with respect to each tem- map packages outside temperatures to its insides temperature
perature and each retention-time specification. The cost of re- can be obtained from the package providers.
peatedly testing the same wafers should be considered. This cost Also, increasing the temperature at test may fail more dies
limitation is also the reason why the resolution of the retention than that at the normal temperature since the dies are literally
time in Table XIII is in 2 ms, not in a smaller, more accurate unit tested under a condition similar to a burn-in test, which may
of time. Therefore, our theoretical calculation of the equivalent also be a test item requested from the customers to detect the
retention time can be used as an efficient guideline during the infant-mortality dies and further reduce the defect level. There-
above process of searching the equivalent retention time with fore, increasing the temperature at test can cover two needs at
silicon experiments, which can save the high cost of repeatedly the same time, one for reducing the retention test time and the
testing a significant number of test wafers. other for improving the defect level. Besides, to elevate the
Table XIV further shows the total eDRAM-test-time reduc- ovens temperature to the desired level may take extra time,
tion which can be achieved by increasing the testing temper- which is another overhead of increasing temperature at test. For-
ature. In Table XIV, Columns 4, 5, and 6 list the equivalent tunately, as long as the temperature is increased to the desired
1726 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2012

level, we can keep on sending the wafers into the oven and apply
test continually. Thus, the overhead of increasing the ovens
temperature is a one-time overhead, whose impact can be fur-
ther reduced if the volume of the order is large.
Fig. 7. Relations among , and
.
V. DEFECT-LEVEL ESTIMATION OF WEAR-OUT DEFECTS
UNDER ECC
level under ECC, we also need to obtain the probability distri-
Reliability testing, such as THB test [18], HAST test [19], and
bution of the number of single defects existing before applying
HTOL test [20], is applied to measure the reliability or lifetime
the production testing, which is a Poisson distribution as well
of manufactured chips by operating them under an extreme con-
and can be collected from the production testing.
dition of certain environmental or electrical parameters. Those
Before introducing our mathematical model of estimating this
extreme conditions can accelerate the wear-out failure mech-
defect level with the use of ECC, we first define the following
anisms, such as electron migration, dielectric breakdown, hot
notations:
carrier effects, and mobile ionic contamination. Hence we could
: the number of bits per word;
use the result of the above reliability testings to foresee the
: the number of words in one memory chip;
products failure rate occurring after certain months or years of
: the number of bits in one memory chip ;
usage. This failure caused by the wear-out defects is one source
: the random variable denoting the number of single
of products defect level.
defects existing before applying the production testing;
In current industry, the cost of the above reliability testings is
: the mean of the random variable ;
still expense. Also, the application time of a reliability testing
: the random variable denoting the number of added
may take several days or sometimes even weeks (such as THB
single defects during the reliability testing;
test). As a result, unlike the production burn-in testing, which is
: the mean of the random variable ;
applied to each part to accelerate the infant-mortality failures,
: the probability that event occurs;
a reliability testing can only be applied to a small portion of
: the event that a part containing random single
the products to accelerate the wear-out failures. Thus, in this
defects passes the production testing with the use of ECC;
section, we provide a mathematical model to estimate the defect
: the event that a part containing random single
level of a eDRAM macro resulting from the wear-out defects
defects passes the reliability testing with the use of ECC;
based on limited samples. Also, this model considers the use
DL: the defect level caused by the wear-out defects.
of ECC circuitry, which is seldom used in commodity DRAMs,
The defect level caused by the wear-out defects is equal to
especially MCM DRAM KGDs.
, where
The most straightforward method to estimate this defect
represents the probability that a part passes the reliability
level is just to run the reliability testing with the ECC function
testing in condition that the part passes the production testing.
and count the failed parts at the end. However, the number of
Fig. 7 illustrates the relations among
sampled parts for the reliability testing is usually around few
, and .
hundreds and the general acceptable defect level is under 100
Once the part passes the reliability testing, it must be able to
DPPM. This sampling size is not enough to support such a fine
pass the production testing. Hence, we can calculate the defect
resolution of the defect level. For example, in our own THB or
level, DL, by the following equation:
HTOL test of an eDRAM product, we sample total 231 parts
(77 parts per lot for three consecutive lots) and our target defect
level is 32 DPPM. Therefore, instead of counting the failed
parts, we directly count the number of defective eDRAM cells
for each part before and after the reliability testing. Because
the ECC circuitry may mask the effect of some defective cells, (16)
we need to turn off the ECC function and directly read the data
from cells, which requires a bypass mode of the ECC circuitry When applying the production testing, the number of defects
to realize this action. As described above, we can obtain the in a part is . To pass the production test, there cannot exist
probability distribution of the number of the added defective two defects in a word given the . Thus, the
cells on a part during the reliability testing. is equal to
Those defective cells resulting from the wear-out defects are
actually random single defects, and thus the above probability
distribution can be modeled by the Poisson distribution. The re-
sult of our internal experiment also confirms this Poisson distri-
bution. The most important parameter for a Poisson distribution (17)
is its , which represents the mean of the Poisson distribution.
Based on few hundreds of sampled parts, the sampled mean of where represents the possible combinations that the
the number of added defective cells after the reliability testing defects locate in different words and represents the total
is more reliable than the sampled DPPM. To estimate the defect possible combinations that defects locate in the memory array.
YANG et al.: TESTING METHODOLOGY OF EMBEDDED DRAMS 1727

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[28] A. Ney, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, M. Bas- Mango C.-T. Chao received the B.S. and M.S.
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2009, pp. 13441348. Hsinchu, Taiwan, in 1998 and 2000, respectively,
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266271. He is an Assistant Professor with the Department
[30] Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, Efficient testing of of Electronics Engineering, National Chiao Tung
SRAM with optimized march sequences and a novel DFT technique for University. His current research interests include
emerging failures due to process variations, IEEE Trans. Very Large VLSI testing, TFT circuitry design, and physical
Scale Integr. Syst., vol. 13, no. 11, pp. 12861295, Nov. 2005. design automation.

Hao-Yu Yang received the B.S. degree from the Rei-Fu Huang received the B.S. and Ph.D. degrees
Electrical Engineering and Computer Science Un- from the Department of Electrical Engineering,
dergraduate Honors Program at National Chiao Tung National Tsing Hua University, Hsinchu, Taiwan. He
University, Hsinchu, Taiwan, in 2009. He is currently is a technical Manager with MediaTek Inc., Hsinchu
pursuing the Ph.D. degree in electronics engineering City, Taiwan. His research interests include memory
from the Institute of Electronics, National Chiao intellectual property design and testing.
Tung University, Hsinchu, Taiwan.
His current research interest is memory testing.

Chi-Min Chang received the B.S. degree from the Shih-Chin Lin received the B.S. and M.S. degrees
Department of Electrical Engineering, National Cen- from the Department of Electrical Engineering, Na-
tral University, Taoyuan, Taiwan, in 2006, and the tional Chiao Tung University, Hsinchu, Taiwan.
M.S. degree from the Department of Electronics En- He is a director with UMC IP Design Division,
gineering, National Chiao Tung University, Hsinchu, Hsinchu City, Taiwan. His research interests include
Taiwan, in 2008. memory intellectual property design and testing.
He is with Taiwan Semiconductor Manufacturing
Company, where he focused on test structure de-
signing and WAT testing.