Ch

Chapter 1
Introduction to Memories

Jin-Fu Li
Advanced Reliable Systems (ARES) Lab.
Dept. of Electrical Engineering
N ti
National l Central
C t lU University
i it
Jhongli, Taiwan
 Outline

• Importance of Embedded Memories

• Overview of Memory Structures

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 Embedded Memory – The Key to SOC
• Embedded memory is becoming more central to
integrated circuit design
• Historically, ICs were dominated by the logic
f
functions,
ti with
ith memory being
b i external
t l
• Today,
y an SOC contains many
y memory
y blocks of
different sizes, shapes and functionality
− Typically, embedded memories represent about
30%~50% SOC area
• The Semiconductor Industry Association (SIA)
predicts that 90% of the SOC’s surface will be
memory y in 2011
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 Embedded Memory – The Key to SOC
z SOC memory continues to increase
Memory Area Reused Logic Area New Logic Area

20%

52%
16% 71%
83%
90% 94%

16%
64%

13%
32% 9%
6% 4%
16% 8% 4% 2%
99 02 05* 08* 11* 14*
*Foreast Source: SIA, ITRS, 2000
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 Embedded Memory – Advantages
• Area
− Embedding multiple memories on a single SOC reduces
the
h amount off silicon
ili used
d
• Performance
− Embedding faster, wider memories and moving them
closer to processor can increase system performance
substantiallyy
• Power
− Embedded memories eliminate the need to drive off
off-chip
chip
capacitance between the stand-alone memories and other
system chips
• Design reuse
− By reusing embedded memories, system designers can
significantly reduce develop time and cost
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 Embedded Memory – Quality
• During manufacture
− Yield
− Exponential yield model
− Y = e− , where A and D denote the area and
AD

defect density, respectively

• After manufacture
− Reliability

• During
D i use
− Soft error rate

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 Quality During Manufacture
• Issues of embedded memory
− As the density of transistors is increased,
increased the D is
increased compared to logic
− About 2X logic for high density 6
6-T
T SRAM
• Solutions
− Redundancy
R d d & laser
l repair
i using
i ATE
− Error correction code (ECC)

• Redundancy & repair

− Achieve y
yield p
parity
y with logic,
g , or better
− About 3% area overhead
− Recommended over 1Mb

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 Quality During Manufacture

− Corrects <5 defects per Mb

− Laser repair manufacturing flow

• ECC
− Detect/repair defects in individual words
− 25-30% area overhead
∗ Ex:
E 6 extra bits
bi ffor single
i l bit
bi correction
i ini 32 bi
bit words
d
− Latency penalty
∗ At least one clock cycle
y latency
yppenalty
y

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 Quality-Insurance Strategies for Memories
.Large Capture Memory Conventional test and repair approaches
Memory Tester .Redundancy analysis
1
1. Long testing time
.Swap the defective
Laser Repair cells 2. Expensive memory tester and
logic tester are needed
.Test
Test the repaired
Memory Tester memories

Logic
g Tester .Test the remaining
non-memory components
.Test Built-In Self-Test (BIST)

BIST & BISR approaches .Diagnostics Built-In Self-Diagnosis (BISD)

1. Short testing time
2. Only cheap logic tester Built-In Redundancy Analyzer
.Redundancy allocation
(BIRA)
is needed

.Swap the defective cells Redundancy Reconfiguration

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 Introduction to Memories
• Overview of semiconductor memory types
Semiconductor Memories

Read/Write Memory or
Random Access Memory (RAM) Read Only Memory (ROM)

Random Access Non-Random Access

Memory (RAM) Memory (RAM) •Mask (Fuse) ROM
•Programmable ROM (PROM)
•Erasable PROM (EPROM)
•Static RAM (SRAM) •FIFO/LIFO •Electrically EPROM (EEPROM)
D
•Dynamic i RAM (DRAM) Shift Register
•Shift R i t •Flash Memory
•Register File •Content Addressable •Ferroelectric RAM (FRAM)
Memory (CAM) •Magnetic RAM (MRAM)

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 Memory Elements – Memory Architecture
• Volatile memories may be divided into the following
categories
− Random
R d access memory
− Serial access memory
− Content addressable memory
• Memory architecture
2m+k bits
row decoder
row decoder
2n-k words
row decoder
d d
row decoder

column decoder
k
n-bit address column mux,
m-bit data I/Os sense amp
amp,
write buffers
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 1-D Memory Architecture
S0 S0
Word0 Word0
S1 S1
Word1 Word1
S2 S2
Word2 Word2
A0
S3 S3

Decoder
A1

Ak-1

Sn-2 Storage Sn-2

Wordn-2 element Wordn-2
Sn-1 Snn-11
Wordn-1 Wordn-1

m bit
m-bit m-bit
m bit
Input/Output Input/Output

n select signals: S0-Sn-1 n select signals are reduced

to k address signals:
g A0-Akk-11

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 2-D Memory Architecture
S0
Word0 Wordi-1
S1

A0

ecoder
A1
Row De

Ak-1

Sn-1
Wordni-1

A0
Aj-1 Column Decoder

Sense Amplifier
Read/Write Circuit

m-bit Input/Output
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 3-D Memory Architecture
Row
Column
ock
Blo

Input/Output

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 Conceptual 2-D Memory Organization

Address der
ow Decod
M
Memory Cell
C ll
Ro

Column decoder
D t I/Os
Data I/O

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 Memory Elements – RAM
Generic RAM circuit
Bit line conditioning Clocks

RAM Cell

n-1:k

Sense Amp
Amp, Column Write
k-1:0 Mux, Write Buffers Clocks

Address write data read data

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 Memory Elements – RAM Cells
6-T SRAM cell
word line

bit - bit
4-T SRAM cell

word line

bit - bit

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 Memory Elements – RAM Cells
1-T DRAM cell

word line word line

bit bit

Layout of 1-T DRAM (right) word line

Vdd

bit

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 Memory Elements – DRAM Retention
Time
Write and hold operations in a DRAM cell

WL=1 WL=0

on + off +
+ Cs Vs Cs Vs
Input Vdd - -
-

Write Operation Hold

V s = V max = V DD − V tnt
Q max = C s (V DD − V tn )

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 Memory Elements – DRAM Retention
Time
Charge leakage in a DRAM Cell
Vs(t)
WL 0
WL=0
Vmax
IL Minimum logic 1
V1 voltage
off +
Cs Vs(t)
-
t
th

dQ s
IL = −( )
dt
dV s
IL = −C s ( )
dt
ΔVs
IL ≈ −C s ( )
Δt
Cs
t h = | Δ t |≈ ( )Δ Vs
IL
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 Memory Elements – DRAM Refresh
Operation
As an example, if IL=1nA, Cs=50fF, and the difference of Vs is 1V, the
hold time is
50 × 10 −15
t h= −9
× 1 = 0 .5 μ s
1 × 10
Memory units must be able to hold data so long as the power is
applied. To overcome the charge leakage problem, DRAM arrays
employ a refresh operation where the data is periodically read from
every cell
cell, amplified
amplified, and rewritten
rewritten.

The refresh cycle must be performed on every cell in the array with a
minimum
i i refresh
f h ffrequency off about
b t

1
f refresh ≈
2t h

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 Memory Elements – DRAM Read
Operation
WL=1

IL
on +
Cbit Cs Vs Vf
+ -
Vbit Vf
-

Q s = C sV s

Q s = C sV f + C bit V f
Cs
Vf = ( )V s
C s + C bit

This shows that Vf<Vs for a store logic 1. In practice, Vf is usually

reduced to a few tenths of a volt, so that the design of the sense
p
amplifier becomes a critical factor

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 Memory Elements – RAM Read Operation

precharge
precharge
p g

bit, -bit

word line
word

data

- bit bit

data

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Memory Elements – RAM Write Operation

N5 N6
write data
word

write
N3 N4

word

bit -bit
bit, bit
- bit bit
N1 N2
write
cell -cell
cell, cell
write data

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 Memory Elements – Row Decoder

word<3> word<0>

word<2> word<1>

word<1> word<2>

word<0> word<3>

a<1> a<0> a<1> a<0>

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 Memory Elements – Row Decoder
Predecode circuit
word<7>

word<6>
d 6

word<5>

word<4>

word<3>

word<2>

word<1>

word<0>

a2 a1 a0
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 Memory Elements – Row Decoder
Actual implementation
a0

a4
a3
a2 word
a1

-a0 clk

Pseudo-nMOS example

a0 word
od

a1 a2 en

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 Memory Elements – Column Decoder
bit<7>
bit<6>
bit 5
bit<5>
bit<4>
selected-data
bit<3>
bit<2>
bit 2
bit<1>
bit<0>

to sense amps and write ckts

-bit<7>
-bit<6>
-bit<5>
bit<5>
-bit<4>
-selected-data
-bit<3>
-bit<2>
bit 2
-bit<1>
-bit<0>

a0 -a0 a1 -a1 a2 -a2

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 Memory Elements – Multi-Ported RAM

write
read0
read1

-rbit1 -rbit0 -rwr_data rwr_data rbit0 rbit1

write
read0
read1
-rbit1 -rwr_data rwr_data rbit0

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 Memory Elements – ROM
A 4x 4-bit NOR-based ROM array

R1 R2 R3 R4 C1 C2 C3 C4
R1 0 1 0 1
1 0 0 0
0 1 0 0 0 0 1 1
R2
0 0 1 0 1 0 0 1
R3 0 0 0 1 0 1 1 0

R4

C1 C2 C3 C4
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 Memory Elements – ROM
A 4x 4-bit NAND-based ROM array

C1 C2 C3 C4

R1 R1 R2 R3 R4 C1 C2 C3 C4

0 1 1 1 0 1 0 1
R2
1 0 1 1 0 0 1 1
R3
1 1 0 1 1 0 0 1
1 1 1 0 0 1 1 0
R4

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 Memory Elements – ROM
Typical ROM architecture

2N word lines

NOR Row NOR

D
Decoder
d ROM Array

1 2 3 N
Address bits 2M columns

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