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TPS40303, TPS40304, TPS40305

SLUS964B NOVEMBER 2009 REVISED MAY 2015

TPS4030x 3-V to 20-V Input Synchronous Buck Controller

1 Features 3 Description

1 Input Voltage Range From 3 V to 20 V The TPS4030x is a family of cost-optimized

synchronous buck controllers that operate from 3-V to
300-kHz (TPS40303), 600-kHz (TPS40304), and 20-V input. The controller implements a voltage-mode
1.2-MHz (TPS40305) Switching Frequencies control architecture with input-voltage feed-forward
High- and Low-Side FET RDS(on) Current Sensing compensation that responds instantly to a change in
Programmable Thermally Compensated OCP input voltage. The switching frequency is fixed at 300
Levels kHz, 600 kHz, or 1.2 MHz.
Programmable Soft-Start The Frequency Spread Spectrum (FSS) feature adds
600-mV, 1% Reference Voltage to the switching frequency, significantly reducing the
peak EMI noise and making it much easier to comply
Voltage Feed-Forward Compensation with EMI standards.
Supports Prebiased Output
The TPS4030x offers design with a variety of user-
Frequency Spread Spectrum programmable functions, including soft-start,
Thermal Shutdown Protection at 145C overcurrent protection (OCP) levels, and loop
10-Pin 3-mm 3-mm SON Package With Ground compensation.
Connection to Thermal Pad OCP level may be programmed by a single external
resistor connected from the LDRV pin to circuit
2 Applications ground. During initial power on, the TPS4030x enters
a calibration cycle, measures the voltage at the LDRV
POL Modules
pin, and sets an internal OCP voltage level. During
Printers operation, the programmed OCP voltage level is
Digital TVs compared to the voltage drop across the low-side
Telecom FET when it is on to determine whether there is an
overcurrent condition. The TPS4030x then enters a
shutdown and restart cycle until the fault is removed.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS40303
TPS40304 VSON (10) 3.00 mm 3.00 mm
TPS40305
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Simplified Application Diagram

VOUT
TPS4030x VIN

5 FB BOOT 6

4 COMP HDRV 7
VOUT
3 PGOOD SW 8

2 EN/SS LDRV/OC 9

SD 1 VDD BP 10
VIN GND
PAD

UDG-09158

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS40303, TPS40304, TPS40305
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Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 12
2 Applications ........................................................... 1 8 Application and Implementation ........................ 13
3 Description ............................................................. 1 8.1 Application Information............................................ 13
4 Revision History..................................................... 2 8.2 Typical Applications ................................................ 13
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 27
6 Specifications......................................................... 4 10 Layout................................................................... 28
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 28
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 29
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 30
6.4 Thermal Information .................................................. 4 11.1 Device Support...................................................... 30
6.5 Dissipation Ratings ................................................... 4 11.2 Documentation Support ........................................ 30
6.6 Electrical Characteristics........................................... 5 11.3 Related Links ........................................................ 30
6.7 Typical Characteristics .............................................. 7 11.4 Community Resources.......................................... 30
7 Detailed Description .............................................. 9 11.5 Trademarks ........................................................... 30
7.1 Overview ................................................................... 9 11.6 Electrostatic Discharge Caution ............................ 31
7.2 Functional Block Diagram ......................................... 9 11.7 Glossary ................................................................ 31
7.3 Feature Description................................................... 9 12 Mechanical, Packaging, and Orderable
Information ........................................................... 31

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (August 2012) to Revision B Page

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Original (November 2009) to Revision A Page

Changed minimum controllable pulse width max value from 100 to 70 ................................................................................. 5

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5 Pin Configuration and Functions

DRC Package
10-Pins VSON
Top View
FB COMP PGOOD EN/SS VDD

5 4 3 2 1

Thermal Pad

6 7 8 9 10

BOOT HDRV SW LDRV/ BP

OC

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Gate drive voltage for the high-side N-channel MOSFET. A 0.1-F capacitor (typical) must be connected
BOOT 6 I between this pin and SW. For low input voltage operation, an external schottky diode from BP to BOOT is
recommended to maximize the gate drive voltage for the high-side.
Output bypass for the internal regulator. Connect a low ESR bypass ceramic capacitor of 1 F or greater from
BP 10 O
this pin to GND.
COMP 4 O Output of the error amplifier and connection node for loop feedback components.
Logic level input which starts or stops the controller via an external user command. Letting this pin float turns
the controller on. Pulling this pin low disables the controller. This is also the soft-start programming pin. A
capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an
internal current source of 10 A. The resulting voltage ramp of this pin is also used as a second non-inverting
EN/SS 2 I
input to the error amplifier after a 0.8 V (typical) level shift downwards. Output regulation is controlled by the
internal level shifted voltage ramp until that voltage reaches the internal reference voltage of 600 mV the
voltage ramp of this pin reaches 1.4 V (typical). Optionally, a 267-k resistor from this pin to BP enables the
FSS feature.
Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal
FB 5 I
reference voltage.
PGOOD 3 O Open-drain power good output.
HDRV 7 O Bootstrapped gate drive output for the high-side N-channel MOSFET.
Gate drive output for the low-side synchronous rectifier N-channel MOSFET. A resistor from this pin to GND
LDRV/OC 9 O is also used to determine the voltage level for OCP. An internal current source of 10 A flows through the
resistor during initial calibration and that sets up the voltage trip point used for OCP.
Power input to the controller. Bypass VDD to GND with a low ESR ceramic capacitor of at least 1.0-F close
VDD 1 I
to the device.
Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high-
SW 8 O
side FET driver.
Ground connection to the controller. This is also the thermal pad used to conduct heat from the device. This
Thermal connection serves a twofold purpose. The first is to provide an electrical ground connection for the device.
GND
Pad The second is to provide a low thermal impedance path from the device die to the PCB. This pad should be
tied externally to a ground plane.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VDD 0.3 22 V
SW 3 27 V
SW (< 100 ns pulse width, 10 J) 5 V
BOOT 0.3 30 V
HDRV 5 30 V
BOOT-SW, HDRV-SW (differential from BOOT or HDRV to SW) 0.3 7 V
COMP, PGOOD, FB, BP, LDRV, EN/SS 0.3 7 V
TJ Operating junction temperature 40 145 C
Tstg Storage temperature 55 150 C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- 1500 V
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD Input voltage 3 20 V
TJ Operating junction temperature 40 125 C

6.4 Thermal Information

TPS4030x
(1)
THERMAL METRIC DRC (VSON) UNIT
10 PINS
RJA Junction-to-ambient thermal resistance 44.3 C/W
RJC(top) Junction-to-case (top) thermal resistance 56.1 C/W
RJB Junction-to-board thermal resistance 19.2 C/W
JT Junction-to-top characterization parameter 0.7 C/W
JB Junction-to-board characterization parameter 19.4 C/W
RJC(bot) Junction-to-case (bottom) thermal resistance 5.5 C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Dissipation Ratings

RJA HIGH-K BOARD (1) POWER RATING (W) POWER RATING (W)
PACKAGE AIRFLOW (LFM)
(C/W) TA = 25C TA = 85C
0 (Natural Convection) 47.9 2.08 0.835
10-Pin SON (DRC) 200 40.5 2.46 0.987
400 38.2 2.61 1.04

(1) Ratings based on JEDEC High Thermal Conductivity (High K) Board. For more information on the test method, see TI technical brief
(SZZA017).

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6.6 Electrical Characteristics

TJ = 40C to 125C, VVDD = 12 V, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE REFERENCE
TJ = 25C, 3 V < VVDD < 20 V 597 600 603
VFB FB input voltage mV
40C < TJ < 125C, 3 V < VVDD < 20 V 594 600 606
INPUT SUPPLY
VVDD Input supply voltage range 3 20 V
IDDSD Shutdown supply current VEN/SS < 0.2 V 70 100 A
IDDQ Quiescent, nonswitching Let EN/SS float, VFB = 1 V 2.5 3.5 mA
ENABLE/SOFT-START
VIH High-level input voltage, EN/SS 0.55 0.7 1 V
VIL Low-level input voltage, EN/SS 0.27 0.3 0.33 V
ISS Soft-start source current 8 10 12 A
VSS Soft-start voltage level 0.4 0.8 1.3 V
BP REGULATOR
VBP Output voltage IBP = 10 mA 6.2 6.5 6.8 V
Regulator dropout voltage, VVDD
VDO IBP = 25 mA, VVDD = 3 V 70 110 mV
VBP
OSCILLATOR
TPS40303 270 300 330 kHz
fSW PWM frequency TPS40304 3 V < VVDD < 20 V 540 600 660 kHz
TPS40305 1.02 1.20 1.38 MHz
VRAMP (1) Ramp amplitude VVDD/6.6 VVDD/6 VVDD/5.4 V
Frequency spread spectrum
fSWFSS 12% fSW
frequency deviation
fMOD Modulation frequency 25 kHz
PWM
TPS40303 90%
(1)
DMAX Maximum duty cycle TPS40304 VFB = 0 V, 3 V < VVDD < 20 V 90%
TPS40305 85%
(1)
tON(min) Minimum controllable pulse width 70 ns
HDRV off to LDRV on 5 25 35
tDEAD Output driver dead time ns
LDRV off to HDRV on 5 25 30
ERROR AMPLIFIER
(1)
GBWP Gain bandwidth product 10 24 MHz
(1)
AOL Open loop gain 60 dB
Input bias current (current out of FB
IIB VFB = 0.6 V 75 nA
pin)
IEAOP Output source current VFB = 0 V 2
mA
IEAOM Output sink current VFB = 1 V 2
PGOOD
Feedback upper voltage limit for
VOV 655 675 700
PGOOD
Feedback lower voltage limit for mV
VUV 500 525 550
PGOOD
VPGD-HYST PGOOD hysteresis voltage at FB 25 40
RPGD PGOOD pulldown resistance VFB = 0 V, IFB = 5 mA 30 70
550 mV < VFB < 655 mV,
IPGDLK PGOOD leakage current 10 20 A
VPGOOD = 5 V

(1) Ensured by design. Not production tested.

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Electrical Characteristics (continued)

TJ = 40C to 125C, VVDD = 12 V, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT DRIVERS
RHDHI High-side driver pullup resistance VBOOT VSW = 5 V, IHDRV = 100 mA 0.8 1.5 2.5
RHDLO High-side driver pulldown resistance VBOOT VSW = 5 V, IHDRV = 100 mA 0.5 1 2.2
RLDHI Low-side driver pullup resistance ILDRV = -100 mA 0.8 1.5 2.5
RLDLO Low-side driver pulldown resistance ILDRV = 100 mA 0.35 0.6 1.2
(1)
tHRISE High-side driver rise time CLOAD = 5 nF 15 ns
(1)
tHFALL High-side driver fall time 12 ns
(1)
tLRISE Low-side driver rise time 15 ns
(1)
tLFALL Low-side driver fall time 10 ns
OVERCURRENT PROTECTION
Minimum pulse time during short
tPSSC(min) (1) 250 ns
circuit
(1) Switch leading-edge blanking pulse
tBLNKH 150 ns
time
VOCH OC threshold for high-side FET TJ = 25C 360 450 580 mV
IOCSET OCSET current source TJ = 25C 9.5 10 10.5 A
VLD-CLAMP Maximum clamp voltage at LDRV 260 340 400 mV
OC comparator offset voltage for low-
VOCLOS TJ = 25C 8 8 mV
side FET
Programmable OC range for low-side
VOCLPRO (1) TJ = 25C 12 300 mV
FET
OC threshold temperature coefficient
VTHTC (1) 3000 ppm
(both high-side and low-side)
tOFF OC retry cycles on EN/SS pin 4 Cycle
BOOT DIODE
VDFWD Bootstrap diode forward voltage IBOOT = 5 mA 0.8 V
THERMAL SHUTDOWN
TJSD (1) Junction shutdown temperature 145 C
(1)
TJSDH Hysteresis 20 C

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6.7 Typical Characteristics

314 625
VVDD = 20 V
313 620
VVDD = 3V
fSW Switching Frequency kHz

fSW Switching Frequency kHz

312 615

311 610

310 605
VVDD = 12 V

309 VVDD = 12 V 600

VVDD = 3V
308 595

307 VVDD = 20 V 590

306 585
TPS40303 TPS40304
305 580
40 25 10 5 20 35 50 65 80 95 110 125 40 25 10 5 20 35 50 65 80 95 110 125

TJ Junction Temperature C TJ Junction Temperature C

Figure 1. Switching Frequency vs Junction Temperature Figure 2. Switching Frequency vs Junction Temperature
1.4 2.24

1.35 VVDD = 20 V
2.22
fSW Switching Frequency MHz

IDDQ Quiescent Current mA

1.3
2.20
1.25

1.2 2.18
VVDD = 3V
VVDD = 12 V
1.15
2.16

1.1
2.14
1.05
TPS40305 VVDD = 12 V
2.12
1
40 25 10 5 20 35 50 65 80 95 110 125 40 25 10 5 20 35 50 65 80 95 110 125

TJ Junction Temperature C TJ Junction Temperature C

Figure 3. Switching Frequency vs Junction Temperature Figure 4. Quiescent Current vs Junction Temperature
72 14

70 13
IOCSET OCSET Current Source mA
IDD(SD) Shutdown Current mA

12
68

11
66
10
64
9
62
8

60
7
VVDD = 12 V
58
6
40 25 10 5 20 35 50 65 80 95 110 125 40 25 10 5 20 35 50 65 80 95 110 125

TJ Junction Temperature C TJ Junction Temperature C

Figure 5. Shutdown Current vs Junction Temperature Figure 6. OCSET Current Source vs Junction Temperature

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Typical Characteristics (continued)

600.8 740

VIH Enable High-Level Threshold Voltage mV

VFB Feedback Reference Voltage mV

600.6
720

600.4
700

600.2
680

600

660
599.8

640
599.6

620
599.4
40 25 10 5 20 35 50 65 80 95 110 125 40 25 10 5 20 35 50 65 80 95 110 125

TJ Junction Temperature C TJ Junction Temperature C

Figure 7. Feedback Reference Voltage vs Junction Figure 8. Enable High-Level Threshold Voltage vs Junction
Temperature Temperature
303.0 600

VOCH High-Side Overcurrent Threshold mV

VIL Enable Low-Level Threshold Voltage mV

302.5
550

302.0
500

301.5
450

301.0

400
300.5

350
300.0 40 25 10 5 20 35 50 65 80 95 110 125
40 25 10 5 20 35 50 65 80 95 110 125

TJ Junction Temperature C TJ Junction Temperature C

Figure 9. Enable Low-Level Threshold Voltage vs Junction Figure 10. High-Side Overcurrent Threshold vs Junction
Temperature Temperature
800 1000
VOV/VUV Power Good Threshold Voltage mV

975
750 Overvoltage
950
VSS Soft-Start Voltage mV

700
925
650
900

600 875

850
550
825
500
800
450 Undervoltage
775

400 750
40 25 10 5 20 35 50 65 80 95 110 125 40 25 10 5 20 35 50 65 80 95 110 125

TJ Junction Temperature C TJ Junction Temperature C

Figure 11. Power Good Threshold Voltage vs Junction Figure 12. Soft-Start Voltage vs Junction Temperature
Temperature

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7 Detailed Description

7.1 Overview
The TPS4030x is a family of cost-optimized synchronous buck controllers providing high-end features to
construct high-performance DCDC converters. Prebias capability eliminates concerns about damaging sensitive
loads during start-up. Programmable overcurrent protection levels and hiccup overcurrent fault recovery
maximize design flexibility and minimize power dissipation in the event of a prolonged output short. The
Frequency Spread Spectrum (FSS) feature reduces peak EMI noise by spreading the initial energy of each
harmonic along a frequency band, thus giving a wider spectrum with lower amplitudes.

7.2 Functional Block Diagram

+
10mA 0.6 VREF + 12.5%
Soft Start SS
SS FB BP
EN/SS 2 +
SD 0.6 VREF 12.5%
Fault
Clock 6 BOOT
Controller
6-V + OC
HDRV
VDD 1 7
Regulator References 0.6 VREF
SD
BP 10 BP 8 SW

Calibration Spread
COMP 4 Clock Anti-Cross BP
Circuit Spectrum
Conduction
Oscillator PWM
and
Logic 9 LDRV/OC
Prebias
FB 5 Circuit
PWM
+
+
0.6 VREF 10mA
SS Thermal OC
750 kW
Shutdown Threshold
PGOOD 3
Setting

Fault Controller
OC
PAD
UDG-09160
GND

7.3 Feature Description

7.3.1 Voltage Reference
The 600-mV band gap cell is internally connected to the noninverting input of the error amplifier. The reference
voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final
regulation voltage. The 1% tolerance on the reference voltage allows the user to design a very accurate power
supply.

7.3.2 Enable Functionality, Start-Up Sequence and Timing

After input power is applied, an internal current source of 40 A starts to charge up the soft-start capacitor
connected from EN/SS to GND. When the voltage across that capacitor increases to 0.7 V, it enables the internal
BP regulator followed by a calibration. The total calibration time is about 1.9 ms. See Figure 13. During the
calibration, the device performs in the following way. It disables the LDRV drive and injects an internal 10-A
current source to the resistor connected from LDRV to GND. The voltage developed across that resistor is then
sampled and latched internally as the OCP trip level until one cycles the input or toggles the EN/SS.

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Feature Description (continued)

2.0
VEN/SS
Calibration
1.6 Time

VIN Input Voltage V

1.9 ms

1.3 V
1.2

0.8
0.7 V

0.4

VSS_INT
0
t Time ms UDG-09159

Figure 13. Start-Up Sequence and Timing

The voltage at EN/SS is internally clamped to 1.3 V before and/or during calibration to minimize the discharging
time once calibration. The discharging current is from an internal current source of 140 A and it pulls the voltage
down to 0.4 V. The discharging current then initiates the soft-start by charging up the capacitor using an internal
current source of 10 A. The resulting voltage ramp on this pin is used as a second noninverting input to the
error amplifier after an 800 mV (typical) downward level-shift; therefore, actual soft-start does not occur until the
voltage at this pin reaches 800 mV.
If EN/SS is left floating, the controller starts automatically. EN/SS must be pulled down to less than 270 mV to
ensure that the chip is in shutdown mode.

7.3.3 Soft-Start Time

The soft-start time of the TPS4030x is user programmable by selecting a single capacitor. The EN/SS pin
sources 10 A to charge this capacitor. The actual output ramp-up time is the amount of time that it takes for the
10 A to charge the capacitor through a 600-mV range. There is some initial lag due to calibration and an offset
(800 mV) from the actual EN/SS pin voltage to the voltage applied to the error amplifier.
The soft-start is done in a closed-loop fashion, meaning that the error amplifier controls the output voltage at all
times during the soft-start period and the feedback loop is never open as occurs in duty cycle limit soft-start
schemes. The error amplifier has two non-inverting inputs, one connected to the 600-mV reference voltage, and
the other connected to the offset EN/SS pin voltage. The lower of these two voltages is what the error amplifier
controls the FB pin. As the voltage on the EN/SS pin ramps up past approximately 1.4 V (800-mV offset voltage
plus the 600 mV reference voltage), the 600-mV reference voltage becomes the dominant input and the
converter has reached its final regulation voltage.
The capacitor required for a given soft-start ramp time for the output voltage is given by Equation 1.
I
CSS = SS t SS
VFB
where
CSS is the required capacitance on the EN/SS pin. (F)
ISS is the soft-start source current (10 A).
VFB is the feedback reference voltage (0.6 V).
tSS is the desired soft-start ramp time (s). (1)

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Feature Description (continued)

7.3.4 Oscillator and Frequency Spread Spectrum (FSS)
The oscillator frequency is internally fixed. The TPS40303 operating frequency is 300 kHz, the TPS40304
operating frequency is 600 kHz, and the TPS40305 operating frequency is 1.2 MHz.
Connecting a resistor with a value of 267 k 10% from BP to EN/SS enables the FSS feature. When the FSS is
enabled, it spreads the internal oscillator frequency over a minimum 12% window using a 25-kHz modulation
frequency with triangular profile. By modulating the switching frequency, side-bands are created. The emission
power of the fundamental switching frequency and its harmonics is distributed into smaller pieces scattered
around many sideband frequencies. The effect significantly reduces the peak EMI noise and makes it much
easier for the resultant emission spectrum to pass EMI regulations.

7.3.5 Overcurrent Protection

Programmable OCP level at LDRV is from 6 mV to 150 mV at room temperature with 3000 ppm temperature
coefficient to help compensate for changes in the low-side FET channel resistance as temperature increases.
With a scale factor of 2, the actual trip point across the low-side FET is in the range of 12 mV to 300 mV. The
accuracy of the internal current source is 5%. Overall offset voltage, including the offset voltage of the internal
comparator and the amplifier for scale factor of 2, is limited to 8 mV.
Maximum clamp voltage at LDRV is 340 mV to avoid turning on the low-side FET during calibration and in a
prebiased condition. The maximum clamp voltage is fixed and it does not change with temperature. If the voltage
drop across ROCSET reaches the 340-mV maximum clamp voltage during calibration (no ROCSET resistor
included), it disables OC protection. Once disabled, there is no low-side or high-side current sensing.
OCP level at HDRV is fixed at 450 mV with 3000-ppm temperature coefficient to help compensate for changes in
the high-side FET channel resistance as temperature increases. OCP at HDRV provides pulse-by-pulse current
limiting.
OCP sensing at LDRV is a true inductor valley current detection, using sample and hold. Equation 2 can be used
to calculate ROCSET:
I
IOUT(max ) - P-P RDS(on ) - VOCLOS
2
ROCSET =
2 IOCSET



where
IOCSET is the internal current source.
VOCLOS is the overall offset voltage.
IP-P is the peak-to-peak inductor current.
RDS(on) is the drain to source ON-resistance of the low-side FET.
IOUT(max) is the trip point for OCP.
ROCSET is the resistor used for setting the OCP level. (2)
To avoid overcurrent tripping in normal operating load range, calculate ROCSET using the equation above with:
The maximum RDS(ON) at room temperature
The lower limit of VOCLOS (8 mV) and the lower limit of IOCSET (9.5 A) from the Electrical Characteristics
table.
The peak-to-peak inductor current IP-P at minimum input voltage
Overcurrent is sensed across both the low-side FET and the high-side FET. If the voltage drop across either FET
exceeds the OC threshold, a count increments one count. If no OC is detected on either FET, the fault counter
decrements by one count. If three OC pulses are summed, a fault condition is declared which cycles the soft-
start function in a hiccup mode. Hiccup mode consists of four dummy soft-start timeouts followed by a real one if
overcurrent condition is encountered during normal operation, or five dummy soft-start timeouts followed by a
real one if overcurrent condition occurs from the beginning during start. This cycle continues indefinitely until the
fault condition is removed.

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Feature Description (continued)

7.3.6 Drivers
The drivers for the external high-side and low-side MOSFETs can drive a gate-to-source voltage of VBP. The
LDRV driver for the low-side MOSFET switches between BP and GND, while the HDRV driver for the high-side
MOSFET is referenced to SW and switches between BOOT and SW. The drivers have nonoverlapping timing
that is governed by an adaptive delay circuit to minimize body diode conduction in the synchronous rectifier.

7.3.7 Prebias Start-Up

The TPS4030x contains a circuit to prevent current from being pulled from the output during start-up in the
condition the output is prebiased. There are no PWM pulses until the internal soft-start voltage rises above the
error amplifier input (FB pin), if the output is prebiased. Once the soft-start voltage exceeds the error amplifier
input, the controller slowly initiates synchronous rectification by starting the synchronous rectifier with a narrow
on time. The controller then increments that on time on a cycle-by-cycle basis until it coincides with the time
dictated by (1-D), where D is the duty cycle of the converter. This approach prevents the sinking of current from
a prebiased output, and ensures the output voltage start-up and ramp to regulation is smooth and controlled.

7.3.8 Power Good

The TPS4030x provides an indication that output is good for the converter. This is an open-drain signal and pulls
low when any condition exists that would indicate that the output of the supply might be out of regulation. These
conditions include the following:
VFB is more than 12.5% from nominal.
Soft-start is active.
A short-circuit condition has been detected.

NOTE
When there is no power to the device, PGOOD is not able to pull close to GND if an
auxiliary supply is used for the power good indication. In this case, a built-in resistor
connected from drain to gate on the PGOOD pulldown device makes the PGOOD pin look
approximately like a diode to GND.

7.3.9 Thermal Shutdown

If the junction temperature of the device reaches the thermal shutdown limit of 145C, the PWM and the oscillator
are turned off and HDRV and LDRV are driven low. When the junction cools to the required level (125C typical),
the PWM initiates soft-start as during a normal power-up cycle.

7.4 Device Functional Modes

7.4.1 Modes of Operation

7.4.1.1 UVLO
In UVLO, VDD is less than UVLO_ON, the BP6 regulator is off, and the HDRV and LDRV are held low by
internal passive discharge resistors.

7.4.1.2 Disable
Disable is forced by holding SS/EN below 0.4 V. In disable, the BP6 regulator is off, and both HDRV and LDRV
are held low by passive discharge resistors.

7.4.1.3 Calibration
Each enable of the TPS4030X3/4/5 devices requires a calibration which lasts approximately 2 ms. During
calibration the TPS40303/4/5 devices LDRV and HDRV are held off by their respective pulldown drivers while the
device configures as detailed in Enable Functionality, Start-Up Sequence and Timing.

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Device Functional Modes (continued)

7.4.1.4 Converting
When calibration completes, the TPS40303/4/5 devices ramp their reference voltage as described in Soft-Start
Time, and the states of the LDRV and HDRV drivers are dictated by the COMP pin to regulate the FB pin equal
to the internal reference.

8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS4030x is a family of cost-optimized synchronous buck controllers providing high-end features to
construct high-performance DC-DC converters. Prebias capability eliminates concerns about damaging sensitive
loads during start-up. Programmable overcurrent protection levels and hiccup overcurrent fault recovery
maximize design flexibility and minimize power dissipation in the event of a prolonged output short. Frequency
Spread Spectrum (FSS) feature reduces peak EMI noise by spreading the initial energy of each harmonic along
a frequency band, thus giving a wider spectrum with lower amplitudes.

8.2 Typical Applications

8.2.1 Using the TPS40305 for a 12-V to 1.8-V Point-of-Load Synchronous Buck Regulator
Figure 14 shows 12-V to 1.8-V at 10-A synchronous buck application using the TPS40305 switching at 1200 kHz.

Figure 14. TPS40305 Design Example Schematic

8.2.1.1 Design Requirements

For this example, follow the design parameters listed in Table 1.

Table 1. Design Example Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage 8 14 V
VIN(ripple) Input ripple IOUT = 10 A 0.6 V

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Typical Applications (continued)

Table 1. Design Example Electrical Characteristics (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT Output voltage 0 A IOUT 10 A 1.764 1.800 1.836 V
Line regulation 8 V VIN 14 V 0.5%
Load regulation 0 A IOUT 10 A 0.5%
VRIPPLE Output ripple IOUT = 10 A 36 mV
VOVER Output overshoot IOUT falling from 7 A to 3 A 100 mV
VUNDER Output undershoot IOUT rising from 3 A to 7 A 100 mV
IOUT Output current 4.5 V VIN 5.5 V 0 10 A
tSS Soft start time VIN = 12 V 1.5 ms
ISCP Short circuit current trip point 13 15 A
fSW Switching frequency 1200 kHz
Size 1 in2

The bill of materials for this application is shown in Table 2. The efficiency, line, and load regulation from boards
built using this design are shown in Figure 14. Gerber files and additional application information are available
from the factory.

Table 2. Design Example List of Materials

REFERENCE
QTY VALUE DESCRIPTION SIZE PART NUMBER MFR
DESIGNATOR
C1 1 3.3 nF Capacitor, Ceramic, 10 V, X7R, 20% 0603 Std Std
C2 1 820 pF Capacitor, Ceramic, 25 V, X7R, 10% 0603 Std Std
C3 1 150 pF Capacitor, Ceramic, 25 V, X7R, 10% 0603 Std Std
C4 1 3300 pF Capacitor, Ceramic, 25 V, X7R, 10% 0603 Std Std
C5 1 1.0 F Capacitor, Ceramic, 10 V, X7R, 20% 0805 Std Std
C6 1 100 nF Capacitor, Ceramic, 16 V, X7R, 20% 0603 Std Std
C7 1 1 F Capacitor, Ceramic, 25 V, X7R, 20% 0805 Std Std
C8 2 10 f Capacitor, Ceramic, 25 V, X7R, 10% 1210 Std Std
0.328
C11 1 330 F Capacitor, Aluminum, 25 V, 20%, 160 m EEVFK1E331P Panasonic
0.390 inch
C12 2 22 F Capacitor, Ceramic, 6.3 V, X5R, 20% 0805 Std Std
0.268
L1 1 0.32 H Inductor, SMT, 17 A PG0083.401 Pulse
0.268 inch
QFN-8
Q1 1 MOSFET, N-Channel, 25 V, 97 A, 4.6 m CSD16322Q5 TI
POWER
QFN-8
Q2 1 MOSFET, N-Channel, 25 V, 59 A, 9.6 m CSD16410Q5A TI
POWER
R3 1 422 Resistor, Chip, 1/16W, 1% 0603 Std Std
R4 1 10.0 k Resistor, Chip, 1/16W, 1% 0603 Std Std
R5 1 4.99 k Resistor, Chip, 1/16W, 1% 0603 Std Std
R6 1 2.20 k Resistor, Chip, 1/16W, 1% 0603 Std Std
R8 1 100 k Resistor, Chip, 1/16W, 1% 0603 Std Std
R10 1 2 Resistor, Chip, 1/16W, 1% 0603 Std Std
R11 1 3.74 k Resistor, Chip, 1/16W, 1% 0603 Std Std
U1 1 IC, 3-V to 20-V sync. 1.2-MHz Buck controller DRC10 TPS40305DRC TI

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8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Selecting the Switching Frequency

To achieve the small size for this design, the TPS40305, with fSW = 1200 kHz, is selected for minimal external
component size.

8.2.1.2.2 Inductor Selection (L1)

Synchronous buck power inductors are typically sized for approximately 30% peak-to-peak ripple current (IRIPPLE)
Given this target ripple current, the required inductor size can be calculated in Equation 3.
VIN(max) VOUT V 1 14 V 1.8 V 1.8 V 1
L OUT = = 471 nH
" 0.3 I OUT VIN(max) f SW 0.3 10 A 14 V 1200 kHz
(3)
Selecting a standard 400-nH inductor value, solve for IRIPPLE = 3.5 A
The RMS current through the inductor is approximated by Equation 4.
IL(rms ) = IL(avg)2 + 1 I
12 RIPPLE
2
= IOUT 2 + 1 I
12 RIPPLE
2
= 102 + 1 3.52
12 = 10.05 A
(4)

8.2.1.2.3 Output Capacitor Selection (C12)

The selection of the output capacitor is typically driven by the output transient response. Equation 5 and
Equation 6 overestimate the voltage deviation to account for delays in the loop bandwidth and can be used to
determine the required output capacitance.
2
I I I L I L
VOVER < TRAN DT = TRAN TRAN = TRAN
COUT COUT VOUT VOUT COUT (5)
ITRAN I I L L ITRAN2
VUNDER < DT = TRAN TRAN =
COUT COUT VIN - VOUT (VIN - VOUT ) COUT
(6)
If VIN(min) > 2 VOUT, use overshoot (Equation 5) to calculate minimum output capacitance. If VIN(min) < 2 VOUT,
use undershoot (Equation 6) to calculate minimum output capacitance.
ITRAN(max)2 L 42 400nH
COUT(min) = = = 35 mF
(VOUT ) VOVER 1.8 100mV
(7)
With a minimum capacitance, the maximum allowable ESR is determined by the maximum ripple voltage and is
approximated by Equation 8.
IRIPPLE
VRIPPLE(total) -
VRIPPLE(total) - VRIPPLE(cap) 8 COUT fSW
ESRMAX = =
IRIPPLE IRIPPLE

3.5 A
36mV -
8 35 mF 1200kHz
= = 7mW
3.5 A (8)
Two 0805, 22-F, 6.3-V, X5R ceramic capacitors are selected to provide more than 35 F of minimum
capacitance and less than 7 m of ESR (2.5 m each).

8.2.1.2.4 Peak Current Rating of Inductor

With output capacitance, it is possible to calculate the charge current during start-up and determine the minimum
saturation current rating for the inductor. The start-up charging current is approximated by Equation 9.
V COUT 1.8 V 2 22 mF
ICHARGE = OUT = = 0.053 A
tSS 1.5ms (9)

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IL(peak ) = IOUT(max) + 12 IRIPPLE + ICHARGE = 10 A + 12 3.5 A + 0.053 A = 11.8 A

(10)

Table 3. Inductor Requirements

SYMBOL PARAMETER VALUE UNIT
L Inductance 400 nH
IL(rms) RMS current (thermal rating) 10.05 A
IL(peak) Peak current (saturation rating) 11.8 A

A PG0083.401, 400-nH inductor is selected for its small size, low DCR (3.0 m) and high-current handling
capability (17-A thermal, 27-A saturation).

8.2.1.2.5 Input Capacitor Selection (C8)

The input voltage ripple is divided between capacitance and ESR. For this design VRIPPLE(cap) = 150 mV and
VRIPPLE(esr) = 150 mV. The minimum capacitance and maximum ESR are estimated by Equation 11.
ILOAD VOUT 10 1.8 V
CIN(min) = = = 12.5 mF
VRIPPLE(cap) VIN fSW 150mV 8 V 1200kHz
(11)
VRIPPLE(esr ) 150 mV
ESR MAX = = = 12.7 m W
ILOAD + 1
2 IRIPPLE 11.75 A (12)
The RMS current in the input capacitors is estimated by Equation 13.
IRM S (cin ) = ILO A D D (1 - D ) = 10 A 0.225 (1 - 0.225 ) = 4.17 A RM S
(13)
Two 1210, 10-F, 25-V, X5R ceramic capacitors with approximately 2-m of ESR and a 2.5-A RMS current
rating each are selected. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias
voltage to ensure the capacitors allow sufficient capacitance at the working voltage.

8.2.1.2.6 MOSFET Switch Selection (Q1 and Q2)

Reviewing available TI NexFET MOSFETs using TIs NexFET MOSFET selection tool, the CSD16410Q5A and
CSD16322Q5 5-mm 6-mm MOSFETs are selected.
These two FETs have maximum total gate charges of 5 nC and 10 nC, respectively, which draws 18 mA at 1.2
MHz from the BP regulator, less than its 50 mA minimum rating.

8.2.1.2.7 Bootstrap Capacitor (C6)

To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to less than
50 mV.
CBOOST = 20 QG2 = 20 5nC = 100nF (14)

8.2.1.2.8 VDD Bypass Capacitor (C7)

Per the TPS40305 Electrical Characteristics specifications, select a 1.0-F X5R or better ceramic bypass
capacitor for VDD.

8.2.1.2.9 BP Bypass Capacitor (C5)

As listed in the Electrical Characteristics, a minimum of 1.0-F ceramic capacitance is required to stabilize the
BP regulator. To limit regulator noise to less than 10 mV, the value of the bypass capacitor is calculated in
Equation 15.
CBP = 100 MAX(QG1,QG2 ) (15)
Because Q1 is larger than Q2, and the total gate charge of Q1 is 10 nC, a BP capacitor of 1.0 F is calculated. A
standard value of 1.0 F is selected to limit noise on the BP regulator.

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8.2.1.2.10 Short-Circuit Protection (R11)

The TPS40305 uses the negative drop across the low-side FET at the end of the OFF time to measure the
inductor current. Allowing for 30% over maximum load and 20% rise in RDS(on)Q1 for self-heating, the voltage drop
across the low-side FET at current limit is given by Equation 16.
VOC = (1.3 ILOAD 21 IRIPPLE ) 1.2 R DS (on) Q1 = (1.3 10 A 21 3.5 A) 1.2 4.6 m = 62.1 mV
(16)
The TPS40305 internal temperature coefficient helps compensate for the RDS(on) temperature coefficient of the
MOSFET, so the current limit programming resistor is selected by Equation 17.
VOC VOCLOS(min) 62.1mV ( 8mV)
RCS = = = 3.69 k 3.74 k
2 IOCSET(min) 2 9.5 mA ! (17)

8.2.1.2.11 Feedback Divider (R4, R5)

The TPS40305 controller uses a full operational amplifier with an internally fixed 0.600-V reference. R4 is
selected between 10 k and 50 k for a balance of feedback current and noise immunity. With R4 set to 10 k,
The output voltage is programmed with a resistor divider given by Equation 18.
VFB R4 0.600 V 10.0kW
R5 = = = 5.0kW 4.99kW
VOUT - VFB 1.8 V - 0.600 V (18)

8.2.1.2.12 Compensation: (C2, C3, C4, R3, R6)

Using the TPS40k Loop Stability Tool for 100-kHz bandwidth and 60 phase margin with a R4 value of 10.0 k,
the following values are returned.
C2 = C_1 = 820 pF
C3 = C_3 = 150 pF
C4 = C_2 = 3300 pF
R3 = R_2 = 422
R6 = R_3 = 2.20 k

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8.2.1.3 Application Curves

100 225 95
VIN = 14 V Phase VIN = 8 V
80 IOUT = 10 A 180 90
BW = 82 kHz
Phase Margin 55 85
60 135

80 VIN = 12 V

h Efficiency %
40 90 VIN = 14 V
Gain dB

Phase
75
20 45
70
0 0
65
-20 Gain -45
60
-40 -90
55
-60 -135
0.1 1 10 100 1k 50
f Frequency kHz
0 2 4 6 8 10

Figure 15. Gain and Phase vs Frequency ILOAD Load Current A

Figure 16. Efficiency vs Load Current

Figure 17. Output Ripple (500-MHz Bandwidth)

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8.2.2 A High-Current, Low-Voltage Design Using the TPS40304

For this 20-A, 12-V to 1.2-V design, the 600-kHz TPS40304 was selected for a balance between small size and
high efficiency.

Figure 18. TPS40304 Design Example Schematic

8.2.2.1 Design Requirements

For this example, follow the design parameters listed in Table 4.

Table 4. Design Example Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage 8 14 V
VINripple Input ripple IOUT = 20 A 0.5 V
VOUT Output voltage 0 A IOUT 20 A 1.164 1.200 1.236 V
Line regulation 8 V VIN 14 V 0.5%
Load regulation 0 A IOUT 20 A 0.5%
VRIPPLE Output ripple IOUT = 20 A 36 mV
VOVER Output overshoot 5 A IOUT 15 A 100 mV
VUNDER Output undershoot 5 A IOUT 15 A 100 mV
IOUT Output current 8 V VIN 14 V 0 20 A
tSS Soft-start time VIN = 12 V 1.5 ms
ISCP Short-circuit current trip point 26 A
fSW Switching frequency 600 kHz
Size 1.5 in2

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Selecting the Switching Frequency

To achieve the small size for this design the TPS40304, with fSW = 600 kHz, is selected for minimal external
component size.

8.2.2.2.2 Inductor Selection (L1)

Synchronous buck power inductors are typically sized for approximately 30% peak-to-peak ripple current (IRIPPLE)
Given this target ripple current, the required inductor size can be calculated in Equation 19.
VIN(max) - VOUT V 1 14V - 1.2V 1.2V 1
L OUT = = 305nH
0.3 IOUT VIN(max) FSW 0.3 20A 14V 600kHz (19)
Selecting a standard 300-nH inductor value, solve for IRIPPLE = 6 A
The RMS current through the inductor is approximated by Equation 20.

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I Lrms = I Lavg2 + 1 I
12 RIPPLE
2
= I OUT2 + 1 I
12 RIPPLE
2 = 202 + 112 62 = 20.07 A
(20)

8.2.2.2.3 Output Capacitor Selection (C12)

The selection of the output capacitor is typically driven by the output transient response. Equation 21 and
Equation 22 overestimate the voltage deviation to account for delays in the loop bandwidth and can be used to
determine the required output capacitance.
2
I I I L I L
VOVER < TRAN DT = TRAN TRAN = TRAN
COUT COUT VOUT VOUT COUT (21)
ITRAN I I L L ITRAN2
VUNDER < DT = TRAN TRAN =
COUT COUT VIN - VOUT (VIN - VOUT ) COUT
(22)
If VIN(min) > 2 VOUT, use overshoot (Equation 21) to calculate minimum output capacitance. If VIN(min) < 2 VOUT,
use undershoot (Equation 22) to calculate minimum output capacitance.
ITRAN(MAX)2 L 102 300nH
COUT(MIN) = = = 250mF
(VOUT ) VOVER 1.2 100mV (23)
With a minimum capacitance, the maximum allowable ESR is determined by the maximum ripple voltage and is
approximated by Equation 24.
IRIPPLE 6A
VRIPPLE(total) - 36mV -
VRIPPLE(Total) - VRIPPLE(CAP) 8 COUT FSW 8 250mF 600kHz
ESRmax = = = = 5.2mW
IRIPPLE IRIPPLE 6A
(24)
Two 47-F and one 220-F capacitors are selected to provide more than 250 F of minimum capacitance and
5.2 m of ESR.

8.2.2.2.4 Peak Current Rating of Inductor

With output capacitance, it is possible to calculate the charge current during start-up and determine the minimum
saturation current rating for the inductor. The start-up charging current is approximated by Equation 25.
VOUT COUT 1.2 V(2 47 mF + 220 m F)
ICHARGE = = = 0.251 A
TSS 1.5 ms (25)
1 +1
IL _ PEAK = I OUT(max) + 2 IRIPPLE + I CHARGE = 20 A 2 6 A + 0.2512 A = 23.25 A (26)

Table 5. Inductor Requirements

PARAMETER VALUE UNIT
L Inductance 300 nH
IL(rms) RMS current (thermal rating) 20.07 A
IL(peak) Peak current (saturation rating) 23.25 A

8.2.2.2.5 Input Capacitor Selection (C8)

The input voltage ripple is divided between capacitance and ESR. For this design VRIPPLE(cap) = 150 mV and
VRIPPLE(esr) = 150 mV. The minimum capacitance and maximum ESR are estimated by Equation 27.
ILOAD VOUT 20 1.2V
CIN(min) = = = 33.3uF
VRIPPLE(CAP) VIN FSW 150mV 8V 600kHz (27)
VRIPPLE(ESR) 150 mV
ESRMAX = = = 6.5 mW
ILOAD + 1 I 23A
2 RIPPLE (28)
The RMS current in the input capacitors is estimated by Equation 29.
IRMS _ CIN = ILOAD D (1 D) = 20 A 0.15 (1 - 0.15) = 7.14 Arms
(29)
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Three 1210, 10-F, 25-V, X5R ceramic capacitors are selected. Higher voltage capacitors are selected to
minimize capacitance loss at the DC bias voltage to ensure the capacitors allow sufficient capacitance at the
working voltage.

8.2.2.2.6 MOSFET Switch Selection (Q1 and Q2)

Reviewing available TI NexFET MOSFETs using the TI NexFET MOSFET selection tool, the CSD16410Q5A and
CSD16321Q5 5-mm 6-mm MOSFETs are selected.
These two FETs have maximum total gate charges of 5 nC and 10 nC, respectively.

8.2.2.2.7 Bootstrap Capacitor (C6)

To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to less than
50 mV.
CBoost = 20 QG1 = 20 5 nC = 100 nF (30)

8.2.2.2.8 VDD Bypass Capacitor (C7)

Per the TPS40304 data sheet, select a 1.0-uF X5R or better ceramic bypass capacitor for VDD.

8.2.2.2.9 BP Bypass Capacitor (C5)

Per the TPS40304 data sheet, a minimum 1.0-uF ceramic capacitance is required to stabilize the BP regulator.
To limit regulator noise to less than 10 mV, the value of the bypass capacitor is calculated in Equation 31.
CBP = 100 MAX(QG1,QG2 ) (31)
Because Q2 is larger than Q1, and the total gate charge of Q2 is 10 nC, a BP capacitor of 1.0 F is calculated. A
standard value of 1.0 F is selected to limit noise on the BP regulator.

8.2.2.2.10 Short-Circuit Protection (R11)

The TPS40304 uses the negative drop across the low-side FET at the end of the OFF time to measure the
inductor current. Allowing for 30% over maximum load and 20% rise in RDS(on)Q1 for self-heating, the voltage drop
across the low-side FET at current limit is given by Equation 32.
VOC = (1.3 ILOAD - 21 Iripple ) 1.2 RDSONG2 = (1.3 20 A- 21 6 A) 1.2 4.6 mW = 127 mV
(32)
The TPS40304 internal temperature coefficient helps compensate for the MOSFETs RDS(on) temperature
coefficient, so the current limit programming resistor is selected by Equation 33.
VOC - VOCLOS(min) 127 mV - ( 8 mV)
RCS = = = 7.1 kW
2 IOCSET(min) 2 9.5 mA
(33)

8.2.2.2.11 Feedback Divider (R4, R5)

The TPS40304 controller uses a full operational amplifier with an internally fixed 0.6-V reference. R4 is selected
between 10 k and 50 k for a balance of feedback current and noise immunity. With R4 set to 10 k, The
output voltage is programmed with a resistor divider given by Equation 34.
VFB R4 0.600 V 10.0 kW
R7 = = = 10 kW
VOUT - VFB 1.2 V - 0.600 V (34)

8.2.2.2.12 Compensation: (C2, C3, C4, R3, R6)

Using the TPS40k Loop Stability Tool for 100-kHz bandwidth and 60 phase margin with a R4 value of 10.0 k,
the following values are returned.
C4 = 680 pF
C5 = 100 pF
C6 = 680 pF
R1 = 10 k
R2 = 1.5 k
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8.2.2.3 Application Curves

95 100 225
VIN = 8 V
90 80 180
Phase
85 60 135

80 VIN = 14 V
h Efficiency %

40 90

Gain dB

Phase
75 VIN = 12 V
20 45
70
0 0
65
20 45
Gain
60
40 90
55
60 135
50 1k 10 k 100 k 1M
0 5 10 15 20
f Frequency Hz
ILOAD Load Current A Figure 20. Gain and Phase vs Frequency

Figure 19. Efficiency vs Load Current

Figure 21. Output Ripple 10 mV/div, 2-s/div, 20-MHz Bandwidth

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8.2.3 A Synchronous Buck Application Using the TPS40303

Figure 22 shows a 3.3-V/5-V/12-V to 0.6-V at 10-A synchronous buck application using the TPS40303 switching
at 300 kHz.

0.6

+ +

Figure 22. TPS40303 Design Example Schematic

8.2.3.1 Design Requirements

For this example, follow the design parameters listed in Table 6.

Table 6. Design Example Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage 3.3 14 V
VINripple Input ripple IOUT = 10 A 0.6 V
VOUT Output voltage 0 A IOUT 10 A 0.582 0.6 0.618 V
Line regulation 3 V VIN 14 V 0.5%
Load regulation 0 A IOUT 10 A 0.5%
VRIPPLE Output ripple IOUT = 10 A 12 mV
VOVER Output overshoot 3 A IOUT 7 A 100 mV
VUNDER Output undershoot 3 A IOUT 7 A 100 mV
IOUT Output current 3.3 V VIN 14 V 0 10 A
tSS Soft-start time VIN = 12 V 1.5 ms
ISCP Short-circuit current trip point 13 15 A
Efficiency VIN = 12 V, IOUT = 5 A 84%
fSW Switching frequency 300 kHz
Size 1.5 in2

8.2.3.2 Detailed Design Procedure

8.2.3.2.1 Selecting the Switching Frequency

To achieve the small size for this design the TPS40303, with fSW = 300 kHz, is selected for minimal external
component size.

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8.2.3.2.2 Inductor Selection (L1)

Synchronous buck power inductors are typically sized for approximately 30% peak-to-peak ripple current (IRIPPLE)
Given this target ripple current, the required inductor size can be calculated in Equation 35.
VIN(max) - VOUT V 1 14V - 0.6V 0.6V 1
L OUT = = 638nH
0.3 IOUT VIN(max) FSW 0.3 10A 14V 300kHz (35)
Selecting a standard 600-nH inductor value, solve for IRIPPLE = 3.2 A
The RMS current through the inductor is approximated by Equation 36.
ILrms = ILavg2 + 1 I
12 RIPPLE
2
= IOUT 2 + 1 I
12 RIPPLE
2
= 102 + 1 3.22
12 = 10.04A
(36)

8.2.3.2.3 Output Capacitor Selection (C12)

The selection of the output capacitor is typically driven by the output transient response. Equation 37 and
Equation 38 overestimate the voltage deviation to account for delays in the loop bandwidth and can be used to
determine the required output capacitance.
2
I I I L I L
VOVER < TRAN DT = TRAN TRAN = TRAN
COUT COUT VOUT VOUT COUT (37)
ITRAN I I L L ITRAN2
VUNDER < DT = TRAN TRAN =
COUT COUT VIN - VOUT (VIN - VOUT ) COUT
(38)
If VIN(min) > 2 VOUT, use overshoot (Equation 37) to calculate minimum output capacitance. If VIN(min) < 2 VOUT,
use undershoot (Equation 38) to calculate minimum output capacitance.
ITRAN(MAX)2 L 42 600 nH
COUT(MIN) = = = 160 mF
(VOUT) VOVER 0.6 100 mV
(39)
With a minimum capacitance, the maximum allowable ESR is determined by the maximum ripple voltage and is
approximated by Equation 40.
IRIPPLE 3.2 A
VRIPPLE(total) - 36 mV -
VRIPPLE(Total) - VRIPPLE(CAP) 8 COUT FSW 8 160 m F 300 kHz = 8.6 mW
ESRmax = = =
IRIPPLE IRIPPLE 3.2 A
(40)
Two 560-F capacitors are selected to provide more than 160-F of minimum capacitance and less than 8.6 m
of ESR.

8.2.3.2.4 Peak Current Rating of Inductor

With output capacitance, it is possible to calculate the charge current during start-up and determine the minimum
saturation current rating for the inductor. The start-up charging current is approximated by Equation 41.
V COUT 0.6 V(2 560 mF)
ICHARGE = OUT = = 0.448 A
TSS 1.5 ms (41)
IL _ PEAK = IOUT(max) + 1 1
2 IRIPPLE + ICHARGE = 10A + 2 3.2A + 0.448A = 12.05A (42)

Table 7. Inductor Requirements

PARAMETER VALUE UNIT
L Inductance 600 nH
IL(rms) RMS current (thermal rating) 10.04 A
IL(peak) Peak current (saturation rating) 12.05 A

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8.2.3.2.5 Input Capacitor Selection (C8)

The input voltage ripple is divided between capacitance and ESR. For this design VRIPPLE(cap) = 150 mV and
VRIPPLE(esr) = 150 mV. The minimum capacitance and maximum ESR are estimated by Equation 43.
ILOAD VOUT 10 0.6 V
CIN(min) = = = 40.4 uF
VRIPPLE(CAP) VIN FSW 150 mV 3.3 V 300 kHz
(43)
VRIPPLE(ESR) 150 mV
ESRMAX = = = 13 mW
ILOAD + 1 I 11.6 A
2 RIPPLE (44)
The RMS current in the input capacitors is estimated by Equation 45.
IRMS _ CIN = ILOAD D (1 - D) = 10 A 0.2 (1 - 0.2) = 4 Arms
(45)
Five 1210, 10-F, 25-V, X5R ceramic capacitors with approximately 2-m of ESR and a 2.5-A RMS current
rating each are selected. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias
voltage to ensure the capacitors allow sufficient capacitance at the working voltage.

8.2.3.2.6 MOSFET Switch Selection (Q1 and Q2)

Reviewing available TI NexFET MOSFETs using the TI NexFET MOSFET selection tool, the CSD16323Q3 and
CSD16323Q3 5-mm 6-mm MOSFETs are selected. These two FETs have maximum total gate charges of 8.4
nC.

8.2.3.2.7 Bootstrap Capacitor (C6)

To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to less than
50 mV.
CBoost = 20 QG1 = 20 8.4 nC = 100 nF (46)

8.2.3.2.8 VDD Bypass Capacitor (C7)

Per the TPS40305 Electrical Characteristics specifications, select a 1.0-F X5R or better ceramic bypass
capacitor for VDD.

8.2.3.2.9 BP Bypass Capacitor (C5)

Per the TPS40303 data sheet, a minimum 1.0-uF ceramic capacitance is required to stabilize the BP regulator.
To limit regulator noise to less than 10 mV, the value of the bypass capacitor is calculated in Equation 47.
CBP = 100 MAX(QG1,QG2 ) (47)
Because both Q1 and Q2s are the same, total gate charge is 8.4 nC, a BP capacitor of 0.84 F is calculated. A
standard value of 1.0 uF is selected to limit noise on the BP regulator.

8.2.3.2.10 Short-Circuit Protection (R11)

The TPS40305 uses the negative drop across the low-side FET at the end of the OFF time to measure the
inductor current. Allowing for 30% over maximum load and 20% rise in RDS(on)Q1 for self-heating, the voltage drop
across the low-side FET at current limit is given by Equation 48.
VOC = (1.3 ILOAD - 21 Iripple ) 1.2 RDSONQ2 = (1.3 10A - 21 3.2A) 1.2 4.4mW = 60mV
(48)
The TPS40305 internal temperature coefficient helps compensate for the MOSFETs RDS(on) temperature
coefficient, so the current limit programming resistor is selected by Equation 49.
VOC - VOCLOS(min) 60 mV - (- 8 mV)
RCS = = = 3.6 kW
2 IOCSET(min) 2 9.5 mA
(49)

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8.2.3.2.11 Feedback Divider (R4, R5)

The TPS40305 controller uses a full operational amplifier with an internally fixed 0.600-V reference. R5 is
selected between 10 k and 50 k for a balance of feedback current and noise immunity. With R5 set to 10 k,
the output voltage is programmed with a resistor divider given by Equation 50. Because the feedback voltage is
equal to output voltage, low-side voltage divider resistor is not needed.
VFB R5
RLowside =
VOUT - VFB (50)

8.2.3.2.12 Compensation: (C2, C3, C4, R3, R6)

Using the TPS40k Loop Stability Tool for 100-kHz bandwidth and 60 phase margin with a R5 value of 10 k,
the following values are returned.
C8 = 10 nF
C14 = 270 pF
C15 = 4.7 nF
R6 = 2.74 k
R3 = 1 k

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8.2.3.3 Application Curves

A typical efficiency graph for this design example using the TPS40303 is shown in Figure 23.The typical line and
load regulation this design example using the TPS40303 is shown in Figure 24

100 601
VIN = 3.3 V
90
600
VIN = 3.3 V
80
599

VOUT Output Voltage V

70
h Efficiency %

60 VIN = 5 V 598

50 597 VIN = 5 V
VIN = 12 V
40
596
30
595
20
VIN = 12 V
594
10

0 593
0 2 4 6 8 10 0 2 4 6 8 10

ILOAD Load Current A ILOAD Load Current A

Figure 23. Efficiency vs Load Current Figure 24. Line and Load Regulation

80 200
Gain
60 Phase 175

40 150

20 125
Gain (dB)

Phase ()

0 100

-20 75

-40 50

-60 25

-80 0
10 20 50 100 1000 10000 100000 1000000
Frequency (Hz) D001
D008
D002
Figure 25. Total System Bode

9 Power Supply Recommendations

These devices are designed to operate from an input voltage supply between 3 V and 20 V. This input supply
should remain within the input voltage supply range. This supply must be well regulated.

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10 Layout

10.1 Layout Guidelines

For MOSFET or Power Block Layout, follow the layout recommendations provided for the MOSFET or Power
Block selected.
Connect VDD to VIN as close as possible to the drain connection of the high-side FET to avoid introducing
additional drop which could trigger short-circuit protection.
VDD and BP to GND capacitors should be placed within 2 mm of the device and connected to the Thermal
Pad (GND).
The FB to GND resistor should connect to the thermal tab (GND) with a minimum 10-mil wide trace.
Place VOUT to FB resistor within 2 mm of the FB pin.
The EN/SS-to-GND capacitor should connect to the thermal tab (GND) with a minimum 10-mil-wide trace. It
may share this trace with FB to GND.
If a BJT or MOSFET is used to disable EN/SS, it should be placed within 5 mm of the device.
If a COMP to GND resistor is used, it should be placed within 5 mm of the device.
All COMP and FB traces should be kept minimum line width and as short as possible to minimize noise
coupling.
EN/SS should not be routed more than 20 mm from the device.
If multiple layers are used, extend GND under all components connected to FB, COMP and EN/SS to reduce
noise sensitivity.
HDRV and LDRV should provide short, low inductance paths of 5 mm or less to the gates of the MOSFETs or
Power Block.
No more than 1 of resistance should be placed between HDRV or LDRV and their MOSFET or Power
Block gate pins.
LDRV / OC to GND Current Limit Programming resistor may be placed on the far side of the MOSFET if
necessary to ensure a short connection from LDRV to the gate of the low-side MOSFET.
The BOOT to SW resistor and capacitor should both be placed within 4 mm of the device using a minimum of
10-mil-wide trace. The full width of the component pads are preferred for trace widths if design rules allow.
If via must be used between the HDRV, SW and LDRV pins and their respective MOSFET or Power Block
connections, use a minimum of two vias to reduce parasitic inductance
Refer to the Land Pattern Data for the preferred layout of thermal vias within the thermal pad.
It is recommended to extend the top-layer copper area of the thermal pad (GND) beyond the package a
minimum 3 mm between pins 1 and 10 and 5 and 6 to improve thermal resistance to ambient of the device.

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 TPS40303, TPS40304, TPS40305
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10.2 Layout Example

Figure 26. Top Copper With Components Figure 27. Top Internal Copper Layout
.. ..
.. ..

Figure 28. Bottom Internal Copper Layout Figure 29. Bottom Copper Layer

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Product Folder Links: TPS40303 TPS40304 TPS40305
TPS40303, TPS40304, TPS40305
SLUS964B NOVEMBER 2009 REVISED MAY 2015 www.ti.com

11 Device and Documentation Support

11.1 Device Support

The devices listed in have characteristics similar to the TPS4030x and may be of interest.

Table 8. Related Devices

DEVICE DESCRIPTION
TPS40192/3 4.5 V to 18 V Input 10-pin Synchronous Buck Controller with Power Good
TPS40195 4.5 V to 20 V Synchronous Buck Controller with Synchronization and Power Good
TPS40190 Low Pin Count Synchronous Buck Controller

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Documentation
These references, design tools and links to additional references, including design software, may be found at
http://power.ti.com
1. Additional PowerPAD information may be found in Applications Briefs (SLMA002) and (SLMA004).
2. Under The Hood Of Low Voltage DC/DC Converters SEM1500 Topic 5 2002 Seminar Series
3. Understanding Buck Power Stages in Switchmode Power Supplies, (SLVA057), March 1999
4. Designing Stable Control Loops SEM 1400 2001 Seminar Series

11.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 9. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TPS40303 Click here Click here Click here Click here Click here
TPS40304 Click here Click here Click here Click here Click here
TPS40305 Click here Click here Click here Click here Click here

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

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 TPS40303, TPS40304, TPS40305
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11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright 20092015, Texas Instruments Incorporated Submit Documentation Feedback 31

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 PACKAGE OPTION ADDENDUM

www.ti.com 26-Oct-2016

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TPS40303DRCR ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 125 0303
& no Sb/Br) CU NIPDAUAG
TPS40303DRCT ACTIVE VSON DRC 10 250 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 125 0303
& no Sb/Br) CU NIPDAUAG
TPS40304DRCR ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 0304
& no Sb/Br)
TPS40304DRCT ACTIVE VSON DRC 10 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 0304
& no Sb/Br)
TPS40305DRCR ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 125 0305
& no Sb/Br) CU NIPDAUAG
TPS40305DRCT ACTIVE VSON DRC 10 250 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 125 0305
& no Sb/Br) CU NIPDAUAG

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Oct-2016

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Aug-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS40303DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS40303DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS40304DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS40304DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS40305DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS40305DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS40305DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS40305DRCT VSON DRC 10 250 180.0 12.5 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 4-Aug-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS40303DRCR VSON DRC 10 3000 367.0 367.0 35.0
TPS40303DRCT VSON DRC 10 250 210.0 185.0 35.0
TPS40304DRCR VSON DRC 10 3000 367.0 367.0 35.0
TPS40304DRCT VSON DRC 10 250 210.0 185.0 35.0
TPS40305DRCR VSON DRC 10 3000 367.0 367.0 35.0
TPS40305DRCR VSON DRC 10 3000 338.0 355.0 50.0
TPS40305DRCT VSON DRC 10 250 210.0 185.0 35.0
TPS40305DRCT VSON DRC 10 250 338.0 355.0 50.0

Pack Materials-Page 2
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