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TPS54310
SLVS412F – DECEMBER 2001 – REVISED APRIL 2019

TPS54310 3-V to 6-V Input, 3-A Output Synchronous-Buck PWM Switcher

With Integrated FETs
1 Features 3 Description
1• 60-mΩ MOSFET switches for high efficiency at 3- As a member of one of TI's families of dc/dc
A continuous output source or sink current regulators, the TPS54310 low-input-voltage high-
output-current synchronous-buck PWM converter
• Adjustable output voltage down to 0.9 V With 1% integrates all required active components. Included
accuracy on the substrate with the listed features are a true,
• Externally compensated for design flexibility high performance, voltage error amplifier that
• Fast transient response provides high performance under transient conditions;
an undervoltage-lockout circuit to prevent start-up
• Wide PWM frequency: fixed 350 kHz, 550 kHz, or until the input voltage reaches 3 V; an internally and
adjustable 280 kHz to 700 kHz externally set slow-start circuit to limit in-rush
• Load protected by peak current limit and thermal currents; and a power good output useful for
shutdown processor/logic reset, fault signaling, and supply
• Integrated solution reduces board area and total sequencing.
cost The TPS54310 device is available in a thermally
enhanced 20-pin HTSSOP (PWP) PowerPAD™
2 Applications package, which eliminates bulky heatsinks. TI
provides evaluation modules to aid in quickly
• Low-voltage, high-density systems with power achieving high- performance power supply designs to
distributed at 5 V or 3.3 V meet aggressive equipment development cycles.
• Point-of-load regulation for high
performance DSPs, FPGAs, ASICs, and Device Information(1)
microprocessors PART NUMBER PACKAGE BODY SIZE (NOM)
• Broadband, networking and optical TPS54310
HTSSOP
6.40 mm × 6.30 mm
communications infrastructure PowerPAD (20)

• Portable computing/notebook PCs (1) For all available packages, see the orderable addendum at
the end of the data sheet.

Simplified Schematic Efficiency vs Load Current

Input Output 96
VIN PH
TPS54310 94

BOOT 92
PGND
Efficiency − %

90
VBIAS VSENSE
AGND COMP 88

86

84
TA = 25°C
82 VI = 5 V
VO = 3.3 V
80
0 0.5 1 1.5 2 2.5 3
Load Current − A

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................... 9
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 12
3 Description ............................................................. 1 9 Application and Implementation ........................ 13
4 Revision History..................................................... 2 9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 18
7 Specifications......................................................... 4 11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
7.1 Absolute Maximum Ratings ...................................... 4
11.2 Layout Example .................................................... 19
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4 12 Device and Documentation Support ................. 20
7.4 Thermal Information .................................................. 4 12.1 Related DC/DC Products ...................................... 20
7.5 Dissipation Ratings .................................................. 5 12.2 Receiving Notification of Documentation Updates 20
7.6 Electrical Characteristics........................................... 5 12.3 Community Resources.......................................... 20
7.7 Typical Characteristics .............................................. 7 12.4 Trademarks ........................................................... 20
12.5 Electrostatic Discharge Caution ............................ 20
8 Detailed Description .............................................. 9
12.6 Glossary ................................................................ 20
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9 13 Mechanical, Packaging, and Orderable
Information ........................................................... 20

4 Revision History
Changes from Revision E (November 2014) to Revision F Page

• Editorial updates only; no technical changes ........................................................................................................................ 1

Changes from Revision D (February 2007) to Revision E Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

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5 Device Comparison Table

DEVICE OUTPUT VOLTAGE DEVICE OUTPUT VOLTAGE DEVICE OUTPUT VOLTAGE

TPS54311 0.9 V TPS54314 1.8 V TPS54372 DDR/Adjustable
TPS54312 1.2 V TPS54315 2.5 V TPS54373 Prebias/Adjustable
TPS54313 1.5 V TPS54316 3.3 V TPS54380 Sequencing/Adjustable

6 Pin Configuration and Functions

PWP PACKAGE
20-PINs
Top View

AGND 1 20 RT
VSENSE 2 19 SYNC
COMP 3 18 SS/ENA
PWRGD 4 17 VBIAS
BOOT 5 16 VIN
PH 6 15 VIN
PH 7 14 VIN
PH 8 13 PGND
PH 9 12 PGND
PH 10 11 PGND

Pin Functions
PIN
DESCRIPTION
NAME NO.
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor
AGND 1
and SYNC pin. Make PowerPAD connection to AGND.
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
BOOT 5
high-side FET driver.
COMP 3 Error amplifier output. Connect compensation network from COMP to VSENSE.
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
PGND 11–13
areas to the input and output supply returns, and negative terminals of the input and output capacitors.
PH 6–10 Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low
PWRGD 4
when SS/ENA is low or internal shutdown signal active.
RT 20 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
SS/ENA 18
capacitor input to externally set the start-up time.
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin
SYNC 19 select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor
must be connected to the RT pin.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
VBIAS 17
high quality, low ESR 0.1-µF to 1.0-µF ceramic capacitor.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
VIN 14–16
device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.
VSENSE 2 Error amplifier inverting input.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN, SS/ENA, SYNC –0.3 7 V
RT –0.3 6 V
VI Input voltage
VSENSE –0.3 4 V
BOOT –0.3 17 V
VBIAS, PWRGD, COMP –0.3 7 V
VO Output voltage
PH –0.6 10 V
PH Internally Limited
IO Output voltage
COMP, VBIAS 6 mA
PH 6 A
Sink current COMP 6 mA
SS/ENA, PWRGD 10 mA
Voltage differential AGND to PGND –0.3 0.3 V
Continuous power dissipation See Dissipation
Ratings
TJ Operating virtual junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- ±1500 V
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VI Input voltage range 3 6 V
TJ Operating junction temperature –40 125 °C

7.4 Thermal Information (1)

TPS54310
(2)
THERMAL METRIC PWP UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 26 °C/W
RθJA Junction-to-ambient thermal resistance (without solder coverage on PowerPad) 57.5 °C/W

(1) Test board conditions:

(a) 3 inch × 3 inch, 2 layers, Thickness: 0.062 inch
(b) 1.5 oz copper traces located on the top of the PCB
(c) 1.5 oz copper ground plane on the bottom of the PCB
(d) Ten thermal vias (see recommended land pattern in application section of this data sheet)
(2) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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7.5 Dissipation Ratings

over operating free-air temperature range (unless otherwise noted) (1) (2)

TA = 25°C TA = 70°C TA = 85°C

PACKAGE
POWER RATING POWER RATING POWER RATING
20-Pin PWP with solder 3.85 W (3) 2.12 W 1.54 W
20-Pin PWP without solder 1.73 W 0.96 W 0.69 W

(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2) Test board conditions:
(a) 3 inch × 3 inch, 2 layers, Thickness: 0.062 inch
(b) 1.5 oz copper traces located on the top of the PCB
(c) 1.5 oz copper ground plane on the bottom of the PCB
(d) Ten thermal vias (see recommended land pattern in application section of this data sheet)
(3) Maximum power dissipation may be limited by overcurrent protection.

7.6 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE, VIN
VIN input voltage range 3 6 V
fs = 350 kHz, SYNC = 0.8 V, RT open 6.2 9.6
fs = 550 kHz, SYNC ≥ 2.5 V, RT open, phase pin 8.4 12.8
Quiescent current mA
open
Shutdown, SS/ENA = 0 V 1 1.4
UNDERVOLTAGE LOCK OUT
Start threshold voltage, UVLO 2.95 3
V
Stop threshold voltage, UVLO 2.70 2.80
Hysteresis voltage, UVLO 0.14 0.16 V
(1)
Rising and falling edge deglitch, UVLO 2.5 µs
BIAS VOLTAGE
Output voltage, VBIAS I(VBIAS) = 0 2.70 2.80 2.90 V
VO (2)
Output current, VBIAS 100 µA
CUMULATIVE REFERENCE
Vref Accuracy 0.882 0.891 0.900 V
REGULATION
IL = 1.5 A, fs = 350 kHz, TJ = 85°C 0.07
Line regulation (1) (3)
%/V
IL = 1.5 A, fs = 550 kHz, TJ = 85°C 0.07
IL = 0 A to 3 A, fs = 350 kHz, TJ = 85°C 0.03
Load regulation (1) (3)
%/A
IL = 0 A to 3 A, fs = 550 kHz, TJ = 85°C 0.03
OSCILLATOR
SYNC ≤ 0.8 V, RT open 280 350 420
Internally set free-running frequency range kHz
SYNC ≥ 2.5 V, RT open 440 550 660
RT = 180 kΩ (1% resistor to AGND) (1) 252 280 308
Externally set free-running frequency range RT = 100 kΩ (1% resistor to AGND) 460 500 540 kHz
RT = 68 kΩ (1% resistor to AGND) (1) 663 700 762
High-level threshold voltage, SYNC 2.5 V
Low-level threshold voltage, SYNC 0.8 V
Pulse duration, SYNC (1) 50
Frequency range, SYNC (1) 330 700 kHz
Ramp valley (1) 0.75 V

(1) Specified by the circuit used in Figure 10.

(2) Static resistive loads only
(3) Specified by design
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Electrical Characteristics (continued)

TJ = –40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1)
Ramp amplitude (peak-to-peak) 1 V
Minimum controllable on time (1) 200 ns
Maximum duty cycle 90%
ERROR AMPLIFIER
Error amplifier open loop voltage gain 1 kΩ COMP to AGND (1) 90 110 dB
Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND (1) 3 5 MHz
Error amplifier common-mode input voltage Powered by internal LDO (1) 0 VBIAS V
range
IIB Input bias current, VSENSE VSENSE = Vref 60 250 nA
VO Output voltage slew rate (symmetric), COMP 1 1.4 V/µs
PWM COMPARATOR
PWM comparator propagation delay time,
PWM comparator input to PH pin (excluding 10 mV overdrive (1) 70 85 ns
dead time)
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA 0.82 1.20 1.40 V
Enable hysteresis voltage, SS/ENA (1) 0.03 V
(1)
Falling edge deglitch, SS/ENA 2.5 µs
Internal slow-start time 2.6 3.35 4.1 ms
Charge current, SS/ENA SS/ENA = 0 V 3 5 8 µA
Discharge current, SS/ENA SS/ENA = 0.2 V, VI = 2.7 V 1.5 2.3 4 mA
POWER GOOD
Power good threshold voltage VSENSE falling 90 %Vref
Power good hysteresis voltage(4) 3 %Vref
(4)
Power good falling edge deglitch 35 µs
Output saturation voltage, PWRGD I(sink) = 2.5 mA 0.18 0.30 V
Leakage current, PWRGD VI = 5.5 V 1 µA
CURRENT LIMIT
VI = 3 V, output shorted(4) 4 6.5
Current limit trip point A
VI = 6 V, output shorted(4) 4.5 7.5
Current limit leading edge blanking time(4) 100 ns
(4)
Current limit total response time 200 ns
THERMAL SHUTDOWN
Thermal shutdown trip point(4) 135 150 165 °C
(4)
Thermal shutdown hysteresis 10 °C
OUTPUT POWER MOSFETS
(4)
rDS(o IO = 3 A, VI = 6 V 59 88
Power MOSFET switches (5)
mΩ
n) IO = 3 A, VI = 3 V 85 136

(4) Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design.
(5) Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design.

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7.7 Typical Characteristics

120 100

Drain-Source On-State Resistance − W

Drain-Source On-State Resistance − W
VI = 3.3 V VI = 5 V
100 IO = 3 A IO = 3 A
80

80
60

60
40
40

20
20

0 0
−40 0 25 85 125 −40 0 25 85 125
TJ − Junction Temperature − °C TJ − Junction Temperature − °C

Figure 1. Drain-Source On-State Resistance vs Junction Figure 2. Drain-Source On-State Resistance vs Junction
Temperature Temperature
750

f − Externally Set Oscillator Frequency − kHz

800
f − Internally Set Oscillator Frequency −kHz

RT = 68 k

650 700
SYNC ≥ 2.5 V

600
550
RT = 100 k
500
450
SYNC ≤ 0.8 V
400
RT = 180 k
350
300

250 200
−40 0 25 85 125 −40 0 25 85 125
TJ − Junction Temperature − °C TJ − Junction Temperature − °C

Figure 3. Internally Set Oscillator Frequency vs Junction Figure 4. Externally Set Oscillator Frequency vs Junction
Temperature Temperature
0.895 0.8950
TA = 85°C
VO − Output Voltage Regulation − V
Vref − Voltage Reference − V

0.893 0.8930

0.891 0.8910

0.889 0.8890 f = 350 kHz

0.887 0.8870

0.885 0.8850
−40 0 25 85 125 3 4 5 6
TJ − Junction Temperature − °C VI − Input Voltage − V

Figure 5. Voltage Reference vs Junction Temperature Figure 6. Output Voltage Regulation vs Input Voltage

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Typical Characteristics (continued)

140 0 3.80
RL= 10 kW,
−20
120 CL = 160 pF,
3.65

Internal Slow-Start Time − ms

TA = 25°C −40
100
−60 3.50

Phase − Degrees
80 Phase −80
Gain − dB

3.35
60 −100
−120 3.20
40 Gain
−140
3.05
20
−160
0 −180 2.90

−20 −200 2.75

0 10 100 1k 10 k 100 k 1 M 10 M −40 0 25 85 125
f − Frequency − Hz TJ − Junction Temperature − °C

Figure 7. Error Amplifier Open Loop Response Figure 8. Internal Slow-Start Time vs Junction Temperature
2.25
TJ − 125°C
2
fs = 700 kHz
Device Power Losses − W

1.75

1.5 VI = 3.3 V

1.25

1
VI = 5 V
0.75

0.5

0.25

0
0 1 2 3 4
IL − Load Current − A

Figure 9. Device Power Losses vs Load Current

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8 Detailed Description

8.1 Overview
The TPS54310 low-input-voltage high- output-current synchronous-buck PWM converter integrates all required
active components. Included on the substrate with the listed features are a true, high performance, voltage error
amplifier that provides high performance under transient conditions; an undervoltage-lockout circuit to prevent
start-up until the input voltage reaches 3 V; an internally and externally set slow-start circuit to limit in-rush
currents; and a power good output useful for processor/logic reset, fault signaling, and supply sequencing.

8.2 Functional Block Diagram

AGND VBIAS

VIN
Enable
Comparator
SS/ENA VBIAS REG
Falling SHUTDOWN
Edge ILIM VIN
1.2 V
Deglitch Thermal Comparator 3−6V
Hysteresis: 0.03 Leading
2.5 ms Shutdown
V Edge
150°C
VIN UVLO Blanking
Comparator Falling 100 ns
and
VIN BOOT
Rising
2.95 V Edge
Hysteresis: 0.16 Deglitch 30 mW
V 2.5 ms SS_DIS
SHUTDOWN
LOUT
PH VO
Internal/External
Slow-start +
R Q Adaptive Dead-Time CO
(Internal Slow-start Time = 3.35 ms −
and
Error S Control Logic
Amplifier PWM
Reference Comparator VIN
VREF = 0.891 V 30 mW

OSC PGND

Powergood
Comparator
PWRGD
VSENSE Falling
0.90 Vref Edge
TPS54610 Deglitch
Hysteresis: 0.03 Vref
SHUTDOWN
35 ms

VSENSE COMP RT SYNC

8.3 Feature Description

8.3.1 Undervoltage Lockout (UVLO)
The TPS54310 incorporates an undervoltage lockout circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device
operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator,
and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise
on VIN.

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Feature Description (continued)

8.3.2 Slow Start and Enable (SS/ENA)
The slow-start and enable pin provide two functions; first, the pin act as an enable (shutdown) control by keeping
the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start-up begins. The reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
The second function of the SS/ENA pin provides an external means of extending the slow-start time with a low-
value capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two effects
on start-up. First, a delay occurs between release of the SS/ENA pin and start up of the output. The delay is
proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
1.2 V
t =C
d (SS) × 5 µA (1)
Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor.
The slow-start time set by the capacitor is approximately:
0.7 V
t = C
(SS) (SS) × 5 µA (2)
The actual slow-start is likely to be less than the above approximation due to the brief ramp-up at the internal
rate.

8.3.3 VBIAS Regulator (VBIAS)

The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. The bypass capacitor should be placed close to the BVIAS pin and returned to AGND. External
loading on VBIAS is allowed, with the caution that internal circuits require a minimum BVIAS of 2.7 V, and
external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be
useful as a reference voltage for external circuits.

8.3.4 Voltage Reference

The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the
high precision regulation of the TPS54310, because it cancels offset errors in the scale and error amplifier
circuits

8.3.5 Oscillator and PWM Ramp

The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the SYNC pin as a
static digital input. If a different frequency of operation is required for the application, the oscillator frequency can
be externally adjusted from 280 kHz to 700 kHz by connecting a resistor to the RT pin to ground and floating the
SYNC pin. The switching frequency is approximated by the following equation, where R is the resistance from RT
to AGND:
SWITCHING FREQUENCY = 100 kΩ × 500 kHz
R (3)
External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a resistor from RT to AGND. Choose an RT resistor that sets
the free-running frequency to 80% of the synchronization signal. Table 1 summarizes the frequency selection
configurations.

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Feature Description (continued)

Table 1. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY SYNC PIN RT PIN
350 kHz, internally set Float or AGND Float
550 kHz, internally set ≥ 2.5 V Float
Externally set 280 kHz to 700 kHz Float R = 68 k to 180 k
Externally synchronized frequency Synchronization signal R = RT value for 80% of external synchronization frequency

8.3.6 Error Amplifier

The high performance, wide bandwidth, voltage error amplifier sets the TPS54310 apart from most dc/dc
converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the
particular needs of the application. Type 2 or type 3 compensation can be employed using external
compensation components.

8.3.7 PWM Control

Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic.
Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch.
Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse
duration. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to
charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the
error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and
turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM
ramp.
During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on
until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The
device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting
VSENSE to approximately the same voltage as Vref. If the error amplifier output is low, the PWM latch is
continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM comparator to change states. The TPS54310 is capable of
sinking current continuously until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds
the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the
output inductor and consequently the output current. This process is repeated each cycle in which the current
limit comparator is tripped.

8.3.8 Dead-Time Control and MOSFET Drivers

Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side
driver does not turn on until the gate drive voltage to the low-side FET is below 2 V. The low-side driver does not
turn on until the voltage at the gate of the high-side MOSFETs is below 2 V. The high-side and low-side drivers
are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side
driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an
external BOOT capacitor and an internal 2.5-Ω bootstrap switch connected between the VIN and BOOT pins.
The integrated bootstrap switch improves drive efficiency and reduces external component count.

8.3.9 Overcurrent Protection

The cycle by cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and
differential amplifier and comparing it to the preset overcurrent threshold. The high-side MOSFET is turned off
within 200 ns of reaching the current limit threshold. A 100-ns leading edge blanking circuit prevents false
tripping of the current limit. Current limit detection occurs only when current flows from VIN to PH when sourcing
current to the output filter. Load protection during current sink operation is provided by thermal shutdown.

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8.3.10 Thermal Shutdown

The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from shutdown when the junction temperature decreases to
10°C below the thermal shutdown trip point and starts up under control of the slow-start circuit. Thermal
shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent
fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up due to the
fault, and then shutting down upon reaching the thermal shutdown point.

8.3.11 Powergood (PWRGD)

The powergood circuit monitors for undervoltage conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold, or SS/ENA is low, or thermal shutdown is asserted. When VIN = UVLO threshold,
SS/ENA = enable threshold, and VSENSE > 90% of Vref, the open-drain output of the PWRGD pin is high. A
hysteresis voltage equal to 3% of Vref and a 35-µs falling edge deglitch circuit prevent tripping of the powergood
comparator due to high-frequency noise.

8.4 Device Functional Modes

8.4.1 Continuous Conduction Mode
The TPS54310 operates in continuous conduction mode, that is, the low-side MOSFET runs fully complimentary
to the high-side MOSFET regardless of output current.

8.4.2 Switching Frequency Configuration

Depending on the configuration of the RT and SYNC pins, the TPS54310 can be configured to switch at 350
kHz, or 550 kHz without external components, or any frequency between 280 kHz and 700 kHz as configured by
a resistor from the RT pin to ground. The TPS54310 can also be synchronized to an external clock using the
SYNC pin. See Table 1 for more information.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS54310 is a 3-V to 6-V integrated FET synchronous buck converter. It is used to convert a DC input
voltage on the VIN pins to a lower output voltage at 3 A maximum output current.

9.2 Typical Application

Figure 10 shows the schematic diagram for a typical TPS54310 application. The TPS54310 (U1) can provide up
to 3 A of output current at a nominal output voltage of 3.3 V. For proper thermal performance, the power pad
underneath the TPS54310 integrated circuit needs to be soldered well to the printed-circuit board.
VIN
J1
2
VI
+ U1
1 C2 C8
GND TPS54310PWP
R3 10 mF
1 20 16
RT VIN
R1 71.5 kW 15
19 VIN L1
10 kW SYNC 14
18 VIN 1.2 mH J3
SS/ENA 10 1
17 PH VO
VBIAS 9 2
4 PH + GND
PWRGD PWRGD 8
C3 3 COMP PH C9 C11
0.1 mF 7 180 mF 1000 pF
PH
6 4V
2 PH C7
VSENSE 5
BOOT
13 0.047 mF
1 PGND
AGND 12
PGND
C5 11
3900 pF PGND
C4
100 pF PwrPAD
R2
3.74 kW
C6 R6 R7

732 W 49.9 W
R4 2700 pF
3.74 kW R5
10 kW
1 Optional

Figure 10. TPS54310 Schematic

9.2.1 Design Requirements

Design requirements for this example are as follows:
• DC input voltage: 3 V – 6 V
• DC output current: 0 A – 3 A
• Load regulation: ±0.5%
• Output voltage ripple: 30 mV
• Input voltage ripple: 150 mV

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Typical Application (continued)

9.2.2 Detailed Design Procedure

9.2.2.1 Input Voltage

The input to the circuit is a nominal 5 VDC, applied at J1. The optional input filter (C2) is a 220-µF POSCAP
capacitor, with a maximum allowable ripple current of 3 A. C8 is the decoupling capacitor for the TPS54310 and
must be located as close to the device as possible.

9.2.2.2 Feedback Circuit

The resistor divider network of R5 and R4 sets the output voltage for the circuit at 3.3 V. R5, along with R2, R6,
C4, C5, and C6 forms the loop compensation network for the circuit. For this design, a Type 3 topology is used.

9.2.2.3 Setting the Output Voltage

The output voltage of the TPS54310 can be set by feeding back a portion of the output to the VSENSE pin using
a resistor divider network. In the application circuit of Figure 10, this divider network is comprised of resistors R5
and R4. To calculate the resistor values to generate the required output voltage use Equation 4.
R5 x 0.891
R4 =
VO - 0.891 (4)
Start with a fixed value of R5 and calculate the required R4 value. Assuming a fixed value of 10 kΩ for R5, the
following table gives the appropriate R4 value for several common output voltages:

Table 2. R4 Values for Common Output Voltages

OUTPUT VOLTAGE (V) R4 VALUE (KΩ)
1.2 28.7
1.5 14.7
1.8 9.76
2.5 5.49
3.3 3.74

9.2.2.4 Operating Frequency

In the application circuit, the 350-kHz operation is selected by leaving RT and SYNC open. Connecting a 68-kΩ
to 180-kΩ resistor between RT (pin 20) and analog ground can be used to set the switching frequency from
280 kHz to 700 kHz. To calculate the RT resistor, use the Equation 5:
R = 100 kΩ × 500 kHz
ƒ
SW (5)

9.2.2.5 Output Filter

The output filter is composed of a 1.2-µH inductor and 180-µF capacitor. The inductor is a low dc resistance
(0.017 Ω) type, Coilcraft DO1813P-122HC. The capacitor used is a 4-V special polymer type with a maximum
ESR of 0.015 Ω. The feedback loop is compensated so that the unity gain frequency is approximately 75 kHz.

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9.2.3 Application Curves

Figure 11. Efficiency vs. Load Current Figure 12. Power Loss vs. Load Current

Figure 13. Junction Temperature vs. Load Current Figure 14. Load Regulation

Figure 15. Output Voltage Ripple Figure 16. Input Voltage Ripple

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Figure 17. Start-Up From VIN Figure 18. System Bode Plot

100 3.4
VI = 4 V VI = 5 V TA = 25°C
95 3.38 VI = 5 V

VO − Output Voltage − %
3.36
90
VI = 6 V
Efficiency − %

3.34
85
3.32
80
3.3
75
3.28

70 3.26

65 3.24
0 1 2 3 4 5 0 1 2 3 4 5
IO − Output Current − A IL − Load Current − A

Figure 19. Efficiency vs Output Current Figure 20. Output Voltage vs Load Current

60 135

VO (AC)
Phase
40 90 10 mV/div
Phase − Degrees
Gain − dB

20 45

Gain

0 0
TA = 25°C

−20 −45
VI = 5 V
IO = 3 A
−40 −90
100 1k 10 k 100 k 1M 400 ns/div
f − Frequency − Hz

Figure 21. Loop Response Figure 22. Output Ripple Voltage

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VI = 5 V VO (AC)
40 ms/div 50 mV/div VI 2 V/div

VO 2 V/div

VPWRGD 5 V/div
IO
2 A/div

1 ms/div

Figure 23. Load Transient Response Figure 24. Slow-Start Timing

125

115
VI = 5 V
T A − Ambient Temperature − ° C

105

95

85
VI = 3.3 V
75

65 Safe Operating Area †

55

45

35
25
0 1 2 3 4
IL − Load Current − A
† Safe operating area is applicableto the test board conditions
listed in the dissipation rating table section of this data sheet.

Figure 25. Ambient Temperature vs Load Current

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10 Power Supply Recommendations

The TPS54310 is designed to operate from an input supply from 3 V to 6 V on the VIN pins. This supply must be
well regulated and properly bypassed for proper operation of the TPS54310. Additionally, the VBIAS pin must
have good local bypassing for noise performance. See the recommendations in Pin Configuration and Functions
and Layout Guidelines for more information.

11 Layout

11.1 Layout Guidelines

Figure 26 shows a generalized PCB layout guide for the TPS54310.
The VIN pins should be connected together on the printed circuit board (PCB) and bypassed with a low ESR
ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor
connections, the VIN pins, and the TPS54X10 ground pins. The minimum recommended bypass capacitance is
10-µF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the PGND
pins.
The TPS54310 has two internal grounds (analog and power). Inside the TPS54310, the analog ground ties to all
of the noise sensitive signals, while the power ground ties to the noisier power signals. Noise injected between
the two grounds can degrade the performance of the TPS54310, particularly at higher output currents. Ground
noise on an analog ground plane can also cause problems with some of the control and bias signals. For these
reasons, separate analog and power ground traces are recommended. There should be an area of ground one
the top layer directly under the IC, with an exposed area for connection to the PowerPAD. Use vias to connect
this ground area to any internal ground planes. Use additional vias at the ground side of the input and output
filter capacitors as well. The AGND and PGND pins should be tied to the PCB ground by connecting them to the
ground area under the device as shown. The only components that should tie directly to the power ground plane
are the input capacitors, the output capacitors, the input voltage decoupling capacitor, and the PGND pins of the
TPS54310. Use a separate wide trace for the analog ground signal path. This analog ground should be used for
the voltage set point divider, timing resistor RT, slow start capacitor and bias capacitor grounds. Connect this
trace directly to AGND (pin 1).
The PH pins should be tied together and routed to the output inductor. Since the PH connection is the switching
node, inductor should be located very close to the PH pins and the area of the PCB conductor minimized to
prevent excessive capacitive coupling.
Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close
to the IC and minimize the conductor trace lengths.
Connect the output filter capacitor(s) as shown between the VOUT trace and PGND. It is important to keep the
loop formed by the PH pins, Lout, Cout and PGND as small as practical.
Place the compensation components from the VOUT trace to the VSENSE and COMP pins. Do not place these
components too close to the PH trace. Due to the size of the IC package and the device pinout, they will have to
be routed somewhat close, but maintain as much separation as possible while still keeping the layout compact.
Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If a
slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz operating frequency,
connect them to this trace as well.
For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A
3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient
temperature and airflow. Most applications have larger areas of internal ground plane available, and the
PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also
help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection
from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch
diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area with four
additional vias located under the device package. The size of the vias under the package, but not in the exposed
thermal pad area, can be increased to 0.018. Additional vias beyond the ten recommended that enhance thermal
performance should be included in areas not under the device package.

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11.2 Layout Example

ANALOG GROUND TRACE

FREQUENCY SET RESISTOR

AGND RT

VSENSE SYNC SLOW START

CAPACITOR

COMPENSATION COMP SS/ENA

NETWORK
PWRGD VBIAS
EXPOSED BIAS CAPACITOR
BOOT
BOOT POWERPAD VIN
CAPACITOR AREA

PH VIN Vin
VOUT
PH VIN

PH PGND

OUTPUT INDUCTOR
PH PGND
PH
PH PGND

INPUT INPUT
BYPASS BULK
CAPACITOR FILTER
OUTPUT
FILTER
CAPACITOR

TOPSIDE GROUND AREA

VIA to Ground Plane

Figure 26. TPS54310 PCB Layout

6 PL ∅ 0.0130 Minimum Recommended Thermal Vias: 6 × .013 dia.

4 PL ∅ 0.0180 Inside Powerpad Area 4 × .018 dia. Under Device as Shown.
Additional .018 dia. Vias May be Used if Top Side Analog
Ground Area is Extended.
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.0150
0.06
0.0227

0.0600

0.0400
0.2560 0.2454 0.1010
0.0400

0.0600

0.0256

0.1700 Minimum Recommended Exposed

0.1340 Copper Area For Powerpad. 5mm
Minimum Recommended Top 0.0620 Stencils may Require 10 Percent
Side Analog Ground Area 0.0400
Larger Area

Figure 27. Recommended Land Pattern for 20-Pin PWP PowerPAD

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12 Device and Documentation Support

12.1 Related DC/DC Products

• TPS40000—dc/dc controller
• PT5500 series—3-A plug-in modules
• TPS757XX—3-A low dropout regulator

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 2-Aug-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS54310PWPR ACTIVE HTSSOP PWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54310 Samples

TPS54310PWPRG4 ACTIVE HTSSOP PWP 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54310 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 2-Aug-2023

OTHER QUALIFIED VERSIONS OF TPS54310 :

• Enhanced Product : TPS54310-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54310PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54310PWPR HTSSOP PWP 20 2000 350.0 350.0 43.0

Pack Materials-Page 2
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