Introduction to

CMOS VLSI
Design

Silicon-on-Insulator (SOI)

Curtis Nelson
Walla Walla University
 Outline
q Overview of Silicon-on-Insulator (SOI)
q Floating Body Voltage
q SOI Advantages
q SOI Disadvantages
q Implications for Circuit Styles
q Summary

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 SOI Overview
q SOI-based devices differ from conventional silicon-built devices
in that the silicon junction is above an electrical insulator,
typically silicon dioxide or sapphire (these types of devices are
called silicon on sapphire, or SOS). The choice of insulator
depends largely on intended application, with sapphire being
used for high-performance radio frequency (RF) and radiation-
sensitive applications, and silicon dioxide for diminished short
channel effects in microelectronics devices.

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 SOI Overview
q The implementation of SOI technology is one of several manufacturing
strategies employed to allow the continued miniaturization of microelectronic
devices, colloquially referred to as extending Moore's Law. Reported benefits
of SOI technology relative to conventional silicon (bulk CMOS) processing
include:
Lower parasitic capacitance due to isolation from the bulk silicon, which
improves power consumption.
Resistance to latchup due to complete isolation of the n- and p-well
structures.
Higher performance at equivalent VDD. Can work at low VDD's.
Reduced temperature dependency due to no doping.
Better yield due to high density, better wafer utilization.
Reduced antenna issues.
No body or well taps are needed.
Lower leakage currents due to isolation thus higher power efficiency.
Inherently radiation hardened ( resistant to soft errors ), thus reducing the
need for redundancy.

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 SOI Overview
q Adopted for IBM PowerPC processors in 1998
Higher performance and lower power than CMOS
Higher manufacturing cost and complicated circuit design
q Differences from bulk CMOS
Transistor source, drain, & body (channel) surrounded by
insulating SiO2 rather than substrate (well)
Eliminates most diffusion parasitic Capacitance
Body no longer tied to GND or VDD
Any change in body voltage modulates Vt (which has its own
advantages and disadvantages)

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 SOI Overview
q IBM began to use SOI in the high-end RS64-IV "Istar" PowerPC-AS
microprocessor in 2000. Other examples of microprocessors built on SOI
technology include AMD's 130 nm, 90 nm, 65 nm, 45 nm and 32 nm single,
dual, quad, six and eight core processors since 2001. Freescale adopted SOI
in their PowerPC 7455 CPU in late 2001, currently Freescale is shipping SOI
products in 180 nm, 130 nm, 90 nm and 45 nm lines. The 90 nm Power
Architecture based processors used in the Xbox 360, PlayStation 3 and Wii use
SOI technology as well. Competitive offerings from Intel however continues to
use conventional bulk CMOS technology for each process node, instead
focusing on other venues such as HKMG and Tri-gate transistors to improve
transistor performance. In January 2005, Intel researchers reported on an
experimental single-chip silicon rib waveguide Raman laser built using SOI.
q As for the traditional foundries, on July 2006 TSMC claimed no customer
wanted SOI, but Chartered Semiconductor devoted a whole fab to SOI.

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 SOI Inverter
q Process starts with a wafer containing a thin layer of SiO2
buried beneath a thin single-crystal silicon layer

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 IBM SOI Process
q Scanning electron micrograph of a 6-transistor static RAM cell
in 0.22 um IBM SOI process

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 Two Types of SOI
q Partially depleted (PD)
Body thicker than channel depletion width
Body voltage changes, depending on the amount of charge
injected into bulk
Causes history effect, which changes Vt
q Fully depleted (FD)
Body thinner than channel depletion width
Fixed body charge
Body voltage does not change
Thin body makes this very hard to manufacture
Therefore, seldom used

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 Floating Body Voltage
q Key to understanding SOI is to follow the body voltage
q Body voltage varies as body charges/discharges
q Charge paths to/from floating body

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 Body Charge Paths
q Reverse-biased drain-to-body Ddb and
source-to-body Dsb junctions
Carry small diode leakage currents into
body
q High-energy carriers cause impact
ionization
Create e hole pairs
Injected into gate or gate oxide
Cause hot e wearout
Corresponding holes accumulate in
body
Most pronounced at VDS > intended
operating point
Iii is impaction ionization current into body

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Ways for Charge to Exit Body
q As body voltage increases
Source-to-body Dsb junction slightly
forward biases
Charge exiting from Dsb balances charge
entering from Ddb
q Rising gate/drain voltage capacitively
couples body upward
May strongly forward-bias source-to-body
Dsb junction and spill charge out of body
During long idle periods (micro-seconds),
body Voltage reaches equilibrium
When switching resumes
Charge spills off body
Shifts body voltage and Vt significantly

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 SOI Advantages
q Lower Cdiffusion largely eliminated
q Lower parasitic delay
q Lower dynamic power consumption
q Potential for lower Vt
Bulk CMOS Vt varies with channel length
Poly etching variations cause Vt variations
Must make Vt high enough to limit worst-case subthreshold
leakage, so nominal Vt is typically higher that needs to be
SOI
Smaller threshold variations
Nominal Vt can be closer to worst-case
Faster transistors, especially at low VDD

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 Subthreshold Swing
q Bulk CMOS subthreshold slope of n vT ln10
vT = kT/q (thermal voltage, 26 mV at room temp)
n is process dependent, usually about 1.5
q So subthreshold slope is about 90 mV/decade
For each 90 mV decrease in Vgs below Vt, subthreshold
leakage current is reduced by 10 X
q SOI (IBM) -- subthreshold slope of 75-85 mV/decade
q Double-gate MOSFETs and FINFETs are SOI
variations
Offer even lower subthreshold slopes
Gate surrounds channel turns off quicker

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 FINFETs

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 Latchup
q SOI is immune to latchup because the
insulating oxide eliminates the parasitic
bipolar devices that could trigger latchup

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 SOI Disadvantages
q History effect
Changes in body V modulate Vt, vary gate delay
q Body voltage depends on whether device was idle or
switching -- delay is a function of switching history
q Overall, elevated body voltage
Reduces Vt and makes gates faster but the uncertainty makes
circuit design more challenging
q Model history effect
Assign different propagation and contamination delays to
each gate
History effect causes about 8% gate delay variation (IBM)
Less than process and environmental variations

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 More Disadvantages
q History effect
Causes significant mismatches between otherwise matched
transistors
Sense amplifier (differential pair problems)
Analog OPAMP
Gilbert cell analog multiplier (mixer)
May be solved by introducing substrate contact to make
transistor pair behave identically

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Parasitic Bipolar Transistor
q Can be a problem because the body/base floats

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 Current Pulse Problems
q Hold source & drain high for a long time
While gate is low
Base floats high through diode leakage
q Then, pull source low and npn transistor turns ON
IB flows from body/base to source/emitter
Causes IB to flow from drain/collector to source/emitter
depends on channel length & doping but can be greater than 1
Can get a current pulse from drain to source even though
transistor should be OFF

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 Current Pulse
q This current pulse is sometimes called Pass-gate
Leakage
q Often happens to OFF pass transistors where
source & drain are initially high and then go low
No problem for static circuits because the ON transistors
oppose the glitch
Causes malfunctions in dynamic latches in logic
Need strong keepers to hold node steady

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 Self-Heating Problem
q SiO2 is great thermal and electrical insulator
Heat accumulates in transistors
Rather than spreading to substrate as in CMOS
q Individual transistors with large power
Heat substantially more than the die
Deliver less current, slower
q Can raise T by 10 to 15 C for clock and I/O devices
Less significant for logic

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 Implications for Circuits
q SOI good for fast CMOS logic
Smaller Cdiffusion gives lower parasitic delay
Lower Vt gives better drive current and lower delay
q SOI attractive for low-power design
Smaller Cdiffusion reduces dynamic power
Easier to scale down VDD
Consider FINFETs sharper subthreshold slope
q Static CMOS in PD SOI
Similar to bulk CMOS family, but faster
History effect causes pattern dependent delay variation

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 Dynamic Gates
q New problem: pass-gate leakage
Causes dynamic latches and gates to lose charge on
dynamic node
Fixed by staticizing the output

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 Solve Pass-gate Leakage
q Staticize capacitive storage nodes
Cross-coupled inverter pair for latches
q pMOS keeper for dynamic gates
Can pre-discharge internal nodes to prevent pass-gate
leakage
Then have a charge sharing problem on internal nodes
q Staticizing transistors must be as strong as
normal path
Slows down gates

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 Gated Clock Problems
q Gated clocks have increased skew
History effect makes clock switch more slowly when
activated after being disabled for a long time

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 Summary
q Overview of SOI
q Floating Body Voltage
q SOI Advantages
q SOI Disadvantages
q Implications for Circuit Styles

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