International Journal of Engineering and Advanced Research Technology (IJEART)

ISSN: 2454-9290, Volume-3, Issue-6, June 2017

Architecture of Static Random Access Memory

Design Using 65nm Technology
Mr. Naveen K B, Mrs. Kavya K

Abstract For those headway in innovation organization yield. The principle challenge in the outline of reversible
and sort for Utilization of the hardware gadgets in distinctive circuit is to lessen the refuse yield. A proficient SRAM cell is
applications, request Tremendous size memories will store displayed in this paper with limited refuse yields, with limited
alternately transform those information. Regularly static access quantum delay and limited quantum taken a toll as contrasted
memory (SRAM) cells would utilized because of its secondary
with the current outline . A 16 8 SRAM cluster was created
Pace get to attributes. With the exponential increment in the
Size of the memory, the force devoured Eventually perusing
with the proposed SRAM cell and with decoder.
those memorycells would Likewise expanding exponentially. Whatever is left of the paper is composed as takes
Reversible circuits clinched alongside later a considerable length after. Area II expounds writing Theoretical Background. Area
of time. Have picked up its premium because of its low energy III presents System Overview Segment IV delineate the
qualities. This Paper proposes Reversible SRAM cell with read System Analysis and Results and segment V presents
and write signals. The recommended plan minimizes the number conclusions.
of trash outputs. Eventually perusing 66. 66%, Quantum
expense by 71. 5% Also Quantum delay by. 68. 5% over the II. THEORETICAL BACKGROUND
existing plans. . This paper additionally explains the execution
points of interest of 16 8 SRAM array exhibit with minimum SRAM Basics
trash and quantum cost. The memory circuit is said to be static if the stored data
can be retained indefinitely, as long as the power supply is on,
Index Terms Reversible Logic, SRAM Cell, TRASH without any need for periodic refresh operation. The data
Minimization and quantum cost storage cell, i.e., the one-bit memory cell in the static RAM
arrays, invariably consists of a simple latch circuit with two
stable operating points. Depending on the preserved state of
I. INTRODUCTION the two inverter latch circuit, the data being held in the
Low power VLSI configuration has picked up enthusiasm memory cell will be interpreted either as logic '0' or as logic
for late years due to its extensive variety of uses. Landauer '1'. To access the data contained in the memory cell via a bit
has proposed that for each piece loss of data in consistent line, we need atleast one switch, which is controlled by the
calculations that are not reversible, KT ln2 Joules of vitality corresponding word line
will be scattered as warmth, where K is the Boltzmanns
consistent and T is the temperature in Kelvin at which the A. READ Operation
framework is working. Bennett demonstrated that zero power Consider a data read operation, shown in Figure 28.41,
scattering in rationale circuits is conceivable just if a circuit is assuming that logic '0' is stored in the cell. The transistors M2
made out of reversible rationale entryways. The entryway and M5 are turned off, while the transistors M1 and M6
which does not lose any data is called as reversible door. operate in linear mode. Thus internal node voltages are V1 =
Reversible circuit has picked up its enthusiasm because of its 0 and V2 = VDD before the cell access transistors are turned
minimization of nonadiabatic misfortunes which will on. The active transistors at the beginning of data read
diminish the warmth scattering . With the expansion in the operation
memory application, outlining of low power memory cell has
picked up enthusiasm for late years. A memory that comprises
of circuits fit for holding their state the length of energy is
connected is known as static recollections. Static arbitrary get B. WRITE Operation
to memory (SRAM) is well known among other memory cells Consider the write '0' operation assuming that logic '1' is
because of its rapid qualities. SRAM employments a basic stored in the SRAM cell initially the voltage levels in the
bistable circuit to hold an information bit. Two cross coupled CMOS SRAM cell at the beginning of the data write
inverters in the regular 6T cell shapes a lock which is utilized operation. The transistors M1 and M6 are turned off, while
to store the information. At whatever point there is a M2 and M5 are operating in the linear mode. Thus the internal
requirement for putting away other information in a similar node voltage V1 = VDD and V2 = 0 before the access
cell, past information must be deleted which demonstrates the transistors are turned on. The column voltage Vb is forced to
irreversibility operation of the memory cell and brings about '0' by the write circuitry.
the warmth scattering. The calculations which take put in the
customary memory are irreversible. Morrison et.al., has
proposed SRAM configuration utilizing reversible circuit
plan. Each door yield that is repetitive is known as waste Technology Scaling
Since the 1960s the price of one bit of semiconductor
memory has dropped 100 million times and the trend

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 Architecture of Static Random Access Memory Design Using 65nm Technology

continues. The cost of a logic gate has undergone a similarly data, TABLE I: Truth table for access transistors during
dramatic drop. This rapid price drop has stimulated new writing operation Bit(b) Word Line (WL) Data Stored (D)
applications and semiconductor devices have improved the X 0 Previous Data Stored
ways people carry out just about all human activities. The 111
primary engine the powered the ascent of electronics is 010
miniaturization. By making the transistors and the stored and bit (B) input. If WL = 0, third output will be the
interconnects smaller, more circuits can be fabricated on each previously stored data. If WL = 1, third output will be the bit
silicon wafer and therefore each circuit becomes cheaper. (B) input. During read operation the bit (B) and bit ( B ) of
Miniaturization has also been instrumental in the the SRAM cell is connected to the sense amplifier which is
improvements in speed and power consumption. used to produce the corresponding output data. The latch was
Gordon Moore made an empirical observation in the 1960s modelled by using one Feynman gate and one Fredkin gate.
that the number of devices on a chip doubles every 18 months WL output in 33 Fredkin gate is used to enable the row cells.
or so. The Moores Law is a succinct description of the So, the total number of garbage output for the proposed
persistent periodic increase in the level of miniaturization. SRAM cell is 1. Considering the line 2 in Figure 4 if WL = 0,
Each time the minimum line width is reduced, we say that a data stored will be the output in line 2 of the 3 3 Fredkin gate
new technology generation or technology node is introduced. which resembles the hold state of the access transistor. If WL
Examples of technology generations are 0.18mm, 0.13mm, = 1, data input will be the output of the line 2. This line 2 is fed
90nm, 65nm, 45nmgenerations. The numbers refer to the to the Feynman gate which performs the latch operation.
minimum metal line width. Poly-Si gate length may be
smaller. At each new node, the various feature sizes of circuit B. Proposed SRAM cell with Read and Write
layout, such as the size of contact holes, are 70% of the
Signals
previous node. This practice of periodic size reduction is
called scaling. Historically, a new technology node is This segment examines about the proposed reversible
introduced every three years or so. The main reward for SRAM cell with read and compose signals. Figure 1
introducing a new technology node is the reduction of circuit demonstrates the proposed reversible SRAM cell. A 3 3
size by 2. (70% of previous line width means ~50% reduction Fredkin entryway and a 2 2 Feynman entryway is utilized to
in area, i.e. 0.7 x 0.7= 0.49.) Since nearly twice as many store the single piece of information and it is controlled by
circuits can be fabricated on each wafer with each new two 3 3 Fredkin entryway. Consider reality
technology node, the cost per circuit is reduced significantly. table for traditional SRAM cell as appeared in TableII. So,the
That is the engine that drives down the cost of ICs. Besides contribution to the SRAM cell is word line motion from the
line width, some other parameters are also reduced with push decoder, compose flag, information in, read flag and the
scaling such as the MOSFET gate oxide thickness and the yield of the SRAM cell is compose line which is passed to the
power supply voltage. The reductions are chosen such that the following SRAM cell in a similar column, compose line, read
transistor current density (Ion/W) increases with each new line and information out.
node. Also, the smaller transistors and shorter interconnects The contribution to the 3 3 Fredkin entryways are compose
lead to smaller capacitances. Together, these changes cause flag, consistent info rationale "0" and the information input.
the circuit delays to drop . Historically, integrated circuit The yield of the 3 3 Fredkin entryway are compose flag,
speed has increased roughly 30% at each new technology rubbish and the yield line. At the point when WL = 1 , then
node. Scaling does another good thing reducing capacitance the SRAM cell will be either in read mode or compose mode.
and, especially, the power supply voltage is effective for In the event that compose flag is "1" then whatever the
lowering the power consumption. Thanks to the reduction in estimation of information in will be put away in the SRAM
C and Vdd, power consumption per chip has increased only cell. In the event that the compose flag is "0" and if read flag is
modestly per node in spite of the rise in switching frequency, f "1" then the esteem put away in the SRAM cell will be the
and (gasp) the doubling of transistors per chip at each
estimation of the information out which looks like genuine
technology node. If there had been no scaling, doing the job of
usefulness of the regular SRAM cell. The quantum cost of the
a single PC microprocessor chip-- running 500M transistors
proposed SRAM cell with the read/compose flag is 16 and
at 2GHz using 1970 technology would require the electrical
power output of a medium-size power generation plant. the refuse yield of the proposed configuration is 3. The plan is
checked and reproduced utilizing Verilog HDL in Xilinx.
III. SYSTEM OVERVIEW
A. Proposed 16 8 SRAM Array
This section discusses the proposed SRAM cell design using
reversible gates.The proposed fully reversible SRAM cell. In this area, 168 SRAM cluster was proposed. The decoder
Since the latch and the access transistors in the conventional is utilized to interpret the information address furthermore, is
SRAM is irreversible, latch and access transistors are utilized to choose the proper word lines. The word line yield
modelled with the reversible elements. of each SRAM cell is utilized to empower the following
SRAM cell there by decreasing the rubbish yield of each
A. Proposed Reversible SRAM cell SRAM cell.The information was given by the compose
circuits and the bit and bit of each SRAM cell is associated
The Fredkin gate used as the access transistors. The inputs to with the sense circuits in request to play out the read
the Fredkin gate are WL, previous data Fig.1: Proposed operation.In the proposed SRAM cluster, four 2-to-4
Reversible SRAM Cell The Fredkin gate used as the access decoders are utilized with empower bit to interface eight
transistors. The inputs to the Fredkin gate are WL, previous reversible SRAM cells in an exhibit.

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 International Journal of Engineering and Advanced Research Technology (IJEART)
ISSN: 2454-9290, Volume-3, Issue-6, June 2017
IV. SYSTEM ANALYSIS AND RESULTS [3] R. Keyes and R. Landauer, Minimal energy dissipation in logic, IBM
Journal of Research and Development, vol. 14, no. 2, pp. 152157,
March 1970.
Rubbish yield minimization is one of the real undertakings [4] M. Morrison, M. Lewandowski, R. Meana, and N. Ranganathan,
in the outline of the reversible circuits.In this area, trash yield, Design of static and dynamic ram arrays using a novel reversible logic
quantum cost andquantum postponement of the current gate and decoder, in Nanotechnology (IEEE-NANO), 2011 11th IEEE
Conference on, Aug 2011, pp. 417420.
SRAM cell utilizing reversible circuit plan and the proposed
[5] S. Mahammad and K. Veezhinathan, Constructing online testable cir-
SRAM cell is introduced. Table 1 demonsate the analysis of cuits using reversible logic, Instrumentation and Measurement, IEEE
SRAM Design Transactions on, vol. 59, no. 1, pp. 101109, Jan 2010.
[6] R. Feynman, Quantum mechanical computers, Foundations of
Physics, vol. 16, no. 6, pp. 507531, 1986.
[7] E. Fredkin and T. Toffoli, Conservative logic, in Collision-Based
Computing, A. Adamatzky, Ed. Springer London, 2002, pp. 4781.
[8] L. Brillouin, Science and Information Theory, Academic Press Inc., New
York, New York, 1956.
[9] R. Landauer and J. A. Swanson, Phys. Rev., 121, 1668 (1961).
[10] . K. Mendelssohn, Progress in Cyrogenics, Vol. 1, Academic Press Inc.,
New York, New York, 1959. Chapter I by D. R. Young, p. 1.
[11] . L. B. Russell, IRE Convention Record, p. 106 (1957).
Figure 1:Proposed reversible SRAM Cell [12] J. A. Swanson, IBM Journal, 4, 305 (1960).We would like to take this
opportunity to amplify two points in Swansons paper which perhaps
were not adequately stressed in the published version.
(1) The large number of particles (-100) in the optimum element are a result
V. RESULT of the small energies per particle (or cell) involved in the typical
cooperative phenomenon used in computer storage. There is no question
that information can be stored in the position of a single particle, at room
temperature, if the activation energy for its motion is sufficiently large (-
several electron volts).
(2) Swansons optimum volume is, generally, not very different from the
common sense requirement on U, namely: vt exp( - U/kT)<<l, which
would be found without the use of information theory. This indicates
that the use of redundancy and complicated coding methods does not
permit much additional information to be stored. It is obviously
preferable to eliminate these complications, since by making each
element only slightly larger than the optimum value, the element
becomes reliable enough to carry information without the use of
redundancy.
[13] R. L. Wigington, Proceedings of the IRE, 47, 516 (1959).
[14] A. W. Lo, Paper to appear in IRE Transactions on Electronic
Computers.
[15] D. Hilbert and W. Ackermann, Principles of Mathematical Logic,
Chelsea Publishing Co., New York, 1950, p. 10.

Mr. Naveen K B, Associate Professor, BGSIT BG Nagara

VI. CONCLUSION Mrs. Kavya K, PG Student, BGSIT BG Nagara
A novel SRAM cell was proposed and the cell was outlined
with Fredkin and Feynman entryways. One Fredkin door and
one Feynman entryways are utilized to outline the SRAM cell.
In this way, the
add up to quantum cost of the proposed SRAM cell is 6 which
is 71.5% lesser than the current outline of reversible SRAM
cell. The most pessimistic scenario postponement of the
proposed SRAM cell is 68.5% lesser than the current outline
of SRAM cell utilizing reversible circuit plan [4]. The circuit
was enhanced and the number of waste yields are diminished
to 1 which is 66.66% lesser than the current reversible SRAM
cell. The plan was confirmed utilizing Xilinx ISE test system
and 16 8 SRAM cluster was executed with the decoder
proposed.The reversible double substance addressable
memory (BiCAM) and ternary substance addressable memory
(TCAM) can be designedas an extension to this work.

REFERENCES
[1] R. Landauer, Irreversibility and heat generation in the computing
process, IBM Journal of Research and Development, vol. 5, no. 3,
pp.183191, July 1961.
[2] C. Bennett, Logical reversibility of computation, IBM Journal
of Research and Development, vol. 17, no. 6, pp. 525532, Nov 1973.

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