Electrical Engineering Digital Electronics Comprehensive Theory with Solved Examples and Practice Questions reR= MADE EASY Publications Corporate Office: 44-44, Kalu Sarai (Near Hauz Khas Metto Station), New Delhi-110016 E-mail infomep@madeeasyin Contact 011-45124660, 8860378007 Visit us at: www madeeasypublcations.org Digital Electronics ‘© Copyright, by MADE EASY Publications. Alltights are reserved. No part of this publication may be reproduced, stored in or introduced into a retvieval system, or transmitted in any form or by any means (electronic, mechanical, photo-copying, recording or otherwise), without the prior written permission of the above mentioned publisher of this book. First Edition: 2015 Second Edition: (Revised and Updated): 2016 © Alig ‘wen persion reserve by MADE EASY PUBLICATIONS No pr ofthis book maybe repro the blsher and any frm thou thePreface This look was motivated by the desire to further the evolution of a concise bbook on Digital Electronics. Keeping infocus the importance of this subject in GATE and ESE, we have done a proper study and therealter developed the content of the book accordingly. This edition has an expanded discussion of all relevant topics in the subject. Inkially, we compiled the perceptions of our students on their problems In GATE and ESE while dealing with the questions from this subject. We B. Singh (f.1ES) Identified their various problems lke- lack of fundamentals of the subject, difficulty in solving simple questions, shortage of a complete study package, etc. These strengthened ‘our determination to resent a comolete edition of Digital Electronics textbook. ‘The book addresses all the requirements of the students, i.e. comprehensive coverage of theory, fundamental concepts, objective type problems and conventional problems, articulated in a lucid language. The concise prosontation will help the readers grasp the concepts with clarty and apply them with ease to solve problems quickly. The book not only covers the entire syllabus of GATE and ESE, but also addresses the need of many other competitive examinations. Topics lke ‘Boolean algebra, logic gates, combinational and sequential logic circuits, registers, counters, logic families, converters and semiconductor memories’, are given full coverage in ine with our research on their importance in competitive examinations, We have put in our sincere efforts to present elaborate solutions for various problems, diferent problem solving methodology, some useful quick techniques to save time while altempting MCQs without compromising the accuracy of answers. A summary of important points to remember is added at the end of each topic, For the convenience of the readers, points to remember are specifically highlighted inthe form of a note: both in theory as well as solved examples, Atthe end of each chapter, sets of practice question are given with their keys, that wil alow the readers to evaluate their understanding of the topics and sharpen their problem solving skils Our team has made their best efforts to remove all possible errors of any kind. Nonetheless, we would highly appreciate and acknowledge if you find and share with us any printing, calculation and conceptual error. Itis impossible to thank all the individuals who helped us, but we would like to sincerely thank all the authors, ecltors and reviewers for pulting in thelr efforts to publish this book With Best Wishes B.singh CMD, MADE EASYContents Digital Electronics Chapter 1 Basics of “Mt. Digital Number Systems 2 12 Codes. 7 13. Arithmetic Operations 10 14 Signed Number Representation 3 15 OverFlow Concept 19 Student Assignment. 21 Chapter 2 Boolean Algebra & Minimization Techniques ..ssscstcnnnenntnnenenennne22 21 Logic Operations 2 22 Laws ofBoolean Algebra 23 23. Boolean Algebtic Theorems 24 24 Minimization of Boolean Functions 27 25 Representation of Boolean Functions....27 28 implicants, Prime implicants and Essential Prime implicants 37 Student Assignments. 41 Chapter 3 Logic Gates and Switching Circuits......43 21 Basic Gates. 8 32 Universal Gates 49 33. Special Purpose Gate 32 34 Realization of Logic Gates Using Universal Gates s7 Student Assignment. 1 Chapter 4 Combinational Logic Circuits................63 41 Design Procedure for Combinational Ciruit..62 42 Arithmetic Circuits ot 43° Nonarithmetic Circuit 7” 44 Hazards 108 Student Asignment. m Chapter 5 Sequential Logic Circuits 5.1 Latches and Flip-Flops. ns 5.2 Race Around Condition 126 53 Conversion of Flip-Flops 19 54 Appliations of Flip-Flops mh Student Assignments. 13 Chapter 6 Registers...rvsennnnnnnennnnnen TSS 61 ShiftRegister. 1s Student Assignment. 48 Chapter 7 COUNTELS «.....ccseescsneessneesennesennesssneeseneeeene TAS, 7.1 Asynchronous/Ripple Counters ur 72 Synchronous Counters. 152 73. Synchronous Counter Design 159 74 State Diagram and State Table 182 75 Finite tate Mode/Machine 165 Student Assignment. 167 Chapter 8 Logic Families cscs T7O 8:1 Switching Circuits a 82 Classification of Digital Logic Family oenuon 175 83. Characteristics of Digital Logic Family wn 176 84 Logic Families 181 Student Asignments. 204 Chapter 9 AID and D/A Converters .207 9.1 Digital to Analog Converter. 207 92 Analog Digital Converters 27 Student Assignment. 229 Chapter 10 Semiconductor Memories.............0.231 10.1 Memory Device, Parameters and Specifications 232 102 Memory Classification 233 Student Assignments. 244CHAPTER Counters Introduction A counter is a circuit that counts the number of occurrences of an input (in terms of positive or negative edge transitions in the case of binary input). Counter circuits are primarily constituted of flip-flops which along with the combinational elements are used for generation of control signals. The flip-flops are interconnected such that their combined state at any time is the binary equivalent of the total number of pulses that have occurred upto that time. Thus a counter is used to count pulses. Each count, a binary number is called a state of a counter. Hence, a counter counting in terms of mits (n flip-flops) has 2° different states. ‘The number of different states in counting sequence is also known as the modulus of the counter. Thus, for ‘n’ flip-flops counter will have ‘2” different states and then the counter is said to be “MOD-2" counter ‘The MOD number represents the frequency division obtained from the last flip-flop. It would be capable of counting upto (2° 1) before returning to zero state. Therefore, If M = Total number of states and n= Total number of FFs Then, Ms2" It M= 2”; Binary counter, M < 2”; Non-binary counter Depending upon the manner in which the flip-flops are triggered, GoUinters can be divided into two major categories: (Asynchronous counter (Ripple/series counter) (i) Synchronous counter (Parallel counter). ‘The comparison between synchronous and asynchronous counter is listed in Table (7.1). (©copyright MADE EASY ‘wwnmmadeeasypublications.org | Publleations146 | Electrical Engineering © Digital Electronics MADE EASY Table-7.1 Synchronous Counter Asynchronous Counter 1. All the fip-lops are triggered simulta-| 1. Different FFs are triggered with different neously with the same clock. clock. 2. Operationis aster 2. Operationis slower. 3. Anyrequired sequence canbe designed. | 3. Will operate onlyina fixed count sequence. 4, Nodecoding error occurs. 4. Decoding error occurs due tot, 5. Designing is complex as the number of | 5. Designing is easy even for more number of states increases, slates. 6._e4g-Ring counter, Johnson counter. 6._e.g. Ripple UP counter, Ripple DOWN counter. * Up/Down Counter: a counter counts in such a way that the decimal equivalent of the output increases with successive clock pulses, is called ‘UP counter’. It decreases, itis called ‘Down counter’. An Up/Down counter can also be designed which can count in any direction depending upon the control input, Application of Counters * To count the number of CLK Pulses. + To-count the number of items in industry. + Works as a “Frequency divider”. + Used in ime measurement * For distance measurement in RADAR system. + InAnalog to Digital converter (ADC). + Inmeasurement of PRI (Pulse Repetition interference). ‘Remember = In “MOD-N Counter’ if applied input frequency is then the output frequency is IN, states of combined counter is (Mx N) and counter is called “MOD-MN’ counter. MOD-MN counter Input frequency MOM 9} MON a ences ad Figure-7.1 Accertain J-K flip-flop has t,= 12ns, the largest that can constructed from cascading these FFs and still operating upto 10 MHz is Solution: Time period of clock pulse =10°"sec. 1 1OMHz Propagation delay of each FF = 12x 10°° sec Numbor of FF required = !2u. = fon Therefore, the number of FF required = 8 MoD < 2 and Modulus of counter = 2¢ = 256 . Re MADE EASY Scoprishe)MADE EASY ounters Publications. Counte 147 7.1 Asynchronous/Ripple Counters + Inaripple counter, there is no elock or source of synchronizing the pulses, however, the state change still occurs due to pulses at clock input of the flip-flops. . Here, the first flip-flop is clocked by external clock pulse and each successive flip-flop is clocked from the previous output 7.1.1 3-Bit Ripple Counter © Figure 7.2 (a) shows a S-bit binary ripple counter which consists of a series connection of complementing J-K flip-flops, with the output of each flip-flop connected to the clock pulse (CP) input of the next higher order flip-flop. + The flip-flop holding the LSB receives the incoming clock pulses. 1a ahoity, ofits, a oxi 3) 1x 3) 1-\m 3, (488) (uss) Figure-7.2(a) Logicdiagram of a3-bitripple counter Operation ‘+ Itis assumed that the flip-flops change their state on the negative going edge of clock pulse. © Note that all the flip-tiops are considered in toggled mode. + Q,will change its state in every clock pulse, + Q,will change its state when Q, will change from 1 to 0. + Q,will change its state when Q, will change from 1 to 0. * Depending upon the operation, the transition table is shown in Table 7.2. Table-7.2 Transitiontabletruth table CLK | & | & | 0 |o}o] 0 |-4 1]olo|1 2 }o]1]o 3 fo]1]4 4 |1]o]o 5 |1]o]1 6 }a]1fo ziatiati 8 0 0 0 = + Initially all FFs are set to zero. + The maximum possible state = 8 (from Oto 7) ‘+ The timing diagram of 3 bit ripple counter is shown in Figure 7.2 (b). — peppy © copyright MADE ERSY vvovmadeeesypubcatonsor)148 | flectrical Engineering © Digital Electronics MADE EASY Figure-7.2(b) © Ifthe input clock frequency is then the output frequency © Foran‘N bit ripple counter, ifthe propagation delay of each tip-top is t, then the period of cloc! is given by Tou 2N toa 1 o faux Sy and foo “Rigg * For determination of Up/Down counter: Trigger Applied | CLK givento | Access as Negative edge @ Up counter Positive edge Q Down counter Negative edge a Down counter Positive edge a Up counter + The major disadvantage of a ripple counter is the error due to the propagation delay of fip-flops i.e. t,gWhich, is known as decoding error or transient state. To overcome the decoding error in ripple counter we may use “strobe signal’ Thus, with strobe signal Toux 2 Ntpg + Ts where, T, = Delay of AND gate (used to give strobe signal) ‘+ Inthe counter discussed above all the states are used to get the output and therefore called as binary ripple counter { wormmadeeasypublications.org MADE ERSY © CopyrightMADE EASY counters | 449 7A2 EEEEZEZRE Consicer the circuit given below e mss | 2 bi Ripple > oS je cux ‘counter ana iss It 7 segment + asplay & use| abi Ripple ' Down A counter iss Enable If Enable =0; 7 segment display 11 (b=c=e= f= 1) Enable = 1; 7 segment display data according to Inputs Initially both the counter were cleared. After 78 clock pulses the data displayed on the 7 segment display is__. Solution: Atter 78 clock pulse Output of counter C, Output of counter C, 7 segment display abedefg Enable 1410001 0 = Data displayed on 7 segments ‘11" (1110), (0010), Asynchronous Inputs + Inthe clocked flip-flops discussed in previous chapters the inputs to S-R, J-K, Dand Tare called synchronous inputs because their effect on the output of the flip-flop is synchronized with the clock input. * There are most IC flip-flops available, which have one of more asynchronous inputs. These asynchronous inputs affect the flip-flop output independently from the synchronous inputs and clock input © These inputs can be used to SET the flip-flop (1) or RESET the flip-flop (0) at any instant of time regardless of the conditions at other inputs. © There are mainly two types of asynchronous inputs labelled-PRESET (PRE) and CLEAR (CLR), + Anactive HIGH level on PRESET input will set the FF and active HIGH level on CLEAR input will RESET the FF. Similarity an active LOW level on PRESET input will SET the FF and on CLEAR input will RESET the FF as shown in Figure 7.3 ser ser RESET RESET 1 ° 1 ° PRE PRE cur ctr Figure-7.3 Coma MADE EASY worn madeeasypubliationsora)150 | Electrical Engineering Digital Electronics MADE EASY ——Fatestons im ‘Aripple counter can be made to work as an up/down counter using 2: 1 MUX and a. > ae You Know @ 14, ott, | 1-4 ott, |] i. a, 24 aA y| y Mux ux cuK IS Oh | 1K, i | 14K 3, ee signal If, Control= 0; clock applied withQ —». Up counter If, Control = 1; clock applied with @ —-. Down counter: 7.1.3. Non Binary Counter + Foranon binary counter M< 2". * Figure 7.4 shows amod-10 counter or a decade counter. Here the t is 4 thus the number of used state = ve “4 sh cx |x, ay Kk fal number of fip-lops required ‘0 and the number of unused state = 6 cur Figure-7.4 Decadecounter + Inorder to design anon binary decade counter a logic gate is used which detects 10 stage from 0000 to 1001 and as soon as 1010 appears it clears all the flip-flops as shown in Figure 7.4 + Table 7.3 shows the transition table of a decade counter. Table-7.3 Truthtable ck QT aT ala@ 0} 0)0]0]| 0 1+ }o}ofo]1 2|o0|;o]1]|o 3 }olof1)4 4|ol1}olo s|o|1l|oj4 s|o|i]i}o 7Tlolafa}a a|i|ofolo 9 |1l|ofo|1 wlrlolilo . It is clear from the truth table that as soon as 1910 appears, inputs to the AND gate becomes 11 which resets the flip-flop with ‘CLR’ = 1 © The output frequency of MOD-10 counter = #10. there is no feedback present at Q, then the output frequency * When decade counter counts from 0 to 9 then itis known BCD counter. ee [womumadeeasypubliationsorg MADE ERSY ©copytoht)MADE EASY counters | 454 NOTE = Formakingnon binary counter, i CLR is present and CLK is connected with output Q, then we use AND gate, (Figure 7.4). Similarly CLR => Q=> AND Gate CLR = @ = NOR Gate CIR = Q=)NAND Gate GIR = G > ORGate Emo MOD-60 counter was needed to divide the 60-Hz line frequency down to 1 Hz. Construct an appropriate MOD-60 counter. Solution: Mop <2" 60 < 2%; s0,N=6 Hence, we need six FFs. The counter is to be cleared when it reaches the count of sixty (111100). Thus, the outputs of flip-flops C, D, Eand Fmust be connected to the NAND gate. The output of flip-flop Fwill have a frequency of 1 Hz Ey {ov ot cuk Kk) [oLK K Wo0-60 counter EEEZEZE Consider the circuit given below YoY % 2x4 Decoder s8_LsB ° J, Preset _@,|—{ Down, ao Crock unter Up/Down {up Coumar ° Cvear_ | —~ Coan Clock Assuming the initial value of counter output (Q,, Q,) as zero, the counter output for 8 clock pulses in decimal form is (a) 0, 3,2,1,0,1,2,3 © (c) 0, 1,2,3,3,2, 1,0 @ e copyright MADE ERSY wonumadeeasypublcations.org152 7.2 724 Electrical Engineering # MADE EASY ———Fubltestions Solution :(b) nitially Q ° ° Yo = AK tip-top is cleared Q,-0 Q.=1 As clock pulse is applied counter starts up counting ‘As counter reaches Q, = 1, Q, = 1 after 3 clock pulses J-K flip flop is preset => Q,=1 a » Counter starts down counting until ¥ is low and this repeats. So, Output Q, Q, in decimal form is 0,1,2,3,2, 1,0,1 Synchronous Counters The problem encountered with ripple counters are caused due to the accumulated FFs propagation delay. In other words, the FFs do not change states simultaneously in synchronism with the input pulses. These limitations can be overcome with the use of synchronous counters or parallel counters in which, all the flip-flops are triggered simultaneously by the CLIC input pulses. The maximum operating frequency for this counter will be significantly higher than that of the corresponding ripple counter, ‘The synchronous counters are classified as: () Shiftregister counters 1. Ring counter 2, Twistedrring counter/iohnson counter (i) Series carry counter (iii) Parallel cany counter Shift Register Counters One of the applications of shitt register is that they can be’ artangedto form different types of counters. Shit register counters are obtained from seria-in serial-out (SISO) shift register by providing feedback from the output of the last FF to the input ofthe first FF. ‘The most widely used shift register counters are: 4. Ring counter. 2. Twisted ring counter. Ring Counters Itis the simplest shift register counter. Itis also called “end carry counter The Figure 7.5 (a) shows the logic diagram of a four bit ring counter using DF. Its state diagram and transition table is shown in Figure 7.5 (b) and (c) respectively. —EE wwwmadeeasypublications.org MADE ERSY © copyright) PublicationsMADE EASY ounters Publications. Counte 153 3, a, 3, cuk Figure-7.5 (a) Logic diagram ofa ring counter ‘+ Itis clear from the logic diagram that the Qoutput of each state is connected to Dinputof the next state. However the output Q, of LSB FFis connected back to the input D, of MSB FF such that an array of FFsis arranged in a ring and, hence, the name ‘ing counter’ ‘+ Inthis only one bits high and is made to circulate around the register as long as clock pulses are applied. a > (©) State diagram 1000 1 0 oO 2 0 oO 4-state 3 41 0 4 oO 1 af en &D am |4 a 6 oO 0 7 4 0 8 oO 1 9 oO 0 (6) Truth table Figure-7.5 (b) and (c) * As the sequence repeats itself after four clock pulses, thus, the number of distinct states in the ring counter is equal to the number of FFs used in the counter. Therefore, with n flip-flops, there are n-states presentin ring counter. Hence, MOD-M=n © With ‘n'flip-tlops, maximum count possible in ring counter is (2°). * The timing diagram is shown in Figure 7.5 (a). Publlaations — cnn © Copyright MADE EASY wmadeeaspubistonsorg)154 | Electrical Engineering © Digital Electronics MADE EASY Figure-7.5(d) Timing diagram ofa 4-bitring counter * Thus, the number of unused states in ring counter is (2° 1). Advantages Decoding is very easy in ring counter, because there is no ald of extra circuits. Disadvantages Outputs are not symmetric. Self-Starting Ring Counter a, a a, LSe-FF CHT LTT intay at FFs are sotto 200 Figure-7.6 (a) Selfstarting ring counter ciock | @ | @ | % | & o fo ;o]o0]o 1} 1] o0]o0/]o 2}o|/1]/o0/]o0 3 | 0 | 0 | 4 | O }astates 4 }o|o}o}4 5 | 1] o0/]0/o0 6 }ol|1]o}o 7 }ol|o/]14/]o 8 | 0 | o | o | 4 {*saes 9 |1jol]olfo Figure-7.6(b) * In 4-bitring counter the used states = 4 and the unused input = 24 4 Inany counter if CLK frequency is “f" the FFs output frequency is “IN” (where N = No, of states). a { wormmadeeasypublications.org MADE ERSY © CopyrightMADE EASY counters | 155 Publications Applications of Ring Counter + Inanalogto digital converter + Instepper motors © Incontrolled signal generation such as interrupts ‘Twisted Ring Counter Johnson Counter) * The Johnsen counter is a SISO shift register obtained by providing feedback from the inverted output of the last FF to the input of the first flip-flop. + Itis also know as (Twisted ting counter (ii) Switch tailing counter (iii) Mobies counter (i) Creeping counter (») Walking counter + Figure 7.7 (a) shows the logic diagram of a 4-bit Johnson counter. It is clear that the Q output of each stage is connected to the D input of the next stage, however the oulput @ of the last stage is connected to the D input of the first stage, therefore, the name ‘twisted ring counter 4 eck Flgure-7.7 (a) Twistedting counter ‘+The state diagram and the transition table is shown in Figure 7.7 (b) and (d) respectively. Let initially all the FFs are reset. ckKTQ[@][alo@ ee 1|1]/o]o/0 2|/1]1]}o]o s}1}afajo a}afafa|a s|/o]1}i|4 e/ofo}i|4 7\/o]o}o|1 cK ©) @ Figure-7.7 (b),(c)and(d) ‘+ Itis clear from the truth table, that the sequence is repeated atter every eighth clock pulse. Thus for 'r' FFs there are 2n possible states. MOD-M=2n * The total number of unused state = (2° 2n). Publlaations — cnn © Copyright MADE EASY wmadeeaspubistonsorg)156 | flectrical Engineering © Digital Electronics MADE EASY + Innormal “Johnson counter" with‘ flip-flops and the input frequency is 'f'then the output frequency is fan, + When a counter enters into an unused state, it will persist in moving from one unused state to another and will never find its way to a used stat + Thus, counter is said to be suffered trom the problem of "LOCK OUT". This problem can be overcome by adding a Gate. + Ina‘counter ita feedback connection is used, the number of possible states will decrease. NOTE: In Johnson counter to decode each state two input AND gate or NOR gate is used. EEEEZEZE «Consider the digital circuit shown in the given figure 2, a} 3, (9, a ‘lotk Generator ‘The average propagation delay of each NAND gate in the clock generator circuit is 10 ns. Calculate the frequency of the signal at Q,, Solution: Here the clock generator is a ring oscillator circuit 1 ae ou 2Nteg N= Number of logic gates ty = Propagation delay of each logic gate ‘OMHz ux = 2x5x10n The clocked sequential circuit is a 3-bit Johnson counter foxx _ 10MH2 2x3 «6 66 MHz The square wave C, shown in figure is given to the clock input of a 4-bit binary Up/Down counter whose Up/Down input is fed with the pulse train P,, The counter is a negative edge triggered one, The counter starts with 0000 and will reach 0000 again at the SHA AR AEA a I (a) 15%" clock pulse {b) 16" clock pulse (c) 44" clock pulse (d) 48" clock pulse { wormmadeeasypublications.org MADE ERSY © Copyright |MADE EASY Counters | 157 Solution (e) Here in every P, pulse there are 3 clock pulses. For initial two clock pulses counter will work as Up counter as P, is high and for 3" clock puise it will work as down counter so in every three clock pulse it will be incremented by only 1 (2 increment and one decrement), so after 14 x 3 = 42 clock pulses counter goes to 14, After that P, goes high for two clock pulses and counter will be incremented by 2 is 14 + 2 = 16 i.e, equivalent to 0000. So atter 42 + 2 = 44 clock pulses counter will be go to 0000 again The 14-bit timer is loaded with the counter value of 07D0 H. The timer input is connected to a clock with a frequency of 800 KHz. The timer Is programmed to produce a continuous signature wave output. The frequency of the square wave output is (a) 400 KHz (b) 800 kHz (c) 400 Hz (a) 2000 kHz Solution :(¢) (O7DO)H > (0x 168 +7 x 16% + 13 X16! +0 x 169) = (2000),, 800 x 10% frequency of square wave generated Zoo = 40H Bane 12 MHz clock frequency is applied to a cascaded counter of modulus-3 counter, modulus-4 counter and modulus-5 counter. What are the lowest output frequency and the ‘overall modulus, respectively? (a) 200 kHz, 60 (b) 1 MHz, 60 (c) 3 MHz, 12 (d) 4MHz, 12 Solution:(a) In cascade the resulting mode of counter = Mx Nx 0=3%4%5 6 Lowest output frequency = 12*17 209 x 10% = 200 kt4z 3x4x6 Overall modulus = 3x 4x6 = 60 7.2.2. Synchronous Series Carry Counter © A4+bit (MOD-16) series carry counteris shown in Figure 7.8 (a). The basic principle of operation of this synchronous counter is inputs of the flip-flops are connected in such amanner that only those FFs that are supposed to toggle on a given CLK will have T= 1 teh oS) | pt Leow a, a a cLke Figure-7.8 (a) Series carry counter @ayne MADE EASY vowmmadeeasypublications.org |158 | Electrical Engineering * Digital Electronics MADE EASY © The circuit shown above is a synchronous counter. | 1. Q, toggles for every CLK pulse is applied. 2. Q, toggles when Q, = 1 and CLK pulse is applied 3. Q, toggles when Q, = 1 and Q, = 1 and CLK pulses applied 4. Q, toggles when Q, = Q, = Q, = 1 and CLK pulse is applied. * The truth table, depending upon the operation is shown in Table 7.4 Table-7.4 Truthtableforseriescamrycount this counter CLK Qs Q Qa Q 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 "1 1 0 1 1 12 1 1 ° 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 16 0 0 0 0 * _ Inorder to get synchronous down counter, @ output of each stage is connected to the input of the next stage. ‘+ Mostimportant advantage of this counter is that it reduces the ‘decoding error’ ‘+The total delay for synchronous series counter is Toux fog + (= 2) pg (AND-Gate) As the number of bit increases, the propagation delay of FFs and the propagation delay of AND gate also increases, this will increase the total delay of the circuit. Thus, in order to overcome this difficulty synchronous parallel carry counter is used For synchronous parallel carry counter. Teun ® fea * loa (AND-Gate) ‘Remember: Speed of synchronous parallel carry counter > speed of synchronous series carry counter > speed of ripple carry counter. 20ns. Compare this with f,,,, for a MOD-16 ripple counter. (ii) What has to be done to convert this counter to MOD-37? (ii) Determine f,,, for the MOD-32 parallel counter. a { wormmadeeasypublications.org MADE ERSY © copyright)MADE EASY counters | 159 Solution: () The total delay that must be allowed between input clock pulses is equal to FF t,,+ AND gate fhe THUS, Trjgg, 250 + 20 = 70ns, and so the parallel counter has . = youg = M8 MHz (parallel counter) AMOD-16 ripple counter uses four FFs f,,,~ 50ns. Thus, f., or the ripple counter is 1 4x 50ns (ii) A fifth FF must be added, since 25 = 32. The CLK input of this FF is also tied to the input pulses. Its Jand K inputs are fed by the output of a four-input AND gate whose inputs are A, B, Cand 5 MHz (ripple counter) Dd, (iii) fyaqi8 still determined as in (a) regardless of the number of FFs in the parallel counter. THUS, fg. is stil 14.3 MHz. 7.3 Synchronous Counter Design Synchronous countets for any given count sequence and modulus can be designed in the following way. + Identify the numberof flip-flops, number of inputs and number of outputs required. + Construct the state table with the help of present state, next state and excitation table of the FFs, + Prepare K-map for each flio-op input.in terms of flip-flop outputs as the input variable, obtain and minimize the logical expressions. * Connect the circuit using flip-slops and other gates corresponding to the minimized expressions. EEZEEZEADN «Design a 3-bit synchronous counter using J-K Flip-flops. ip-flops required is 3. Let the flip-flops be FF,, FF, and outputs are given below: ;, and thelr inputs and Flip-flop Input Output FF on Ko a FF, Jo 2, Fr, Joke a Presentstate | Next tte Flop puis FF, QQ lA A Bolo Ko A Ki ve Ke 00 ajo 0 1|1 x 0 x 0 x oo 1fo 1 o|x + 1 x o x 0 7 afo 1 1|1 x x 0 o x 0 1 a]1 0 olx + x 1 4 x 40 0/1 0 1|1 x 0 x x 0 to 4/1 4 olx + 4 x x 0 ti o]s 4 a]t x x 0 x 0 ta afoo ofx t+ x 1 x 4 oo 0 — — © copyright MADE EASY vwwmadeeasypublcations org)160 | flectrical Engineering © Digital Electronics MADE EASY Publlestions The count sequence and the required inputs of flip-flops are given in table. The inputs tothe flip-flops are determined by using K-MAP. 2.0, 2.2, Qo ort 10 rw or no ‘ ol o |x| x|o Ws [e da 4% 2.0, 2,0, XN! oo or tt 10 X00 otto colo }o|x)o ol x | x]o]o 1} 0 |[4 | x]| x a} x |x [4] 0 Up, 0 > Down) (a) 0, 1, 2,3, 4, 4, 3,2, 1, 1,2,3,4 (b) 0, 1,2, (©) 0,1, 2,3, 4,5, 5, 4,3, 2, 1,0,1 (d) 0,1,2,8,4,5, 4,3, 2 Solution:(d) ritialy Q = 0 and count up (@ = 1) is active so it started counting up and when it reaches to § then decoder output at pin 5 becomes 0 and preset will be active and it will set Q and it will make the counter mode down and count becomes 4, then 3 then 2 then 1 then 0, as soon as it reaches 0, decoder output at pin 0 is low and clear is active and Q goes to 0 and @ = 1 so up is active and it counts 1, 2, 80 sequence is 0, 1, 2,3, 4,5,4,3,2,1,0, 1,2 EEELALM Consider the counter circuit shown below: 1 25 a, 2 3. +74 Tap ate a ck. cur © Copyright MADE ERSY woumadeeasypublcations.org162 74 a Electrical Engineering * Digital Electronics MADE EASY (Inthe above figure, Y can be expressed as (a) Q,(Q, + Q)) {b) +22, (c) Q3(Q, + Q,) (d)_ Q,+Q,0; (i) The above circuit is a (a) Mod-8 counter (b) Mod-9 counter (c) Mod-10 counter (d) Mod-11 counter Solution: @ (a) Y= (Q,Q5)-(Q Qs) = (Q, Qs) + (Q; Qs) = 2, Q + Q Q = QQ, + Q,) Gi) (c) To reset the counter output Ymust be one Y= Q(Q,+Q,) Be] ae) a | & 1[o]1]o 1] 14} 0]}0 a}ajilo When the counter output Q, @, Q, Q, = 1010 then the output Y will give output 1 and it will be given to inverter, so itwillreset the counter and again counting wil start and itwillnot go for further combinations, So, MOD of the counter is ‘10 State Diagram and State Table . A state diagram is a pictorial representation of the relationship between the present state, the input, the next state, and the output of a sequential circuit. However, for the implementation of sequential cuit, the information contained in the state diagram is to be translated into state table. Thus, the state table is a tabular representation of the state diagram, * Consider the sequential circuit shown in Figure 7.10 (a). a a, cike Figure-7.10 (a)Logicdiagram The circuit consists of two T FFs with external input x. A set of next state equation can be writen as (Q, 43) = QT, =Q, xO, (Q,,.)2 = Qp@ T= Q, Ox Re MADE EASY a)MADE EASY counters | 163 ‘* The corresponding state table is shown Table 7.5 Table-7.5 Staretable Present State |Input| Next stato | Required excitation] Cs ee Te 0 ofofo]|o 0 0 o ofia}o]a ° 1 o tfolo]a ° 0 o a fata ° 1 1 1 o |o| 4 ° ° 0 1 ofa ]4 1 ° 1 1 1 }o}4 1 ° ° 1 1}/1}]o]o 1 1 * From the state table, the state diagram may be drawn as shown in Figure 7.10 (b). 10 GS 0101 Figure-7.10 (6) tatediogram + Here, each encircled binary number represents a particular state ofthe fipiop outputs. Each directed ine which indicates the transition between the two state's labelled with two binary numbers separated by a ‘slash’. The first number represent the input during present state and the second number represents the next state 7.4.1 State Diagram of Various Flip-Flops S-R Flip-Flop ‘The state table and state diagram of the SR flip-flop are shown in Figure 7, 11 (a), and (b) respectively. For SR flip-flop the next slate equation is Q,., = $+AO, input Present State | inp Noxt state so con Q, s] 81 Gn on ‘or 0 0 0 ° 1 0 0 ° 1 0 1 F 1 o 1 1 1 ° 1 ° 1 1 1 x (@) State Tale (2) State Dlagram Figure7.11 (a)andib) — peppy © copyright MADE EASY vwwnmadeeasypublcations org164 | Electrical Engineering © Digital Electronics MADE EASY +K Flip-Flop The state table and state diagram for JK tl flip-flop the next state equation is flop shown in Figure 7.12 (a) and (b) respectively. For JK 1 = JO, +RQ, Present State Input Next state a, yf «| em ° o | o ° ° o| 4 ° ° +} 0 1 ° +]4 1 1 1 o| o 1 oa ; oa 5 on 1 1] 0 1 4 si ° 70 (a) State Table {b) State Diagram Figure-7.12 (aland(o) D Flip-Flop The state table and state diagram for Dtiip-tlop are shown in Figure 7.13 (a) and (b) respectively. For Dilip-tlop the next state equation is ney =O Present State | Input Next state , D om n 0 ° 0 000 " ° 1 1 0 fi 1 ° ° 1 1 1 w (a) State Table (0) State Diagram Figure-7.13 (a)and(o) T Flip-Flop The state table and state diagram for T fiip-lop are shown in Figure 7.14 (a) and (b) respectively. For Tiliplop the next state equation is Q,,1=Q,@T Present State | Input | Next state @ T Om wi ° ° ° ot ° 1 1 1 ° 1 1 1 ° 76 (a) State Table (0) State Diagram Figure-7.14 (a)andib) . Re MADE EASY a)MADE EASY counters | 165 Publications 7.5 Finite State Model/Machine (© Copyright ‘The finite state machine is an abstract model that describes the synchronous sequential machine In a sequential circuit, the output depends upon the present input as well as past history and therefore it would need an infinite capacity for storing them. Since it is impossible to implement machines with infinite storage capacity, finite state machines are used. Thus finite state machines are sequential circuits whose past history can affect their fulure behaviour in only a finite number of ways, ‘That means finite state machines are machines with a fixed number of states. Every finite state machine has a finite number of memory devices. ‘The block diagram of a finite state model is shown in Figure 7.15. Here x,, x» ---x, are the inputs Vy de + -Y ate the outputs, z,, 2, --+z, are state variables and Z,, Z,--+ Z, represents the next stato. 4 4 4 Figure-7.15 Block diagram of astate model With an r-state machine, we can generate a periodic sequence of less than or equal to n-states Finite machines are of two types. The major difference between them is the way the output is generated. They are (Moore type model (i) Mealy type model Table (7.6) shows a comparison between the Moore machine and the mealy machine Table-7.6 Comparison between Mooreand Mealy model Moore Machine Mealy Machine 4. The outputs a function of present | 1. The output is a function of present state oniy. state as well as present input 2. The change in input does not affect | 2. The change in input may affect the the output ofthe circuit ‘output ofthe circuit. 3. For implementing same function, it | 3. Itrequires less number of states for requires more number of states. implementing same function 4, The designing of Moore modelis | 4, The designing of Mealy model is easy. complex. cnn MADE EASY rw madeeasypublcationsog Publlaations