CMOS 45 GHz vector modulator with gain/ networks were designed using a coplanar waveguide transmission line

phase correction through calibration constructed using the thick top metal lines.

E. Juntunen, D. Dawn, J. Laskar and J. Papapolymerou Measured results: Shown in Fig. 3 is a photo of the CMOS vector
modulator die. The die area excluding pads is 0.56 mm2. For measure-
A 45 GHz vector modulator designed in 45 nm SOI CMOS is pre- ment purposes, one phase of the differential output was terminated with
sented along with an open-loop calibration technique for gain/phase a 50 resistor on chip.
correction. The continuous 360 vector modulator consists of a
passive quadrature signal generation network followed by a Gilbert
cell modulator. The simple, open-loop calibration procedure results
in RMS gain and phase errors less than 0.5 dB and 5, respectively.
The circuit consumes 18 mW of DC power from a 1 V supply.

Introduction: There has been a tremendous amount of activity in

millimetre-wave (30300 GHz) transceiver design for wireless com-
munications. Phased arrays have been proposed as a solution to the
problems of high propagation loss and low achievable output power
from silicon technologies at millimetre-wave frequencies [1]. Linear
amplication using nonlinear components (LINC) architectures, conver-
sely can provide high-efciency linear amplication for single-element
transmitters [2]. A key building block for both topologies is a vector
modulator. Phase and amplitude accuracy are crucial for maintaining
Fig. 3 Vector modulator die photograph
array factors close to the theoretical maximum in phased array architec-
tures [3] and in LINC transmitters for providing accurate modulation.
Depending on the precision requirements of the application, cali-
This Letter presents the design of a 45 GHz vector modulator in
bration may need to be applied to correct for phase and amplitude imbal-
45 nm silicon-on-insulator (SOI) CMOS that can be employed in a
phased array transceiver or a LINC transmitter. A simple and effective ances in the 90 hybrid and amplitude imbalances in the balun and/or
Gilbert cell modulator due to mismatch [4]. The normalised, ideal differ-
calibration procedure based only upon power measurements is described
ential i and q signal voltages to drive the modulator as a function of
that results in very low RMS gain and phase errors of 0.5 dB and 5,
respectively. desired output phase, , are given by (1) and (2):
i = cos (u) (1)
Vector modulator design: A block diagram of the millimetre-wave
vector modulator can be seen in Fig. 1. Quadrature signals are generated q = sin (u) (2)
using a 90 hybrid implemented by a branchline coupler with a coplanar The calibrated differential signal voltages written in terms of the
waveguide transmission line with signal and ground paths in the thick desired output vector angles are given by (3) and (4). DC offset and
top metal. Next, vertically coupled Marchand baluns using the top amplitude imbalances are compensated for by shifting and scaling the
two thick metals are used to generate the differential signals that drive differential input swing, whereas the IQ imbalance is corrected by
the Gilbert cell modulators. Simulation results show the Marchand adding a component iqcorr to the i vector proportional to the IQ imbal-
balun and quadrature hybrid having insertion losses of 1.7 and 2.75 ance and the magnitude of the q vector, as depicted graphically in Fig. 4.
dB, respectively, at 45 GHz. This results in a magnitude error given by 1-cos(), which amounts to
an error of less than 1.52% for an IQ imbalance of 10.
passive IQ
ic = (imax iDC ) cos (u) + iDC + iqcorr
Gilbert cell
generation network modulator (3)
I+
I
qc = (qmax qDC ) sin (u) + qDC (4)
0
mm-wave in mm-wave out
90
Q+
where iqcorr = sin (c)qc , imax and qmax are the i- and q-path maximum
swings, iDC and qDC are the i- and q-path DC offsets, and is the IQ
Q
i+ i q+ q
phase modulation
imbalance.
The coefcients for (3) and (4) were determined manually through
Fig. 1 Vector modulator block diagram power-only measurements on a set of test vectors. The DC offset
terms iDC and qDC were found by varying the differential biases i and
q until perfect cancellation was achieved, resulting in a zero-vector
OUT+
OUT output. Coefcients imax and qmax were then determined by nding
40x
I+ Q+
1.1 pF 20
1 m
I Q the weaker of the I and Q vectors then scaling the other to this power
level. Next, was found by changing its value such that the 45 (I+
VG2
1.5 pF i+ i q+ q
1 k 40x1 m
245 fF 262 m
I+
I
VDD Q), 135 (I + Q), 225 (IQ), and 315 (IQ) vectors had the
124 m
130 m same power levels as illustrated by Fig. 5.
VG2
20 m
OUT+
OUT
58 m
VG2 140 m iqcorr
Q+
Q+ Q+
VDD
Q i+ i q+ q

VG2

Fig. 2 Vector modulator active Gilbert cell core

I+
Vector rotation is performed by a double-balanced Gilbert cell core,
wherein the differential quadrature signals (I , Q ) generated by the
passive network are weighted by the differential inputs to the tail tran- Fig. 4 IQ imbalance correction illustrated graphically
sistors (i , q ) and summed. The circuit schematic of the Gilbert
cell modulator is seen in Fig. 2. The series resistors at the gates of the MATLAB code containing the calibration equations was used to drive
tail transistors serve as ESD protection. The limitation this places on the modulator via external DACs. Shown in Fig. 6 are the measured
the baseband bandwidth of the circuit is more than an order of magni- RMS gain and phase errors against frequency as dened in [5]. In
tude greater than the capability of the measurement setup. Matching both plots, RMS errors are given for the uncalibrated vector modulator,

ELECTRONICS LETTERS 14th February 2013 Vol. 49 No. 4

as well as after it had been calibrated at 45 GHz. For the frequency range Conclusion: A 45 GHz vector modulator designed in 45-nm SOI
of 4248 GHz, the RMS gain error is < 1.3 dB for the uncalibrated case CMOS was presented along with a gain and phase balance calibration
and < 0.5 dB after calibration. For the same frequency range the RMS procedure. The simple, open-loop calibration procedure resulted in
phase error is < 10 uncalibrated and < 5 calibrated. RMS gain and phase errors less than 0.5 dB and 5, respectively.

Acknowledgment: This work was supported by the DARPA/MTO

Leading Edge Access Program.
Q+ Q+
135 45
135 45
I+ I+
The Institution of Engineering and Technology 2013
I I 15 November 2012
225 315 225 315 doi: 10.1049/el.2012.4001
Q Q One or more of the Figures in this Letter are available in colour online.
E. Juntunen (Peraso Technologies, Inc., Toronto, ON, Canada)
E-mail: eric@perasotech.com
Fig. 5 Using relative magnitudes of 45, 135, 225, and 315 test vectors to
correct IQ imbalance D. Dawn (Department of Electrical and Computer Engineering, North
Dakota State University, Fargo, ND, USA)
a Uncalibrated
b Calibrated J. Laskar (InSite Partners, Cuperino, CA, USA)
J. Papapolymerou (Department of Electrical and Computer
RMS gain error, uncalibrated RMS gain error, calibrated
Engineering, Georgia Institute of Technology, Atlanta, GA, USA)
RMS phase error, uncalibrated RMS phase error, calibrated

1.4 14 References
1.2 12
1 Doan, C.H., Emami, S., Sobel, D.A., Niknejad, A.M., and Brodersen, R.
RMS phase error, deg
RMS gain error, dB

1.0 10
W.: Design considerations for 60 GHz CMOS radios, IEEE Commun.
0.8 8 Mag., 2004, 42, (12), pp. 132140
0.6 6 2 Cox, D.: Linear amplication with nonlinear components, IEEE Trans.
0.4 4
Commun., 22, (12), pp. 19421945
3 Natarajan, A., Reynolds, S.K., Tsai, M.D., Nicolson, S.T., Zhan, J.-H.C.,
0.2 2
Kam, D.G., Liu, D., Huang, Y.-L.O., Valdes-Garcia, A., and Floyd, B.
0
40 42 44 46 48 58
0
A.: A fully-integrated 16-element phased-array receiver in SiGe
frequency, GHz BiCMOS for 60-GHz communications, Solid-State Circuits, IEEE
Journal of, 2011, 46, (5), pp. 10591075
Fig. 6 RMS gain and phase error, calibrated against uncalibrated 4 Zhang, X., Larson, L.E., Asbeck, P.M., and Nanawa, P.: Gain/phase
imbalance-minimization techniques for LINC transmitters, IEEE
Trans. Microw. Theory Tech., 2001, 49, (12), pp. 25072516
The vector modulator is capable of a continuous 360 phase rotation, 5 Vadivelu, P.B., Sen, P., Sarkar, S., Dawn, D., Pinel, S., and Laskar, J.:
has an average gain of 13.7 dB and consumes 18 mW of DC power Integrated CMOS mm-wave phase shifters for single chip portable
from a 1V supply. Table 1 compares this work to other CMOS- radar. IEEE MTT-S Int. Microwave Symp. Dig., Boston, MA, USA,
based 360 phase shifters, showing low power consumption and very June 2009, pp. 565568
low RMS gain and phase errors following simple open-loop calibration. 6 Wu, J.-C., Kao, J.-C., Kuo, J.-J., Kao, K.-Y., and Lin, K.-Y.: A 60-GHz
single-ended-to-differential vector sum phase shifter in CMOS for
phased-array receiver. IEEE MTT-S Int. Microwave Symp. Dig.,
Table 1: 360 CMOS vector modulator performance comparison Baltimore, MD, USA, June 2011, pp. 14
Reference [5] [6] This work
Frequency (GHz) 5056 5764 4248
Phase resolution () Continuous 22.5 Continuous
Average gain (dB) 13.5 5.4 13.7
RMS gain error (dB) < 1.76 < 1.2 < 1.3, < 0.5*
RMS phase error () < 21 < 10.5 < 10, < 5*
Area (mm2) 0.17 0.25 0.56
DC power (mW) 6 34 18
CMOS technology 90 nm 90 nm 45 nm SOI
*calibrated at 45 GHz

ELECTRONICS LETTERS 14th February 2013 Vol. 49 No. 4