PPPPP1
module ele( r_floor, r_door,r_callfloor, r_finish, o_floor, o_door, o_elevator
);
input o_door, r_callfloor;
output reg [3:0]r_floor;
output reg r_door, r_finish;
input [3:0]o_floor;
output reg [1:0] o_elevator;
always @ (o_door,o_floor,r_callfloor)
begin
if (r_finish !=1)
begin
if (o_floor == 1 && o_door == 1) //stage 0
begin
r_floor = 4'b0001;
r_door = 0;
o_elevator = 0;
r_finish = 1;
end
else if (o_floor == 1 && o_door == 0 && r_callfloor == 1) //stage 1
begin
r_floor = 4'b0001;
r_door = 1;
o_elevator = 0;
r_finish = 0;
end
else if (o_floor == 1 && o_door == 0 && r_callfloor != 1) //stage 2
begin
r_floor = 4'b0010;
r_door = 0;
o_elevator = 2'b01;
r_finish = 0;
end
else if (o_floor == 2 && o_door == 0 && r_callfloor == 1) //stage 3
begin
r_floor = 4'b0001;
r_door = 0;
o_elevator = 2'b10;
r_finish = 0;
end
else if (o_floor == 2 && o_door == 1) //stage 4
begin
r_floor = 4'b0010;
r_door = 0;
o_elevator = 0;
r_finish = 1;
end
end
end
endmodule
P22222
module step_motor(
input clk,
input rst,
input dir,
input en,
output [3:0] signal_out
);
// Wire to connect the clock signal
// that controls the speed that the motor
// steps from the clock divider to the
// state machine.
wire new_clk;
// Clock Divider to take the on-board clock
// to the desired frequency.
clock_div clock_Div(
.clk(clk),
.rst(rst),
.new_clk(new_clk)
);
// The state machine that controls which
// signal on the stepper motor is high.
step_driver control(
.rst(rst),
.dir(dir),
.clk(new_clk),
.en(en),
.signal(signal_out)
);
endmodule
module step_driver(
input rst,
input dir,
input clk,
input en,
output reg [3:0] signal
);
// local parameters that hold the values of
// each of the states. This way the states
// can be referenced by name.
localparam sig4 = 3'b001;
localparam sig3 = 3'b011;
localparam sig2 = 3'b010;
localparam sig1 = 3'b110;
localparam sig0 = 3'b000;
// register values to hold the values
// of the present and next states.
reg [2:0] present_state, next_state;
// run when the present state, direction
// or enable signals change.
always @ (present_state, dir, en)
begin
// Based on the present state
// do something.
case(present_state)
// If the state is sig4, the state where
// the fourth signal is held high.
sig4:
begin
// If direction is 0 and enable is high
// the next state is sig3. If direction
// is high and enable is high
// next state is sig1. If enable is low
// next state is sig0.
if (dir == 1'b0 && en == 1'b1)
next_state = sig3;
else if (dir == 1'b1 && en == 1'b1)
next_state = sig1;
else
next_state = sig0;
end
sig3:
begin
// If direction is 0 and enable is high
// the next state is sig2. If direction
// is high and enable is high
// next state is sig4. If enable is low
// next state is sig0.
if (dir == 1'b0&& en == 1'b1)
next_state = sig2;
else if (dir == 1'b1 && en == 1'b1)
next_state = sig4;
else
next_state = sig0;
end
sig2:
begin
// If direction is 0 and enable is high
// the next state is sig1. If direction
// is high and enable is high
// next state is sig3. If enable is low
// next state is sig0.
if (dir == 1'b0&& en == 1'b1)
next_state = sig1;
else if (dir == 1'b1 && en == 1'b1)
next_state = sig3;
else
next_state = sig0;
end
sig1:
begin
// If direction is 0 and enable is high
// the next state is sig4. If direction
// is high and enable is high
// next state is sig2. If enable is low
// next state is sig0.
if (dir == 1'b0&& en == 1'b1)
next_state = sig4;
else if (dir == 1'b1 && en == 1'b1)
next_state = sig2;
else
next_state = sig0;
end
sig0:
begin
// If enable is high
// the next state is sig1.
// If enable is low
// next state is sig0.
if (en == 1'b1)
next_state = sig1;
else
next_state = sig0;
end
default:
next_state = sig0;
endcase
end
// State register that passes the next
// state value to the present state
// on the positive edge of clock
// or reset.
always @ (posedge clk, posedge rst)
begin
if (rst == 1'b1)
present_state = sig0;
else
present_state = next_state;
end
// Output Logic
// Depending on the state
// output signal has a different
// value.
always @ (posedge clk)
begin
if (present_state == sig4)
signal = 4'b1000;
else if (present_state == sig3)
signal = 4'b0100;
else if (present_state == sig2)
signal = 4'b0010;
else if (present_state == sig1)
signal = 4'b0001;
else
signal = 4'b0000;
end
endmodule
module clock_div(
input clk,
input rst,
output reg new_clk
);
// The constant that defines the clock speed.
// Since the system clock is 100MHZ,
// define_speed = 100MHz/(2*desired_clock_frequency)
localparam define_speed = 26'd5000000;
// Count value that counts to define_speed
reg [25:0] count;
// Run on the positive edge of the clk and rst signals
always @ (posedge(clk),posedge(rst))
begin
// When rst is high set count and new_clk to 0
if (rst == 1'b1)
begin
count = 26'b0;
new_clk = 1'b0;
end
// When the count has reached the constant
// reset count and toggle the output clock
else if (count == define_speed)
begin
count = 26'b0;
new_clk = ~new_clk;
end
// increment the clock and keep the output clock
// the same when the constant hasn't been reached
else
begin
count = count + 1'b1;
new_clk = new_clk;
end
end
endmodule
#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = "p80" ;
NET "dir" LOC = "p52" ;
NET "en" LOC = "p51" ;
NET "rst" LOC = "p180" ;
NET "signal_out<0>" LOC = "p131" ;
NET "signal_out<1>" LOC = "p125" ;
NET "signal_out<2>" LOC = "p124" ;
NET "signal_out<3>" LOC = "p123" ;
