Fabrication of MOSFET’s

ARPAN DESAI
 Contents

 Lithography/Patterning
 Etching
 Oxide Growth/Oxide Deposition
 Ion Implantation
 Device Isolation Techniques
 Fabrication of nMOS Transistor
 Fabrication of CMOS
 Lithography/Patterning

 An IC consists of several layers of

material that are manufactured
in successive steps.
 Lithography is used to
selectively process the layers,
where the 2-D mask geometry is
copied on the surface.

•The surface of the wafer is coated with a photosensitive

material, the photoresist. The mask pattern is developed on
the photoresist, with UV light exposure.
•Depending on the type of the photoresist (negative or
positive),the exposed or unexposed parts of the photoresist
change their property and become resistant to certain types of
solvents.
 Lithography/Patterning
Positive and Negative Photoresist
Etching

 Etching is a common
process to pattern
material on the surface.

 Once the desired shape

is patterned with
photoresist, the
unprotected areas are
etched away, using wet
or dry etch techniques.
Oxidation

 Oxidation of the silicon

surface creates a SiO2 layer
that acts as an insulator.

 Oxide layers are also used

to isolate metal
interconnections.
Ion Implantation

 Ion implantation is
used to add doping
materials to change the
electrical
characteristics of
silicon locally.
 The dopant ions
penetrate the surface,
with a penetration
depth that is
proportional to their
kinetic energy.
Fabrication of nMOS
Fabrication of nMOS
 Fabrication of nMOS
Functions of Various Layers

 Thin oxide layer:

- It forms the gate oxide of the MOS transistor.
- Dielectric layer that separates gate terminal of
MOSFET from source and drain region as well
as the underlying conductive channel that
connects source and drain when the transistor
is turned on.
 Polysilicon Layer:
- Used both as gate electrode material and also
as an interconnect medium.
 Fabrication of nMOS
SELF ALIGNED PROCESS

 Polysilicon gate, which is patterned before

doping defines:
i.) precise location of the channel region
ii.)location of source and drain regions

Since, this procedure allows very precise

positioning of two regions relative to the gate, it
is called as Self Aligned Process.
Fabrication of nMOS
Fabrication of nMOS
 Device Isolation Techniques

 MOS transistors must be electrically isolated from each

other in order to:
 prevent unwanted conduction paths between
devices
 avoid creation of inversion layers outside the
channel regions
 reduce the leakage currents

 Each device is created in dedicated regions - active areas

 Each active area is surrounded by a field oxide barrier

using few techniques:
i.) Etched field-oxide isolation
ii.) LOCOS (Local Oxidation of Silicon)
 Device Isolation Techniques
Etched field-oxide isolation

1) Grow a field oxide over the entire surface of the chip

2) Pattern the oxide and define active areas

Drawbacks:
 large oxide steps at the boundaries between active areas and field
regions.
 cracking of polysilicon/metal and subsequent deposited layers

 To prevent this, most manufacturers prefer isolation techniques that

partially recess the field oxide into the silicon surface.
 Device Isolation Techniques
Local Oxidation of Silicon (LOCOS)

 Process flow
1) Grow a thin pad oxide (SiO2) on the silicon surface.
Thin pad oxide - protect the silicon surface from
stress caused by nitride
2) Define active area : deposition and patterning a
silicon nitride (Si3N4) layer
 Device Isolation Techniques
Local Oxidation of Silicon (LOCOS)
3) Channel stop implant: p-type regions that surround the
transistors
 To prevent the formation of any unwanted channels
between two neighboring N+ diffusion regions.

4) Grow a thick field oxide

•Field oxide is partially recessed into the surface (oxidation consume

some of the silicon)
 Device Isolation Techniques
Local Oxidation of Silicon (LOCOS)

•Field oxides forms a lateral extension under the nitride layer –

bird’s beak region. Responsible for reduction in active areas.
• Bird’s beak region limits device scaling and device density in VLSI
circuits!

5) Etch the nitride layer and the thin oxide pad layer
 CMOS Fabrication Process:

 CMOS fabrication technology requires

that both n-channel (nMOS) and p- VDD
channel (pMOS) transistors be built on
the same chip substrate.
 To accommodate both nMOS and A Y
pMOS devices, special regions must be
created in which the semiconductor
type is opposite to the substrate type. GND
These regions are called wells of tubs.
 A p-well is created in an n-type CMOS Inverter
substrate or, alternatively , an n-well
is created in a p-type substrate.
CMOS Fabrication Process
CMOS Fabrication Process
Detailed Mask Views
CMOS Fabrication Process
CMOS Fabrication Process
n Well
CMOS Fabrication Process
Polysilicon
CMOS Fabrication Process
Polysilicon Patterning
CMOS Fabrication Process
Self Aligned Process
CMOS Fabrication Process
N Diffusion
CMOS Fabrication Process
N Diffusion Continued..
CMOS Fabrication Process
P Diffusion
CMOS Fabrication Process
Contacts
CMOS Fabrication Process
Metallization
CMOS Fabrication Process
CMOS
Fabrication Steps
Fabrication Steps
THANK YOU
 Review - CMOS Mask Layers
 Determine placement of
layout objects
 Color coding specifies
layers
 Layout objects:
 Rectangles
 Polygons
 Arbitrary shapes
 Grid types
 Absolute (“micron”)
n well
 Scaleable (“lambda”) P substrate
wafer
 Layout Design Rules
 Layout or Design Rules:

 Design rules specify geometric constraints on the layout artwork.

 Specify minimum allowable line widths.
 Provide a communication channel between the IC designer and the
fabrication process engineer.

 Objective:
 To obtain a circuit with optimum yield.
 To minimize the area of the circuit.
 To provide long term reliability of the circuit.

 Two approaches for describing design rules:

Lambda rule
Micron Rule
 Lambda rule

 Every distance in layout rules is specified by lambda

 Given a process, lambda is set to a specific value.
 Process technology is defined using minimum line width.
0.25um technology means minimum line width is
0.25um.
 Lambda=minimum line width/2.

 For a 0.25um process, lambda=0.125um

 In practice, scaling is often not linear.

 Industry usually uses micron rule and lambda rule is used
only for prediction/estimation of the impact of technology
scaling to a design.
Layout Design Rules
 Micron Rule

 Minimum feature sizes and spacing in micro meter units

(normal spec in industry)

 Micron rules can result in as much as a 50% size

reduction over lambda rules.
 Normal style for industry.
 Pro: Allow taking full advantage of technology
 Con: Scaling and Porting becomes more complicated
 Design Rule Entities

1. Layer Representations
– Substrates and/or Wells
– Diffusion Regions (Active areas)
• Select regions: For contacts to substrate or well
– Polysilicon Layers
– Metal Interconnects
• Contact: Metal to active
• Via: Metal to metal
2. Intralayer Constraints
3. Interlayer Constraints
MOSIS (MOS Implementation System) Layout Design
Rules
MOSIS (MOS Implementation System) Layout Design
Rules

Rule Number Description λ Rule

Active Area rules
R1 Minimum active area width 3λ

R2 Minimum active area spacing 3λ

Polysilicon Rules
R3 Minimum poly width 2λ
R4 Minimum poly spacing 2λ
R5 Minimum gate extension of 2λ
poly over active
R6 Minimum poly active edge 1λ
spacing (poly outside active
area)
R7 Minimum poly active edge 3λ
spacing (poly inside active
area)
MOSIS (MOS Implementation System) Layout Design Rules

Rule Number Description λ Rule

Metal Rules
R8 Minimum metal width 3λ
R9 Minimum metal spacing 3λ
Contact Rules
R10 Poly contact size 2λ
R11 Minimum poly contact 2λ
spacing
R12 Minimum poly contact to 1λ
poly edge spacing
R13 Minimum poly contact to 1λ
metal edge spacing
R14 Minimum poly contact to 3λ
active edge spacing
MOSIS (MOS Implementation System) Layout Design
Rules

Rule Number Description λ Rule

R15 Active contact size 2λ
R16 Minimum active contact 2λ
spacing (on the same
active region)
R17 Minimum active contact 1λ
to active edge spacing
R18 Minimum active contact 1λ
to metal edge spacing
R19 Minimum active contact 3λ
to poly edge spacing
R20 Minimum active contact 6λ
spacing (on different
active region)
Layout rules for a minimum size MOSFET (CMOS
Inverter Layout Design)

Minimum overall length of active area = (minimum polysilicon width) + 2 x

(minimum poly to contact spacing) + 2 x (minimum contact size) + 2 x
(minimum spacing from contact to active area edge)
Separation between nMOS and pMOS transistor of
CMOS inverter
Complete mask layout of the CMOS inverter

VDD

A Y

GND