A 1.

2 pm CMOS Implementation of a Low-Power

900-MHz Mobile Radio Frequency Synthesizer

Manop Thamsirianunt Tadeusz A. Kwasniewski"

MITEL Semiconductor, Kanata, Ontario, Canada
*Department of Electronics, Carleton University, Ottawa, Ontario, Canada

Abstract Low-Frequency Parts ! High-Frequency Parts

(CMOS) j(GaAs, Bipolar Traditionally)
A single-chip, low-power all CMOS PLL frequency I

synthesizer for digital mobile radio communication systems .c

I
is presented. The design of PLL components: VCO, dual- Dual-Modulus
Prescalar 1
modulus prescaler and phase-frequency detector are
discussed. Novel circuit techniques and design methodology
allow GHz frequency range operation, and result in good Reference
Frequency
phase noise performance. The measured results of a Fref
monolithic 1.2 j m CMOS PLL implementation indicate a Phase Loop Filter vco
frequency range of 800 to 900 MHz with -94 dBc/Hz phase Detector
noise at a 1-MHz carrier offset, and a power consumption of Fig. I. Spica1 building blocks for a modem RF PLL frequency synthesizer
18 mW at 5 volts.
dead-zone phase-frequency detector is presented. The VCO.
I. Introduction a ring oscillator structure, is based upon the operation of
transistor-only-parasitic-capacitors, with performance and
The rapid growth in demand for digital mobile radio and characteristics evaluated through simulation and post-
ponable telephones has been met through steady reductions fabrication measurements. It has been recently shown that
in cost, terminal size, and power consumption. Many of the speed and phase noise can be simultaneously optimized in a
recently reported implementations of frequency synthesizers non-contradicting manner [4]. The novel CMOS circuit
use a mixture of high-speed semiconductor technologies, as techniques allow achievement of a higher operating
shown in Fig. 1. To date, the voltage-controlled oscillator frequency imd lower power consumption for both VCO and
(VCO) and the dual-modulus divider are implemented in frequency divider [2] than previously reported for any
either bipolar or GaAs Mesfet technologies, while most of frequency synthesizer. The synthesizer chip, excluding loop
the low-frequency digital circuits are implemented in low- filter, was fabricated with a 1.2 pm 5-V standard CMOS
power high-density CMOS technology. Recently, a CMOS technology The VCO shows a phase noise performance
frequency divider was reported which exhibits an operating comparable to known bipolar on-chip VCO designs [5], [6].
frequency to a few gigahertz [ 11, [2], [3], yet there has been 171. A total power consumption below 18 mW was achieved
no report to date on the use of on-chip GHz-range CMOS for the CMOS components of the 900-MHz synthesizer. The
VCOs in mobile radio applications. synthesized output signal conforms with the phase noise
A monolithic CMOS frequency synthesizer with transmission standard requirements for an EIA 30-kHz
performance comparable to that of a discrete component channel spacing cellular telephone system[8].
counterpart poses a great design challenge. The limiting
11. Circuit Description
factor of CMOS circuits for the application considered is
their maximum operating frequency, and therefore circuits A. Voltage Controlled Oscillator (VCO)
must be optimized for speed. As well, the design topology
for a CMOS VCO has to account for performing in the noisy Placing the highest priority on speed implies that the CMOS
digital environment. To successfully integrate an all CMOS oscillator must be constructed using the simplest structures.
PLL on a single chip, special design techniques that such as an odd-number inverter ring oscillator based upon an
minimize noise and maximize speed must be developed. RC relaxation oscillator, as shown in Fig. 2. Each inverter in
this ring can be modelled by a Schmitt trigger and its
In this paper, a high-speed CMOS PLL synthesizer consisting
associated timing components R I , R2 and C,, that form an
of a 900-MHz VCO, a 1.4-GHz frequency divider and a no-

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 RC relaxation oscillator. lnverter ring oscillators consist of VCO along the boundary of the saturated delay cell can be
timing elements R , , R2 and C1 that can be circuit parasitics, utilized. Fig. 3 shows a simplified version of the proposed
and therefore result in frequency of oscillation that can be three-stage-ring oscillator employing a single-stage-inverter
extremely high. delay cell.
Inverter ring oscillators have an inherent drawback. The
frequency stability is dependent on both temperature and Area where short-channel effects
Id c~ be used for VCO application
power supply variations. Process variations can also
contribute to a shift of the center frequency. For a well
designed VCO these effects can be corrected by the feedback
action of a PLL. As well, the PLL suppresses phase noise
within the loop bandwidth. The ring oscillator VCO phase
noise outside the loop bandwidth is not suppressed and its
reduction is therefore a major design challenge. One of the f
solutions to this problem is to use the fastest switching device Fig. 3. Simplified three-stage modified ring oscillator.
possible to reduce susceptibility to noise induced voltage
uncertainty across the parasitic timing capacitor [9]. B. Dual-Modulus Frequency Divider
p vcc ,.,-.-----' A high-speed 1.2pm CMOS 15/16 frequency divider
proposed in [2] was used as an integral part of the monolithic
CMOS synthesizer. The design was well suited for a high-
speed, low-power requirement. Figure 4 shows the
functional block diagram of the divider. It consists of a
RC relaxation oscillator Parasitic-based ring oscillator divide-by-3-or-4 synchronous counter as the first (high
Fig. 2. Generalized ring oscillator. frequency) stage followed by a divide-by-4 asynchronous
counter as the second (low frequency) stage. By employing a
Unlike most bipolar emitter coupled multivibrators, whose level-triggered differential-logic latch, a maximum speed of
low phase noise levels are achieved at the expense of large 1.4 GHz was achieved.
timing capacitance and high biasing current [6],[7], the new
VCO introduced in this work is based upon a modified three-
stage dynamic inverter ring oscillator.
The oscillator, of Fig. 3, consists of a delay cell where
frequency control is achieved by directly controlling the
current through a series transistor of one inverter stage. The
two remaining inverters are connected to form a closed loop
ring. The circuit contains the least number of components
required for a functional relaxation oscillator.
The unique frequency control mechanism of the oscillator is
Fig. 4. Functional block diagram of 15116 frequency divider [2].
the use of short-channel effects (gate-length less than 3p.m) of
controlling transistor to modulate the delay. This scheme C. Phase-Frequency Detector and Loop Filter
allows a gradual monotonic increase in the current of
transistor Mnl into the saturation region. Therefore, using the Although conventional tri-state CMOS phase-frequency
short-channel property of a MOSFET to control the delay detectors (PFD) are the most popular for monolithic PLL
results in two different delay regions. one region where a designs, the existence of a phase distortion zone or "dead
MOSFET is in linear operation and another where it is in the zone" can lead to PLL spurious noise problems, degrading
saturation mode. In the linear region, the delay rate of the overall performance of the synthesized signal.
change is definitely higher than at the boundary of the A phase detector structure which mitigates this problem is
saturation region. shown in Fig. 5. The configuration is based upon an extended
The frequency of oscillation for a ring oscillator is a function range exclusive OR (XOR) with a frequency discriminating
of the delay, and therefore its voltage-to-frequency (V/F) circuit [lo].
characteristic can be expected to have a similar transfer This structure delivers a 220' detection range for 50-MHz
characteristic. Most mobile radio frequency bands are limited operation and eliminates the dead zone by moving it to the
to a few tens of megahertz, therefore the operation of the ends of the detection range. When incorporated in a PLL

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 were laid out symmetrically to achieve a 50% duty cycle

-
output, thereby decreasing output harmonics and jitter.
Fref tput
Transistor sizing was carefully optimized through a series of
HSpice extracted layout simulations. Power and ground lines
were laid out as 2Op-n wide metal lines. Star-ground
Fvco techniques were also employed to prevent ground loops and
power rail ripples, resulting in lower current spikes and
Fig. 5 . Phase-frequency detector with no dead zone. ground bounce which could potentially lead to increased
VCO phase noise. The phase-frequency detector was
synthesizer, this results in the phase detector operating in the
implemented using standard cells because the circuit operates
linear region for the lock condition.
at much lower frequencies than the VCO and the divider.
For the best possible noise performance, a differential
Finally, buried ground rings were placed around the VCO
structure was employed. Differential operation of the phase
circuit to reduce noise coupling from adjacent circuits. On-
detector can be accomplished by replicating the single ended
chip capacitors of 4pF were placed between Vdd and ground
circuit and cross-coupling the two inputs. In this manner, a
lines, on unused space, to decouple high frequency noise on
balanced PLL loop filter is required, as shown in Fig. 6 .
the power supply.
The crucial benefit of having a balanced structure is that the
amount of common mode jitter in the zero crossings at the VI. Experimental Results
PFD output due to substrate noise will be cancelled out
The chip components, including the VCO, the 15/16 moduluh
though the balanced loop filter. As a result, the structure
prescaler and the fully differential PFD were tested to
provides high immunity to noise coupled from digital
characteriz,e performance and functionality of the fabricated
circuitry.
chip. This section presents experimental setups and measured
The loop filter was chosen as an off-chip implementation results performed for the monolithic circuit. A simple test bed
allowing flexibility of loop gain and pole frequency selection. constructed from a printed circuit board and other discrete
components was used to test the synthesizer (see Fig. 7). All
measurements were performed on the bonded IC package.

(a) Fully differential PFD (b) Second-order loop filter

Fig. 6. Fully balanced configuration of phase detector and loop filter.

111. Circuit Implementation

The circuits were laid out using a 1 . 2 double-poly
~ double-
metal N-well CMOS technology. In this section, layout
related design considerations associated with speed Fig. 7. Single-chip implementation and test setup.
improvement, noise and circuit partitioning for the proposed Figure 8 shows the plots of the V/F characteristics for both
VCO, frequency divider and PFD are presented. simulated and measured results. The operating frequency
For circuits to operate at frequencies close to those of their range of the VCO was measured at 386-926 MHz for an input
pre-layout simulation results, standard cells had to be of 1.1-5.0 volts. This appears faster than simulation results by
avoided. Instead, custom designs were created for the VCO, 16%. The phase noise, measured using the HP 3048A phase
incorporating several optimization techniques. noise measurement system, indicated VCO noise levels of -
In order to minimize the parasitic capacitances, the core VCO 83 dBc/Hz,at 100 kHz offset from a 900-MHz carrier.
and frequency divider layouts were made as compact as The closed loop PLL synthesizer 850-MHz spectral output is
possible, and all interconnections were made using metal shown in Fig. 9. The PLL operated in a locked condition from
layers. All transistors employed minimum-design features 800.6-898.8 MHz for a 16 and 15 divide ratio respectively.
except for the transistor widths. The polysilicon layer was The two peaks at 200 kHz offset indicate the loop bandwidth
used exclusively for transistor gates, and all transistors had a of the PLL,. Table 1 summarizes the performance parameters
1 . 2 gate
~ length. All p and n transistors of the VCO circuit of the PLL. components in this design.

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 carrier offset (-94.0dBdHz at 1 MHz offset). With these
’ ’ -7kHz
greater levels of integration achieved, a CMOS
implementation of a PLL frequency synthesizer should
contribute to more widespread use of wireless
, 0 ‘3.0 0 0 0

communications in mass-consumer products.

........... .. Simulated

Fig. 10. Die photograph of PLL components.

VI. Acknowledgements
The authors would like to thank the assistance of Canadian
Microelectronics Corporation (CMC) for fabrication suppon.
Also, the support of the Canadian International Development
Agency (CIDA), the Telecommunication Research Institute
of Ontario (TRIO) and Micronet are also gratefully
acknowledged.

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