Phase Locked Loop
AIM: Design and Implementation of a Phase Locked Loop (PLL) on 180 nm CMOS
Technology
THEORY:
A Phase Locked Loop (PLL) is a closed-loop feedback control system that generates a signal whose
phase is related to the phase of a reference signal. It is widely used in frequency synthesis,
clock generation, demodulation, and data recovery applications. The basic idea is to align the
output phase and frequency of an oscillator with a given reference through a control
mechanism.
The main components of a PLL include:
• Phase Detector (PD) or Phase Frequency Detector (PFD)
• Low-Pass Filter (LPF)
• Voltage Controlled Oscillator (VCO)
Introduction Phase Locked Loops (PLLs) are critical building blocks in modern System-on-
Chip (SoC) applications, generating on-chip clocks and performing frequency synthesis,
modulation/demodulation, and jitter reduction. The demand for high-speed communication
systems motivates the design of PLLs that can provide stable outputs in the GHz range. This
project implements a third-order PLL on a 180 nm CMOS technology node using the Cadence
design environment. Key performance targets include output frequency >1 GHz, low power
consumption, and robust phase lock characteristics.
low-pass filter:
A low-pass filter is an essential circuit in signal processing that allows signals with a frequency
lower than a selected cutoff frequency (fc) to pass through while attenuating higher-frequency
components. These filters are widely used in audio electronics, communication systems, and
instrumentation to eliminate high-frequency noise or extract useful low-frequency signals.
1
where cutoff frequency (fc) =
2𝜋√(𝑅1𝑅2𝐶1𝐶2)
if R1=R2 and C1=C2 then
1
fc =
2𝜋𝑅𝐶
Fig.1 Low pass filter Circuit
Schematic of Low Pass filter:
Fig.2 Schematic of Low Pass Filter
Parameters:
S.no. Component name Parameter Value
1. Resistance resistance 706.7 Ω
2. Capacitance capacitance 160 pF
3. Current source DC Current 30µA
4. Supply voltage DC Voltage 2.5V
5. AC signal AC magnitude 1V
Table 1. Parameter of different components in LPF
Fig.3 Schematic of OPAMP
S.no. Component Name Parameter Value
1. NMOS W/L 0.42/0.18
2. PMOS W/L 0.42/0.18
Table 2. Parameter of different components in OPAMP
Observations:
Fig.4 AC analysis of low pass filter.
Cutoff Frequency, fc=1MHz
Power Consumption,P=1.06mW
Advantages of Low Pass Filters
1. Noise Reduction: Filters out high-frequency noise in audio and communication
systems.
2. Signal Smoothing: Helps in smoothing signals by removing high-frequency
fluctuations.
3. Simplicity: Simple design, especially for passive filters.
4. Cost-effective: Low component cost for basic filtering needs.
5. Versatile Use: Can be adapted for both analog and digital systems.
Voltage-Controlled Oscillator:
A Voltage-Controlled Oscillator (VCO) is an essential electronic component that generates an
oscillating signal, typically in the form of a sine wave, square wave, or triangular wave, whose
output frequency is directly dependent on the magnitude of an input control voltage. The
fundamental function of a VCO is to produce a periodic signal whose frequency can be
dynamically adjusted by varying the input voltage. This characteristic makes VCOs highly
valuable in a wide range of electronic systems where variable-frequency generation is required.
The operation of a VCO is based on varying the reactive components (typically capacitors or
inductors) of a resonant circuit in response to the input voltage. As the control voltage changes,
these components modify the resonant frequency of the circuit, which in turn alters the
frequency of the output signal. VCOs can be implemented using different circuit configurations
such as LC tanks, RC networks, or ring oscillators, depending on the desired frequency range,
linearity, and application requirements.
There are two primary categories of VCOs:
1. Linear VCOs, where the frequency of oscillation varies linearly with the control
voltage, which is ideal for analog signal processing applications.
2. Non-linear or relaxation-type VCOs, which are simpler in design and more
commonly used in digital circuits and low-frequency applications.
Schematic of Voltage Controlled Oscillator:
Fig 5. Schematic of voltage controlled oscillator
Parameters:
S.no. Component name Parameter Value
1. Vdc DC Voltage 1.8V
2. Var Variable voltage 2
3. NMOS(M1,M2,M3,M4, MOSFET W=4.15; L=0.18
M5,M6,M7)
4. PMOS(M8,M9,M10,M1 MOSFET W=4.15; L=0.18
1,M12,M13,M14)
Table 3. Parameters of different components in VCO
Observations:
Fig 6. AC analysis of VCO
Fig7. Power vs Time Graph
Fig8. Phase Noise vs Frequency Graph
S.NO. Parameter Value
1. Output Frequency 865.1MHz
2. Phase Noise -94.6 dBc/Hz
3. Power Consumption 2.06mW
Table 4. Obtained Performance Parameters
Advantages of VCO:
1. Frequency Agility
VCOs can easily adjust their output frequency in response to a control voltage, allowing
dynamic tuning over a wide frequency range. This makes them ideal for applications
like frequency synthesis and modulation.
2. Compact and Easy Integration
Especially in CMOS and digital systems, VCOs (like ring oscillators) can be easily
integrated on-chip, reducing system size and cost.
3. Low Power Consumption
Many VCO designs, particularly those used in integrated circuits, can operate with low
power, making them suitable for battery-powered and portable devices.
4. Wide Tuning Range
VCOs offer a wide frequency tuning range depending on the design, which is beneficial
for systems that require flexibility, such as software-defined radios and variable-
frequency clock systems.
Phase Frequency detector:
The Phase Detector is the first block in a PLL. It compares the phase (and sometimes
frequency) of the input reference signal and the feedback signal from the VCO.
• Function: It outputs a signal proportional to the phase difference.
• Common Types:
o XOR-based PD (for simple applications)
o Phase Frequency Detector (PFD): can detect both phase and frequency
differences, ensuring better acquisition performance and wide locking range.
This block consists of two SR flip flops along with the resetting chain. The reset signal is
triggered when both the inputs are high at the same time. The reset pins of both the SR flip-
flops are connected together and the two set pins are the inputs with reference signal being one
input and VCO’s output as another input. The charge pump is used so that the output from the
PFD should be combined into a single output to drive the LPF and it also pumps in and pumps
out the charge through the LPF and hence the name charge pump. The digital pulses generated
from the PFD are sent to the charge pump and this gives the continuous analog signal. A charge
pump in the Fig. 5 comprises of an inverter and a PMOS at the top and an NMOS at the bottom
(right side).
Schematic of Phase Frequency detector:
Fig9 Phase Frequency detector
Schematic of Phase Locked Loop :
After the connection of all three blocks of PLL. then simulating this design the output obtained
is illustrated in Fig. where the stable frequency is acquired. Detailed view of PLL output is
illustrated below
Fig10. Phase Locked Loop
The schematic represents a fully integrated Phase Locked Loop (PLL) implemented in 180 nm
CMOS technology. It includes the fundamental building blocks necessary for the functioning
of a digital PLL: the Phase Detector (PD), Low-Pass Filter (LPF), and Voltage Controlled
Oscillator (VCO). Each block performs a specific role in achieving phase and frequency
synchronization between the input reference signal and the PLL output.
Observations:
Fig10. Time vs Frequency
Parameters:
S.no. Component name Parameter Value
. Current source DC Current 30µA
4. Supply voltage DC Voltage 1.2V
5. AC signal AC magnitude 1V
Table 5. Obtained Performance Parameters
Applications of PLL (Phase Locked Loop)
Phase Locked Loops are fundamental components in modern electronic systems, valued for
their ability to synchronize, recover, and synthesize signals. Below are key areas where PLLs
are commonly used:
1. Clock Generation and Distribution
• Use: Generate stable, high-frequency clocks from low-frequency references.
• Example: Microprocessors, SoCs, and FPGAs use PLLs to derive internal clocks from
crystal oscillators.
2. Frequency Synthesis
• Use: Generate a wide range of frequencies from a single reference.
• Example: In RF transceivers (e.g., Wi-Fi, Bluetooth, GSM), PLLs enable local
oscillators to tune across multiple channels.
3. Data Recovery
• Use: Recover timing information from data streams.
• Example: In serial communications (USB, Ethernet, SATA), PLLs regenerate clocks
from incoming data for proper synchronization.
4. Demodulation
• Use: Extract information from modulated signals.
• Example: In FM demodulators and other analog communication systems.
5. Motor Speed Control
• Use: Compare motor rotation phase with reference for stable speed control.
• Example: Industrial automation and robotics.
6. Jitter Reduction
• Use: Clean up timing signals in noisy environments.
• Example: Used in digital interfaces like HDMI, DisplayPort, and DDR memory
systems.
Conclusion:
Conclusion and Future Work This project successfully demonstrates a low-power, high-
frequency PLL on a 180 nm CMOS node, achieving 860 MHz output with 1 mW power
consumption. Future enhancements include on-chip loop filter integration, digitally-assisted
calibration for charge pump mismatch, and migration to sub-100 nm technologies for improved
phase noise.
