Name Date EXPERIMENT 1 1 FM Demodulation and Frequency Synthesis Using a Phase-Locked Loop OBJECTIVES 1. Study the operation of the phase-locked loop. 2. Demonstrate how a phase-locked loop is used as an FM demodulator. 3. Demonstrate how a phase-locked loop is used as a frequency synthesizer. MATERIALS One function generator One FM generator One dual-trace oscilloscope ‘One 565 PLL IC One 7490 decade counter (frequency divider) One 7493 4-bit counter (frequency divider) Resistors: 1 kQ, 100 ka Capacitors: 300 pF, 370 pF THEORY In this experiment you will leam how the phase-locked loop (PLL) works and demonstrate its two most commonly used applications as an FM demodulator and a frequency synthesizer. The phase-locked loop is one of the most useful circuits in modern electronic communications because of its versatility and numerous communications applications. It can be used as a frequency modulator, FM demodulator, frequency synthesizer, or in various filtering applications. The phase-locked loop, shown in Figure 11-1, consists of a voltage-controlled oscillator (VCO), a phase detector, and a low-pass filter (LPF). It is a closed-loop feedback control system that locks the frequency of the voltage-controlled oscillator onto an input reference frequency. Itis the purpose of the PLL phase detector to compare the VCO output phase to the input reference phase. The phase of two signals does not need to be the same for the frequencies 145Figure 11-1 Phase-Locked Loop (PLL) Reference Freqin to be equal. If the frequencies are different, then the phase difference will be constantly changing. If the frequencies are identical, then the phase difference will not be changing. As the phase difference increases, the phase detector output will increase. As the phase difference decreases, the phase detector output will decrease. When the phase difference stays constant, indicating that the frequencies are equal, the phase detector output will stay constant. The phase difference (0), in degrees, between two sine waves can be determined by first measuring the time between the sine waves ({) and the time period for one sine wave cycle (T) on the oscilloscope, and then using the following equation to calculate the phase difference. © x 360° T Most phase detectors are digital. The output is a pulsating de voltage with a varying duty cycle. This duty cycle will increase as the phase difference increases, or decrease as the phase difference decreases, causing the average value of the phase detector output voltage to increase or decrease. It is the purpose of the low-pass filter (LPF) to smooth the pulsating output of the phase detector into a de control voltage that is equal to the average output voltage of the phase detector. This de control voltage is applied to the input of the VCO to control its frequency. The output frequency of the VCO will continue to be varied by the output of the phase detector and LPF until the VCO frequency is equal to the reference frequency. Ifthe reference frequency stays constant, the output of the phase detector and LPF will cause the VCO output frequency to stay constant. If the reference frequency is varied, the output of the phase detector and LPF will cause the VCO output frequency to track the reference frequency. By increasing the cutoff frequency of the LPF, the time it takes for the PLL to respond to changes in the reference frequency will decrease, but at the expense of poorer VCO control voltage filtering. This will cause an increase in the control voltage ripple, The higher the LPF cutoff frequency, the greater the control voltage ripple. 146In applications where the reference frequency is changing rapidly, a higher cutoff frequency is required in the LPF. The PLL has three operating states: free-run, capture, and locked. In the free-run state, there is no reference frequency input. Under this condition, there is no phase for the phase detector to compare to the VCO output phase. This will cause the VCO to free-run at its natural frequency, which is determined by its circuit components. When a reference frequency that is close to the free-run frequency of the VCO is applied to the PLL, the phase detector and LPF will produce a de voltage proportional to the phase difference between the reference frequency and the VCO output frequency. This causes the PLL to go into its capture state. The time needed for the VCO to get locked onto the reference frequency is determined by the cutoff frequency of the LPF. The PLL cannot lock onto all frequencies. Only frequencies within a range of frequencies called the capture range can be locked onto from the free-running state. The width of the capture range is determined by the design of the PLL, with the LPF playing an important role. If the reference frequency is outside the capture range, the VCO will continue to operate at the free-running frequency. Once the VCO is locked onto the reference frequency, the PLL is in the locked state. If the reference frequency is varied while the PLL is in the locked state, the VCO output frequency will track the reference frequency. The PLL cannot remain locked for all frequencies. If the reference frequency moves outside the lock range, the PLL will drop out of lock. The VCO lower- and upper-frequency limits determine the lock range. The lock range is larger than the capture range, While the PLL is in the locked state, the output of the LPF is a de voltage that is proportional to the input reference frequency. When the reference frequency increases or decreases, the LPF de output voltage will increase or decrease. Because the LPF output voltage is proportional to the reference frequency, the PLL can be used as an FM detector, as shown in Figure 11-2. For this application, the frequency-modulated carrier is the PLL reference frequency and the output of the LPF is the modulating signal output. Because the LPF is designed for a fast PLL response to changes in the reference frequency, the cutoff frequency is too high to do an effective job of removing the output ripple. The R-C low-pass filter (R and C) has a lower cutoff frequency than the LPF, producing a smoother output signal with less ripple than at the LPF output. Therefore, this R-C low-pass filter output is the FM detector output in Figure 11-2. Because the PLL captures signals only within a particular range of frequencies, it acts like a band-pass filter. This filtering effect causes the PLL to filter out noise, giving it a signal-to-noise ratio that is superior to that of any other type of FM detector. A frequency synthesizer is a variable frequency generator that produces an output frequency that varies in fixed increments over a frequency range. In modern communications, most frequency synthesizers use some variation of a phase-locked loop. By modifying the feedback portion of the loop, we can get the VCO to produce different frequencies at multiples of the reference frequency. The synthesizer output frequency is the ‘VCO output frequency. The circuit in Figure 11-3 shows a phase-locked loop with a frequency divider inserted within the feedback loop. The frequency divider reduces the frequency at the phase detector In2 input. This will force the VCO to increase its frequency 147Figure 11-2 PLL FM Demodulator FM Input’ ‘ea] Phase_Det LPF Recovered 400K0hm ‘Mod Signal oul Im + veo Fit } 10V 100kH2 Skitz LS - by an amount equal to the divider ratio in order to make the divider output frequency be equal to the reference frequency. For example, a divider ratio of ten would require the VCO to increase its frequency by a factor of ten in order to make the divider output frequency be equal to the reference frequency. This would make the VCO output frequency be ten times the reference frequency. By electronically changing the divider ratio, the VCO output frequency can be varied electronically. Most modern frequency synthesizers use a microprocessor to control the divider ratio electronically. The reference frequency sets the increments in which the synthesizer output frequency can be changed. Because the VCO Jocks onto the reference frequency, a stable reference frequency will produce a stable VCO output frequency. The reference frequency oscillator is normally a erystal-controlled oscillator, which provides good frequency stability. The PLL frequency synthesizer in Figure 11-3 will be used to demonstrate how a PLL. frequency synthesizer works Figure 11-3 PLL Frequency Synthesizer Ref Freq In tas[——Jout_tof——Jout_vinf —Jrout_| Freq ia Out oF veo outt [Jin & 5V 10Kt42 0De9 148,PROCEDURE Step 1 Step 2 Step 3 Open circuit file FIGII-1. This circuit will be used to study the operation of the phase-locked loop (PLL). You will monitor the PLL reference frequency input and the VCO output on the oscilloscope. Bring down the oscilloscope enlargement and make sure that the following settings are selected: Time base (Scale = 5 us/Div, Xpos = 0, Y/T), Ch A (Scale = 10 V/Div, ¥pos = 0, DC), Ch B (Scale = 10 V/Div, ‘Ypos = 0, DC), Trigger (Pos edge, Level = 0, Auto), Run the simulation until the phase difference between the sine waves is constant, and then pause the simulation. This represents the locked state. The oscilloscope blue curve plot is the VCO output and the red curve plot is the reference frequeney input. Measure the VCO output (blue curve) time period for one cycle (T) and calculate the VCO output frequency (f,). Question: Is the VCO output frequency equal to the reference frequency? Was this expected? Explain why. Step 4 Step 5 Step 6 Measure the time between the sine waves (t) and calculate the phase difference (0) from this time difference and the time period for one cycle (T). Move the oscilloscope channel B input to the filter output terminal on the PLL. Bring down the oscilloscope enlargement and change the channel B scale to 2 V/Div. Run the simulation until the filter output (top curve) average value is constant, then pause the simulation. There will be a slight ripple in the filter output, Measure the average voltage of the filter output (V;) and record the value. Vem 149Step7 Move the oscilloscope channel B input back to the VCO output terminal on the PLL. (Make sure the oscilloscope connecting wire is still blue by clicking it with the right mouse button and selecting color). Change the reference frequency to 70 kHz, Bring down the oscilloscope enlargement and change the channel B scale back ‘o 10 V/Div. Run the simulation until the phase difference between the sine waves is constant, and then pause the simulation, This represents the locked state. The oscilloscope blue curve plot is the VCO output and the red curve plot is the reference frequency input. Step 8 — Measure the VCO output (blue curve) time period for one cycle (T) and calculate the VCO output frequency (f,) Question: Is the VCO output frequency equal to the reference frequency? Was this expected? Explain why. Step 9 Measure the time between the sine waves (1) and calculate the phase difference (8) from this time difference and the time period for one cycle (T). Question: How did this phase difference compare with the phase difference in Step 4 when the reference frequency was 100 kHz? Explain any difference. Step 10 Move the oscilloscope channel B input to the filter output terminal on the PLL. Bring down the oscilloscope enlargement and change the channel B scale to 2 V/Div. Run the simulation until the filter output (top curve) average value is constant, then pause the simulation, There will be a slight ripple in the filter output Step 11 Measure the average voltage of the filter output (V9) and record the value. Vee 150Question: How did this average voltage compare with the average voltage in Step 6 when the reference frequency was 100 kHz? Explain any difference. Step 12 Step 13 Move the oscilloscope channel B input back to the VCO output terminal on the PLL. (Make sure the oscilloscope connecting wire is still blue). Change the reference frequency to 130 kHz. Bring down the oscilloscope enlargement and change the channel B scale back to 10 V/Div. Run the simulation until the phase difference between the sine waves is constant, and then pause the simulation. This represents the locked state. The oscilloscope blue curve plot is the VCO. output and the red curve plot is the reference frequency input. Measure the VCO output (blue curve) time period for one eyele (T) and calculate the VCO output frequency (f,) Question: Is the VCO output frequency equal to the reference frequency? Was this expected? Explain why. Step 14 Measure the time between the sine waves (t) and calculate the phase difference (0) from this time difference and the time period for one cycle (T). Question: How did this phase difference compare with the phase difference in Step 4 when the reference frequency was 100 kHz? Explain any difference. Step 15 Move the oscilloscope channel B input to the filter output terminal on the PLL. Bring down the oscilloscope enlargement and change the channel B scale to 2 V/Div. Run the simulation until the filter output (top curve) average value is constant, then pause the simulation. There will be a slight ripple in the filter output. 151Step 16 ‘Measure the average voltage of the filter output (V;) and record the value, Ve= Question: How did this average voltage compare with the average voltage in Step 6 when the reference frequency was 100 kHz? Explain any difference. Step 17 Questio Move the oscilloscope channel B input back to the VCO output terminal on the PLL. (Make sure the oscilloscope connecting wire is still blue). Change the reference frequency to 140 kHz. Bring down the oscilloscope enlargement and change the channel B scale back to 10 V/Div. Run the simulation. The oscilloscope blue curve plot is the VCO output and the red curve plot is the reference frequency input. Did the phase difference between the sine waves ever become constant? Is this frequency outside the PLL capture range? Explain your answer. Step 18 Step 19 Step 20 152 Stop the simulation and disconnect the reference frequency generator from the reference frequency input terminal. Run the simulation to four oscilloscope screen displays, then pause the simulation. Measure the VCO output (blue curve) time period for one cycle (T) and calculate the VCO output natural frequency (f,. Open circuit file FIGL1-2. This circuit will be used to demonstrate the operation. of a phase-locked loop (PLL) as an FM demodulator. A frequency-modulated cartier is applied to the PLL reference frequency input and the modulating signal is monitored at the LPF output. Bring down the oscilloscope enlargement and make sure that the following settings are selected: Time base (Scale = 50 us/Div, Xpos = 0, ¥/T), Ch A (Scale = 20 ViDiv, Ypos = -2.0, DC), Ch B (Scale = 2 ViDiv, Ypos = 0, DC), Trigger (Pos edge, Level = 0, Auto) Run the simulation to completion. You have plotted the R-C filter output curve plot (blue) and the frequency-modulated carrier curve plot (red) on the oscilloscope.Question: Does the R-C filter output voltage follow the frequency variations of the frequency- modulated carrier? Was this expected? Step 21 Measure the R-C filter output (blue curve) time period for one cycle (T) and calculate the filter output frequency (fp). Question: Is the R-C filter output frequency equal to the carrier modulating frequency? Was this expected? Explain why. Step 22 Move the oscilloscope channel B input to the LPF output of the PLL. Bring down the oscilloscope enlargement and run the simulation to completion. You have plotted the LPF output curve plot (top curve plot) and the frequeney-modulated carrier curve plot (bottom curve plot) on the oscilloscope. Questions: What is the difference between this LPF output curve plot and the output curve plot of the R-C filter in Step 20? ‘What is the reason for any difference? Step 23 Return the oscilloscope channel B input to the output of the R-C filter. Change the signal frequency on the FM generator to 3 kHz, Bring down the oscilloscope enlargement and change the time base scale to 100 us/Div. Run the simulation to completion. Measure the R-C filter output (top curve) time period for one cycle (T) and calculate the new filter output frequency (fn). Question: Is the new R-C filter output frequency equal to the new cartier modulating frequency? Was this expected? Explain why. 153Step24 Open circuit file FIG1 1-3. This circuit will be used to demonstrate the operation of a phase-locked loop (PLL) as a frequency synthesizer. Notice that the Outl divider output is connected to the phase detector. Bring down the oscilloscope enlargement and make sure that the following settings are selected: Time base (Scale = 20 us/Div, Xpos = 0, Y/T), Ch A (Scale = 10 V/Div, Ypos = 0, DC), ChB (Scale = 5 V/Div, Ypos = 0, DC), Trigger (Pos edge, Level = 0, Auto). Step 25 Run the simulation to completion. You have plotted the PLL VCO output (blue) and the divider output (red) on the oscilloscope. Measure the VCO output (blue curve) time period for one cycle (T) and calculate the VCO output frequency (f,). Step 26 — Measure the divider output (red curve) time period for one cycle (T) and calculate the divider output frequency (f), Questions: What is the relationship between the VCO output frequency and the reference frequency? ‘What is the relationship between the divider output frequency and the reference frequency? Was this expected? Explain why. ‘What is the relationship between the divider output frequency and the VCO output frequency? Based on these results, what is the divider ratio? 154Step 27 Remove the phase detector from the divider Outl terminal and connect it to the divider Out2 terminal. Bring down the oscilloscope enlargement and run the simulation to completion. Measure the VCO output (blue curve) time period for one cycle (T) and calculate the VCO output frequency (f,). Step 28 Measure the divider output (red curve) time period for one cycle (T) and calculate the divider output frequency (9. Questions: What is the relationship between the VCO output frequency and the reference frequency? What is the relationship between the divider output frequency and the reference frequency? ‘Was this expected? Explain why. What is the relationship between the divider output frequency and the VCO output frequency? Based on these results, what is the divider ratio? Did the VCO output frequency change when the divider ratio changed? Was this expected? Explain why. 155