TABLE OF CONTENTS:

SL No: Experiment Name

1. Measurement of modulation index of an AM signal.

Design & set up a PLL using VCO & measurement the lock frequency.
2.

Study of distortion of the demodulated output with varying modulation index of an

3. AM signal (for both DSB-SC & SSB)

4. Study of PAM & Demodulation

Study of PCM & Demodulation

5.

6. Study of Delta Modulator & Demodulator

Design a FM demodulator using PLL.

7.
EXPERIMENT NAME: Measurement of modulation index of an AM signal.

Objective: To perform amplitude modulation of a signal, plot the waveform and calculate
modulation index.

Apparatus Required: CRO, CRO probes, Function Generator (2 nos.), Power supply,
Breadboard, connecting wires. Transistor: - BC548/549 (1 nos.),Resistor: - 330W (2 nos.),
Inductor: - 1mH (1 nos.)

Circuit Diagram

Waveforms:
 Result: Study of Amplitude modulation is completed.

Conclusion: Justify any error, difficulties & precaution

EXPERIMENT NAME: Design a PLL using VCO & measurement the lock
frequency.
Objective: To design a PLL using VCO & to measure the lock frequency.

Introduction:
The phase-locked loop, or PLL, is one of the most useful blocks in modern electronic circuits. It
is used in many
different applications, ranging from communciations (FM modulation, demodulation, frequency
synthesis, signal correlation), control systems (motor control, tracking controls, etc), as well as
applications such as pulse recovery and frequency multiplication.
PLL Theory of Operation:
A PLL is a closed-loop system whose purpose is to lock an oscillator onto a provided input
frequency (sometimes called the reference frequency.) By "closed-loop," we mean that there is
feedback from output to input. In a PLL, negative feedback is used, which makes it self-
correcting. Figure 1 shows the block diagram of a typical PLL.

Figure 1: Phase Locked Loop Block Diagram

A PLL has a special oscillator, a VCO. We know that a VCO changes its output frequency based
on input voltage (as well as Rt and Ct choices). The primary objective of PLL operation is to get
the VCO frequency to be exactly equal to that of the reference frequency. When this happens, the
loop is said to be "in lock."

This is achieved by feeding both the VCO output and the reference frequency into a phase
detector. The phase detector compares the phase of the two waves and outputs a pulsating DC
waveform with a duty cycle proportional to the phase difference (error) between the two signals.
Why compare phase and not frequency?
The answer is that if we compare frequency, then there will always be a small frequency error in
our result. However, if we compare phase, the frequency error is reduced to zero whenever the
phase difference is a constant.
This is easier to visualize if you think about synchronizing the speed of two cars. Two cars do
not have to be in exactly the same position (phase) on the highway to have the same speed. One
can be following the other at a fixed distance (fixed phase difference). As long as they aren't
speeding up or slowing down relative to each other, their speeds (frequencies) will be exactly the
same.

PLL Operating States

A PLL has three operating states. These are the free-running, capture, and locked conditions.
In the free-running state, there is no reference input frequency being provided to the PLL. Design
constants within the system determine what frequency the VCO will run at. Normally, two of
these are the values of Rt and Ct, the VCO timing components.
In the capture state, which is usually short-lived, the PLL has just been given a reference
frequency, and it is in the
process of trying to "lock" onto it. The PLL cannot lock onto all frequencies; only a certain range
of frequencies, within the capture range can be locked onto, if the PLL is initially in the free-
running state. The free-running frequency is usually in the middle of the capture range. The
width of the capture range is determined by PLL design; the loop low-pass filter is important in
determining this.
The last PLL state is the desired state: Locked! In this state, the PLL has successfully passed
through the capture
phase, and it has its VCO steadily "locked" onto the input reference frequency. The PLL cannot
remain locked for all frequencies, and if the input reference frequency moves outside the lock
range (which is usually larger than the capture range), the PLL will drop out of lock.

Figure 2 illustrates the relationship between free-running frequency, capture range, and lock
range:

Figure 2: PLL Operating Regions

Circuit Analysis:
The PLL in this circuit is entirely contained within one IC chip, the LM-565.All that we need to
provide to build a complete functioning PLL are timing elements (Rt, Ct) for the VCO and a
capacitor for the low-pass filter. (The LM-565 has a 3.6K resistor on-chip for the low-pass filter.)
In Figure 3,the VCO timing is set by R1, R2, and C2. The low-pass filter time-constant (which
we will vary) is formed by the internal 3.6K resistor on pin 7 and C5. The reference input goes to
pin 2, one of the phase detector inputs. The other phase detector input on pin 5 is directly
connected to the VCO output on pin 4, closing the loop.

Figure 3: PLL Evaluation Circuit using the LM-565

Procedure & Result:

In this experiment, you will observe the operation of the PLL subsystem. You'll learn to
recognize the three PLL states in actual circuits, and you will also gain some insight into how
circuit values affect PLL operation.
To get accurate frequency readings, it is strongly suggested that you use a frequency counter.
Some of the frequency readings will be fairly close in value. If you have the audio monitor
available, connect its input to the VCO OUTPUT of the PLL circuit so that you can hear the PLL
going in and out of lock.

1. Construct the circuit of Figure 3 using a 10 mF electrolytic for C5. (C5 is the capacitor for the
loop low-pass filter.)
2. Apply power to the circuit, but don't apply a reference signal yet. We want to set the free-
running frequency of the VCO. Adjust R1 until the output frequency of the VCO on pin 4 is 1
KHz.
3. Apply the reference frequency to the reference input of the circuit.
4. Connect scope channel #1 to the reference input of the circuit, and scope channel #2 to the
VCO output. Connect the frequency counter to the reference input, so that the frequency of the
reference is displayed. (Be sure to trigger off channel #1, the reference input.)
5. Set the function generator to 600 Hz, 1 Vpp sine. Observe the two scope traces and describe
what you see below.
6. Slowly increase the frequency of the generator until the PLL just locks. (The two traces appear
stable on the scope). A phase shift will be present between the VCO and reference frequency;
this is OK. This frequency is the bottom of the capture range, FC(lower), as shown in Figure 2.
Record it below.
7. Let's find the top of the lock range. Slowly increase the frequency until the PLL again drops
out of lock. This frequency is the top of the lock range, FL(upper). Record it below.
8. The PLL is now out of lock, and the reference frequency is above the top of the capture range.
Slowly decrease the reference until the PLL locks again; this is FC(upper). Finally, decrease the
reference frequency until the PLL drops out of lock again; this is FL(lower). Record these
values.
9. Let's observe the output from the low-pass filter, to see what happens when the input
frequency changes. We know it is supposed to be smooth DC, so we'll need to use the DC setting
of the scope to see the DC component. We also know that no filter is perfect, so some AC ripple
will be present on top of the DC. Set the reference frequency to 1 KHz, and record the low-pass
filter output on pin 7 of the IC
10. Increase the input frequency (but keep it within the lock range). What happens to the filter
DC output? (You may want to measure pin 7 with a DC multimeter to get more precise voltage
readings).
11. The capture range depends on the low-pass filter of the PLL. Let's see how. Replace C5 with
each value in the table below, and measure the width of the capture and lock ranges for each
case.

12. Study the data in the above table carefully. Describe the relationship between the capture
range and size of the filter capacitor in the low-pass filter according to the data in your table.

ANALYSIS:

The PLL in this circuit is entirely contained within one IC chip, the LM-565.All that we need to
provide to build a complete functioning PLL are timing elements (Rt, Ct) for the VCO and a
capacitor for the low-pass filter. (The LM-565 has a 3.6K resistor on-chip for the low-pass filter.)

In Figure 3, the VCO timing is set by R1, R2, and C2. The low-pass filter time-constant (which
we will vary) is formed by the internal 3.6K resistor on pin 7 and C5. The reference input goes to
pin 2, one of the phase detector inputs. The other phase detector input on pin 5 is directly
connected to the VCO output on pin 4, closing the loop.

CONCLUSION: Justify any error, difficulties & precaution.

EXPERIMENT NAME: Study of distortion of the demodulated output with

varying modulation index of an AM signal (for both DSB-SC & SSB)
Objective: To study the distortion of the demodulated output with varying modulation index of
an AM signal (for both DSB-SC & SSB)

Apparatus: DSB/SSB transmitter trainer kit, function generator,

CRO, probes, connecting wire

Theory:
Block Diagram:

Procedure:

1. Connect the trainer to mains. Make all necessary onboard connections.

2. Provide information signal either internally or externally.
3. Observe the DSB-SC wave form at the output of the balances modulator.
4. The SSB signal is obtained at the o/p of the ceramic BP filter.
5. Compare and contrast the two waveforms on the CRO.
6. Draw SSB signal.

REMARKS:

Justify any error, difficulties & precaution.

WORKING OF REFLEX / MULTI-CAVITY KLYSTRON

EXPERIMENT NAME : Study of PAM & Demodulation.

Aim: To generate the Pulse Amplitude modulated signal and demodulated signals.

Apparatus required:

1.Pulse amplitude modulation trainer.

2. Signal generator
3. CRO
4. BNC probes, connecting wires.

Theory:

PAM is the simplest form of the data modulation. The amplitude of uniformly spaced pulses is
varied in proportion to the corresponding sample values of a continuous message m(t). A PAM
waveform consists of a sequence of list-topped pulses. The amplitude of each pulse corresponds
to the value of the message signal x(t) at the leading edge of the pulse. The pulse amplitude
modulation is the process in which the amplitude of regularity spaced rectangular pulses vary
with the instantaneous sample values of a continuous message signal in a one-one fashion. PAM
is of two types :
1. Double polarity PAM – This is the PAM wave which consists of both positive and negative
pulses.
2. Single polarity PAM – This consists of PAM wave of only either negative or positive pulses.
In this the fixed dc level added to the signal to ensure single polarity signal.

Circuit Diagram:
Procedure:

1 . Switch on pulse Amplitude modulation and demodulation trainer.

2 . In clock generator section connect pin 6 of 555IC to the 33pfcapacitor terminal.
3 . Check the clock generator (RF)output signal.
4 . Connect RF output of clock generator to the RF input of modulator section.
5 . Connect a 1KHz; 2vp-p of sine wave from function generator to the AF input of modulator
section.
6 . Short the 10F terminal and 10k terminal of modulator.
7 . Connect 10k terminal to pin 1 of IC 4016.
8 . Connect the CRO to modulated output of modulator section.
9 . Adjust the 1k potentiometer to vary the amplitude of the modulated signal.
10. Adjust the AF signal frequency from 1KHZ-10KHZ to get stable output waveform. While
increases the AF signal frequency decreases the output signal pulses.
11 During demodulation, connect the modulated output to the PAM input of Demodulator section.
12 .Connect channel 1 of CRO to modulating signal and channel-2 to demodulated output.
Observe the two waveforms that they are 1800out of phase, since the transistor detector operates
in CE configuration.
Experiment Name : Study of PCM & Demodulation.

Aim: to study the circuit of pulse code modulation and demodulation.

Apparatus:

1. Pulse Code Modulation and Demodulation trainer

2. CRO
3. Connecting Wires.

Theory:

In pulse code modulation (PCM) a message signal is represented by a sequence of coded pulses,
which is accomplished by representing the signal in discrete form in both time and amplitude.

The basic operations performed in the transmitter of a PCM system are sampling, quantizing and
encoding. The low pass filter prior to sampling is included to prevent aliasing of the message
signal. The incoming message signal is sampled with a train of narrow rectangular pulses so as to
closely approximate the instantaneous sampling process. To ensure perfect reconstruction of the
message signal at the receiver, the sampling rate must be greater than twice the highest frequency
component W of themessage signal in accordance with the sampling theorem. The quantizing
and encoding operations are usually performed in the same circuit, which is called an analog-to-
digital converter. The same circuit, which is called and analog-to-digital converter. The sampled
version of the message signal is then quantized, thereby providing a new representation of the
signal that is discrete in both time and amplitude. In combining the process of sampling and
quantization, the specification of a continuous message (baseband) signal becomes limited to a
discrete set of values, but not in the form best suited to transmission. To exploit the advantages
of sampling and quantizing for the purpose of making the transmitted signal more robust to nose,
interference and other channel impairments, we require the use of an encoding process to
translate the discrete set of sample values to a more appropriate form of signal.

Regeneration:

The most important feature of PCM system lies in the ability to control the effects of distortion
and noise produced by transmitting a PCM signal through a channel. This capability is
accomplished b reconstructing the PCM signal by means of a chain of regenerative repeaters
located at sufficiently closed spacing along the transmission route. As, illustrated in figure below
three basic functions are performed by a regenerative repeater: equalization timing and decision
making.

The equalizer shapes the received pulses so as to compensate for the effects of amplitude and
phase distortion produced by the non-ideal transmission characteristics of the channel. The
timing circuit provides a periodic pulse trainer, derived from the received pulses, for sampling
the equalized pulses at the instants of time where the signal to noise ratio is maximum. Each
sample so extracted is compared to predetermined threshold in the decision making device. In
each bit interval, a decision is then made whether the symbol is 1 or 0 on the basis of whether the
threshold is exceeded or not. If the threshold is exceeded, a pulse representing symbol ‘1’ is
transmitted. In the way, the accumulation of distortion and noise in a repeater span is completely
removed. The basic operations in the receiver are regeneration of impaired signals, decoding and
reconstruction of the train of quantized samples. The first operation in the receiver is to
regenerate (i.e., reshape and cleanup) the received pulses one last time. This decoding process
involves generating a pulse, the amplitude of which is the linear sum of all the pulses in the code
word. The final operation in the receiver is to recover the message signal by passing the decoder
output through a low pass reconstruction filter whose cut-off frequency is equal to the message
band width W. Assuming that the transmission path is error free, the recovered signal includesno
noise with the exception of the initial distortion introduced by the quantization process.

BLOCK DIAGRAM OF PULSE CODE MODULATION AND DEMODULATION

Procedure:

1. Switch ON Pulse Code Modulation and Demodulation Trainer Kit.

2. Connect the variable DC O/P to the Analog I/P of modulation section.
3. Connect the clock O/P of bit clock generator to the clock I/P of modulation section.
4. By varying the variable DC O/P observe the PCM O/P on CRO.
5. Connect the AF output to Analog I/P of modulation section by removing variable DC O/P.
6. Connect the PCM O/P to PCM I/P of demodulation section.
7. Observe the DAC O/P at channel 1 of CRO and observe the demodulated O/P at channel 2 of
CRO.
Expected Waveforms :
Experiment Name : Study of Delta Modulator & Demodulator.

Aim: (a) To verify the Encoding process of Linear Delta Modulator and corresponding
waveforms.
(b) To verify the operation of the Linear Delta Demodulator.

Apparatus:

1. Experimental kit of Delta modulation & demodulation.

2. 20MHz Dual trace Oscilloscope
3. Patch chords & CRO probes.

Procedure For Modulation:

1. Connect PLA1 to PLAA.

2. Connect channel 1 of CRO to TPA1/TPAA. Adjust VR1 to minimum to get zero level signals.
3. Connect channel-1 to TP1 and channel-2 to TPB1 and adjust VR2 to obtain square wave half
the frequency of the clock rate selected (Output at TP1).
4. Connect channel 1 to TP2 and set voltage/div of channel 1 to mV range and observe a triangle
waveform which is output of integrator. It can be observed that as the clock rate is increased,
amplitude of triangle waveform decreases. This is called minimum step size (Clock rate can be
changed by depressing SW1 switch).
5. Connect channel 1 to TPA1/TPAA. Adjust VR1 in order to obtain a 1 KHz sine wave of 500
mVp-p approximately.
6. Signal approximating 1 KHz is available at the integrator output (TP2). This signal is obtained
by integrating the digital output resulting from delta modulation.
7. Connect channel 1 to TP2 and channel 2 to TPBa. It can be observed that the digital high
makes the integrator output to go upwards and digital low makes the integrator output to go
downwards.
8. With an oscilloscope displaying three traces, it is possible to simultaneously observe the input
signal of the modulation, the digital output of the modulator and the signal obtained by the
integration from the modulator digital output. Notice that, when the output (Feedback signal) is
lower than the analog input the digital output is high, whenever it is low when the analog input is
lower than the integrated output.
9. Increases the amplitude of 1 KHz sine wave by rotating VR1 to 1Vp-p observe that the
integrator output follows the input signal.
10. Increase that amplitude of 1 KHz sine wave further high, and observe that the integrator
output cannot follow the input signal.
11. Repeat the above mentioned procedures with different signal sources and selecting different
clock rates and observe the response of the Linear Delta Modulator.

Block Diagram:
Experimental Setup For Delta Modulation:

Delta Modulation Waveforms:

Procedure For Demodulation:

1. Prearrange the connections of Linear Delta Modulator.

2. Connect PLB1 (Digital output of Delta Modulator) to PLBB (input of Linear Delta
modulator).
3. Connect PLC1 (Linear Delta Demodulator output) to either PLCA (input of fourth order LPF)
or PLCB (input of Second order LPF).

Block Diagram:

Experimental Setup For Delta Modulation:

 Experiment name: Design a FM demodulator using PLL.

Objective:

There are two main objectives for this experiment:

 to implement the phase locked loop (PLL) for FM demodulation.

 to implement frequency discriminator method for demodulating FM.
THEORY:

The block diagram of a phase locked loop (PLL) is shown in Figure 1. The principle of
operation is simple. Suppose there is an unmodulated carrier at the input. If the VCO
was tuned precisely to the frequency of the incoming carrier, ω0, then the instantaneous
output would be a DC voltage, of magnitude depending on the phase difference
between the output of the VCO and the incoming carrier. Now suppose the incoming
carrier started to drift slowly in frequency. Depending upon which way it drifts, the
output voltage will vary accordingly. If the incoming carrier is frequency modulated
by a message, the output of the PLL will follow the message.

Figure 1: the PLL

FM can be demodulated as well by using a differentiator or a frequency

discriminator. Frequency discrimination can be achieved by applying the FM signal to
the linear part (transition region) of a BPF as depicted in Figure 2. The output of the
discriminator is both FM and AM modulated. The message can be recovered by
applying the discriminator output to an envelope detector followed by LPF.

The BPF of the 100 kHz CHANNEL FILTERS module has close-to-linear pattern in the
band 80- 90 kHz.
 Figure 2: Band Pass Filter as a frequency discriminator

The following modules are needed to complete the experiment : AUDIO

OSCILLATOR, ADDER, MULTIPLIER, UTILITIES, 100 kHz CHANNEL
FILTERS, VCO (2 modules, one for the modulator and the second is used for the PLL
demodulator).

APPARATUS USED:

1. Pulse width modulation and Demodulation Trainer.

2. CRO
3. BNC probes and Connecting Wires

PROCEDURE:

Part I: FM Demodulation Using PLL

1. Reconstruct the FM modulator as in the previous experiment (FM Modulation).

Let the message be 2 kHz from the AUDIO OSCILLATOR, the carrier 100
kHz from VCO, and the modulator VCO GAIN about 25%.
2. Model the PLL demodulator illustrated in Figure 1. For the filter use RC LPF
provided in the UTILITIES Module. In the MULTIPLIER module set the
toggle switch to AC. Draw the corresponding module diagram.
3. Set the VCO in the demodulator to 100 kHz. Set the GAIN control to mid-
range position.
4. Connect the output of the modulator to the input of the demodulator.
5. The PLL may or may not lock on to the incoming FM signal. Tune the GAIN
(and if necessary the center frequency) of the PLL-VCO until you obtain lock.
Examine the output of the PLL VCO and compare it with the original message.
Replace the message from the AUDIO OSCILLATOR by a speech signal and make sure that
you can hear the recorded message correctly. Study the effect of varying the frequency f0 and
GAIN of the PLL-VCO on the quality of the received speech.

Part II: Frequency Discriminator

 1. Set the VCO to generate an FM signal with carrier frequency 85 kHz and
GAIN around 25%.
2. Connect the FM signal to the BPF (Use the 100 kHz CHANNEL FILTER
MODULE, set CHANNEL SELECT to 3).
3. Perform envelope detection by connecting the BPF output to the DIODE+LPF in
the UTILITIES module.
4. Connect the output of the envelope detector to the HEADPHONE AMPLIFIER.
5. Apply a speech signal to the FM modulator (VCO), and listen to the
demodulated signal.
6. Tune the VCO carrier frequency slightly around the 85 kHz until you get the
best output (BPF modules may have slightly different characteristics). Get the
approval of your instructor for this step.

REMARKS:

Justify any error, difficulties & precaution.