Unit -5
Phase Locked Loops
Phase locked loop- Phase Locked Loop (PLL) is useful in communication systems
such as radars, satellites, FMs, etc.
Block Diagram of PLL
A Phase Locked Loop (PLL) mainly consists of the following three blocks −
Phase Detector
Active Low Pass Filter
Voltage Controlled Oscillator (VCO)
The block diagram of PLL is shown in the following figure −
The output of a phase detector is applied as an input of active low pass filter. Similarly, the
output of active low pass filter is applied as an input of VCO.
The working of a PLL is as follows −
between the input signal having frequency of 𝑓𝑖𝑛 and feedback (output) signal
Phase detector produces a DC voltage, which is proportional to the phase difference
having frequency of 𝑓𝑜𝑢𝑡.
output − sum of the frequencies fin𝑓𝑖𝑛 and 𝑓𝑜𝑢𝑡 and difference of
A Phase detector is a multiplier and it produces two frequency components at its
frequencies 𝑓𝑖𝑛 & 𝑓𝑜𝑢𝑡.
An active low pass filter produces a DC voltage at its output, after eliminating high
frequency component present in the output of the phase detector. It also amplifies the
signal.
A VCO produces a signal having a certain frequency, when there is no input applied
to it. This frequency can be shifted to either side by applying a DC voltage to it.
Therefore, the frequency deviation is directly proportional to the DC voltage present
at the output of a low pass filter.
The above operations take place until the VCO frequency equals to the input signal
frequency. Based on the type of application, we can use either the output of active low pass
filter or output of a VCO..
PLL operates in one of the following three modes −
Free running mode
Capture mode
Lock mode
Initially, PLL operates in free running mode when no input is applied to it. When an input
signal having some frequency is applied to PLL, then the output signal frequency of VCO
will start change. At this stage, the PLL is said to be operating in the capture mode. The
output signal frequency of VCO will change continuously until it is equal to the input signal
frequency. Now, it is said to be PLL is operating in the lock mode.
Lock Range:
The range of frequencies of the input signal over which a PLL maintain a
lock is called the lock range.
Capture range:
The range of frequencies of the input signal over which a PLL can acquire
lock is called the capture range. The greatest capture range possible is equal to the
lock range but capture range is less than lock range.
TRANSFER CHARACTERISTICS OF PLL:-
When the PLL is in lock, a frequency shift at the input is transferred to a voltage level
shift at the VCO control Terminal. The following characteristics shown the voltage
frequency characteristics of the PLL.
Fig. Transfer characteristics of PLL
1. The input is assumed to be a sine wave, whose frequency is swept over a
broad frequency range and the vertical axis corresponds to the error voltage
Ve (t).
2. the incoming input frequency is slowly increasing.
3. The loop does not respond till the input frequency reaches f₁.
4. This frequency f1 corresponds to the Lower edge of the capture range.
5. After this, the loop immediately locks on to the input signal causing a
negative jump of error voltage (since Input frequency is less than VCO
frequency).
6. As the input signal frequency is further increased beyond f1, Ve (t) varies with
frequency with a slope equal to the reciprocal of the
7. VCO gain,1/K and goes positive when input frequency is greater than VCO
frequency. The loop tracks the input until the input frequency reaches f2
which corresponds to the upper edge of the Lock range.
8. Then the PLL loses track of the input frequency. It is no more in the Lock
state.
9. If the input frequency is slowly swept back, the cycle repents itself.
10. The PLL recaptures signal of frequency f3 and traces it down to frequency
f4.f3 is called the upper edge of the capture range and f4 is the lower edge of
the Lock range .
11. The frequency range between f1 and f3 corresponds to the total capture
range
i.e.
f3 - f1 = 2∆fc and
the frequency range between f2 and f4 corresponds to the total lock range.
F2 – f4 = 2∆fL .
STUDY OF PLL IC 565-
It is available in two package- 10 pin circular metal package and 14 pin dual-in-line
package.
1) 10 pin-metal package-
1. The PLL IC 565 is usable over the frequency range 0.1 Hz to 500
kHz.
2. The output of VCO is capable of producing TTL compatible square
wave.
3. The dual supply is in the range of ±6V to ±12V.
4. The IC can also be operated from single supply in the range 12V to
24V.
Features:
Frequency range - 0.1 Hz-500 Hz
Input impedance - 10 ΚΩ
Output sink current - 1 mA
Output source current - 10 mA
APPLICATION OF PLL-
1) FM Demodulation
2) AM Demodulation
3) Frequency multiplier
4) Frequency synthesizer
FM Demodulator using 565:
1. The operation of FM demodulation using PLL
2. The FM signal is applied to PLL.
3. As the PLL is locked to the FM signal, the VCO start tracking instantaneous
frequency in the input FM signal.
4. The error voltage produced at the output of the error amplifier is directly
proportional to the frequency deviation.
5. Thus the ac component of the error voltage represents the modulating
signal.
6. Demodulation FM output is obtained at the output of the error amplifier.
AM Demodulation-
1. A PLL may be used to demodulate AM signals as shown in the figure
below.
2. The PLL is locked to the carrier frequency of the incoming AM signal.
3. The output of VCO which has the same frequency as the carrier, but
unmodulated is fed to the multiplier.
4. Since VCO output is always 900 before being fed to the multiplier.
5. This makes both the signals applied to the multiplier and the difference
signals, the demodulated output is obtained after filtering high frequency
components by the LPF. Since the PLL responds only to the carrier
frequencies which are very close to the VCO output, a PLL AM detector
exhibits high degree of selectivity and noise immunity which is not
possible with conventional peak detector type AM modulators.
FREQUENCY MULTIPLIER-
1. shows the block diagram for a frequency multiplier using PLL 565.
i.
2. Here , a divide by N network is inserted between the VCO output
(pin 4) and the phase comparator input (pin 5).
3. Since the output of the divider is locked to the input frequency f i,
the VCO is actually running at a multiple of the input frequency.
4. Therefore, in the locked state, the VCO output frequency f o is given
by,
5. F0 =Nfi
6. By selecting proper divider by N network, we can obtain desired
multiplication.
7. For example, to obtain output frequency fo = 6 fi ,a divide by N
should be equal to 6.
FREQUENCY SYNTHESIZER-
1. The Block Diagram of Frequency Synthesizer using PLL that can
produce a precise series of frequencies that are derived from a
stable crystal controlled oscillator.
2. The Fig. 2.130 shows the Frequency Synthesizer Block Diagram. It is
similar to frequency multiplier circuit except that divided by M
network is added at the input of phase lock loop.
3. The frequency of the crystal-controlled oscillator is divided by an
integer factor M by divider network to produce a frequency f osc/M,
where fosc is the frequency of the crystal controlled oscillator.
4. The VCO frequency fVCO is similarly divided by factor N by divider
network to give frequency equal to fvco/N.
5. When the PLL is locked in on the divided-down oscillator frequency,
we will have fosc/M = fvco/N, so that fvco=(N/M)fosc.
