Advanced Computer Architecture
5MD00 / 5Z033
MIPS
Instruction-Set Architecture
Henk Corporaal
www.ics.ele.tue.nl/~heco/courses/aca
TUEindhoven
2011
Topics
Instructions & MIPS instruction set
Where are the operands ?
Machine language
Assembler
Translating C statements into Assembler
For details see the book (ch 2):
Main Types of Instructions
Arithmetic
Memory access instructions
Integer
Floating Point
Load & Store
Control flow
Jump
Conditional Branch
Call & Return
MIPS arithmetic
Most instructions have 3 operands
Operand order is fixed (destination first)
Example:
C code:
A = B + C
MIPS code: add $s0, $s1, $s2
($s0, $s1 and $s2 are associated with variables by
compiler)
MIPS arithmetic
C code:
A = B + C + D;
E = F - A;
MIPS code: add $t0, $s1, $s2
add $s0, $t0, $s3
sub $s4, $s5, $s0
Operands must be registers, only 32 registers
provided
Design Principle: smaller is faster.
Why?
Registers vs. Memory
Arithmetic instruction operands must be registers,
only 32 registers provided
Compiler associates variables with registers
What about programs with lots of variables ?
CPU
Memory
register file
IO
Register allocation
Compiler tries to keep as many variables in registers
as possible
Some variables can not be allocated
large arrays (too few registers)
aliased variables (variables accessible through pointers in C)
dynamic allocated variables
heap
stack
Compiler may run out of registers => spilling
Memory Organization
Viewed as a large, single-dimension array, with an
address
A memory address is an index into the array
"Byte addressing" means that successive
addresses are one byte apart
8 bits of data
0
1
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
...
Memory Organization
Bytes are nice, but most data items use larger "words"
For MIPS, a word is 32 bits or 4 bytes.
0
32 bits of data
32 bits of data
32 bits of data
...
12
32 bits of data
Registers hold 32 bits of data
232 bytes with byte addresses from 0 to 2 32-1
230 words with byte addresses 0, 4, 8, ... 2 32-4
address
Memory layout: Alignment
0
4
8
12
31
23
15
this word is aligned; the others are not!
16
20
24
Words are aligned
What are the least 2 significant bits of a word
address?
Instructions: load and store
Example:
C code:
A[8] = h + A[8];
MIPS code:
lw $t0, 32($s3)
add $t0, $s2, $t0
sw $t0, 32($s3)
Store word operation has no destination (reg) operand
Remember arithmetic operands are registers, not
memory!
Our First C code translated
Can we figure out the code?
swap(int v[], int k);
{ int temp;
temp = v[k]
v[k] = v[k+1];
v[k+1] = temp;
}
swap:
muli
add
lw
lw
sw
sw
jr
Explanation:
index k : $5
base address of v: $4
address of v[k] is $4 + 4.$5
$2 ,
$2 ,
$15,
$16,
$16,
$15,
$31
$5, 4
$4, $2
0($2)
4($2)
0($2)
4($2)
So far weve learned:
MIPS
loading words but addressing bytes
arithmetic on registers only
Instruction
Meaning
add $s1, $s2, $s3
sub $s1, $s2, $s3
lw $s1, 100($s2)
sw $s1, 100($s2)
$s1 = $s2 + $s3
$s1 = $s2 $s3
$s1 = Memory[$s2+100]
Memory[$s2+100] = $s1
Machine Language: R-type instr
Instructions, like registers and words of data, are also 32 bits long
Example: add $t0, $s1, $s2
Registers have numbers: $t0=9, $s1=17, $s2=18
Instruction Format:
op
rs
rt
rd
000000
10001
10010
01000
5 bits
5 bits
6 bits
Can you guess what the field names stand for?
5 bits
shamt
00000
5 bits
funct
100000
6 bits
Machine Language: I-type instr
Consider the load-word and store-word instructions,
Introduce a new type of instruction format
What would the regularity principle have us do?
New principle: Good design demands a compromise
I-type for data transfer instructions
other format was R-type for register
Example: lw $t0, 32($s2)
35
18
op
rs
rt
32
16 bit number
Control
Decision making instructions
alter the control flow,
i.e., change the "next" instruction to be executed
MIPS conditional branch instructions:
bne $t0, $t1, Label
beq $t0, $t1, Label
Example:
if (i==j) h = i + j;
bne $s0, $s1, Label
add $s3, $s0, $s1
Label:
....
Control
MIPS unconditional branch instructions:
j label
Example:
if (i!=j)
h=i+j;
else
h=i-j;
Lab2:
...
beq $s4, $s5, Lab1
add $s3, $s4, $s5
j Lab2
Lab1:
sub $s3, $s4, $s5
Can you build a simple for loop?
So far (including J-type instr):
Instruction Meaning
add $s1,$s2,$s3
sub $s1,$s2,$s3
lw $s1,100($s2)
sw $s1,100($s2)
bne $s4,$s5,L
beq $s4,$s5,L
j Label
Next
$s1 = $s2 + $s3
$s1 = $s2 $s3
$s1 = Memory[$s2+100]
Memory[$s2+100] = $s1
Next instr. is at Label if $s4 $s5
Next instr. is at Label if $s4 = $s5
instr. is at Label
Formats:
R
op
rs
rt
rd
op
rs
rt
16 bit address
op
shamt
26 bit address
funct
Control Flow
We have: beq, bne, what about Branch-if-less-than?
New instruction:
meaning:
if $s1 < $s2 then
$t0 = 1
slt $t0, $s1, $s2
$t0 = 0
else
Can use this instruction to build "blt $s1, $s2, Label"
can now build general control structures
Note that the assembler needs a register to do this,
use conventions for registers
Used MIPS compiler conventions
Name Register number
Usage
0
the constant value 0
$zero
2-3
values for results and expression evaluation
$v0-$v1
4-7
arguments
$a0-$a3
8-15
temporaries
$t0-$t7
16-23
saved (by callee)
$s0-$s7
24-25
more temporaries
$t8-$t9
28
global pointer
$gp
29
stack pointer
$sp
30
frame pointer
$fp
31
return address
$ra
Small Constants: immediates
Small constants are used quite frequently (50% of operands)
e.g., A = A + 5;
B = B + 1;
C = C - 18;
MIPS Instructions:
addi
slti
andi
ori
$29,
$8,
$29,
$29,
$29,
$18,
$29,
$29,
4
10
6
4
How about larger constants?
We'd like to be able to load a 32 bit constant into a register
Must use two instructions; new "load upper immediate" instruction
lui $t0, 1010101010101010
filled with zeros
1010101010101010
0000000000000000
Then must get the lower order bits right, i.e.,
ori $t0, $t0, 1010101010101010
ori
1010101010101010
0000000000000000
0000000000000000
1010101010101010
1010101010101010
1010101010101010
Assembly Language vs. Machine Language
Assembly provides convenient symbolic representation
much easier than writing down numbers
e.g., destination first
Machine language is the underlying reality
e.g., destination is no longer first
Assembly can provide 'pseudoinstructions'
e.g., move $t0, $t1 exists only in Assembly
would be implemented using add $t0,$t1,$zero
When considering performance you should count real
instructions
Addresses in Branches and Jumps
Instructions:
bne $t4,$t5,Label Next instruction is at Label if $t4 $t5
beq $t4,$t5,Label Next instruction is at Label if $t4 = $t5
j LabelNext instruction is at Label
Formats:
I
op
op
rs
rt
16 bit address
26 bit address
Addresses are not 32 bits
How do we handle this with load and store instructions?
Addresses in Branches
Instructions:
bne $t4,$t5,Label
beq $t4,$t5,Label
Formats: use I-type
I
Next instruction is at Label if $t4 $t5
Next instruction is at Label if $t4 = $t5
op
rs
rt
16 bit address
Could specify a register (like lw and sw) and add it to address
use Instruction Address Register (PC = program counter)
most branches are local (principle of locality)
Jump instructions just use high order bits of PC
address boundaries of 256 MB
To summarize:
To summarize:
Category
Arithmetic
Instruction
MIPS assembly language
add
Example
add $s1, $s2, $s3
Meaning
$s1 = $s2 + $s3
Three operands; data in registers
subtract
sub $s1, $s2, $s3
$s1 = $s2 - $s3
Three operands; data in registers
$s1 = $s2 + 100
$s1 = Memory[$s2 + 100]
Memory[$s2 + 100] = $s1
$s1 = Memory[$s2 + 100]
Memory[$s2 + 100] = $s1
Used to add constants
addi $s1, $s2, 100
lw $s1, 100($s2)
load word
sw $s1, 100($s2)
store word
lb $s1, 100($s2)
Data transfer load byte
sb $s1, 100($s2)
store byte
load upper immediate lui $s1, 100
add immediate
Conditional
branch
Unconditional jump
$s1 = 100 * 2
16
Comments
Word from memory to register
Word from register to memory
Byte from memory to register
Byte from register to memory
Loads constant in upper 16 bits
branch on equal
beq
$s1, $s2, 25
if ($s1 == $s2) go to
PC + 4 + 100
Equal test; PC-relative branch
branch on not equal
bne
$s1, $s2, 25
if ($s1 != $s2) go to
PC + 4 + 100
Not equal test; PC-relative
set on less than
slt
$s1, $s2, $s3
if ($s2 < $s3) $s1 = 1;
else $s1 = 0
Compare less than; for beq, bne
set less than
immediate
slti
jump
j
jr
jal
jump register
jump and link
$s1, $s2, 100 if ($s2 < 100) $s1 = 1;
Compare less than constant
else $s1 = 0
2500
$ra
2500
Jump to target address
go to 10000
For switch, procedure return
go to $ra
$ra = PC + 4; go to 10000 For procedure call
MIPS (3+2) addressing modes overview
1. Immediate addressing
op
rs
rt
Immediate
2. Register addressing
op
rs
rt
rd
...
funct
Registers
Register
3. Base addressing
op
rs
rt
Memory
Address
Register
Byte
Halfword
4. PC-relative addressing
op
rs
rt
Memory
Address
PC
Word
5. Pseudodirect addressing
op
Address
PC
Memory
Word
Word
Intermezzo: another approach 80x86
see intel museum: www.intel.com/museum/online/hist_micro/hof
1978: The Intel 8086 is announced (16 bit architecture)
1980: The 8087 floating point coprocessor is added
1982: The 80286 increases address space to 24 bits, +instructions
1985: The 80386 extends to 32 bits, new addressing modes
1989-1995: The 80486, Pentium, Pentium Pro add a few instructions
(mostly designed for higher performance)
1997: Pentium II with MMX is added
1999: Pentium III, with 70 more SIMD instructions
2001: Pentium IV, very deep pipeline (20 stages) results in high freq.
2003: Pentium IV Hyperthreading
2005: Multi-core solutions
2008: Low power ATOM: about 1 Watt
2009: Lincroft: integrated graphics
Note: AMD has competitive processors
A dominant architecture: 80x86
See your textbook for a more detailed description
Complexity:
Instructions from 1 to 17 bytes long
one operand must act as both a source and destination
one operand can come from memory
complex addressing modes
e.g., base or scaled index with 8 or 32 bit displacement
Saving grace:
the most frequently used instructions are not too difficult to
build
compilers avoid the portions of the architecture that are slow
Starting a program
Compile and Assemble C program
Link
insert library code
determine addresses of data and instruction labels
relocation: patch addresses
Load into memory
load text (code)
load data (global data)
initialize $sp, $gp
copy parameters to the main program onto the stack
jump to start-up routine
copies parameters into $ai registers
call main
Starting a program
C program
compiler
Assembly program
assembler
Object program (user module)
Object programs (library)
linker
Executable
loader
Memory
