Emerging Trends in VLSI Design

A big Question..???

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 Moore’s Law
 Moore’s Law: Processor speed / number
transistors doubling approximately 18
months
 Cramming More Components onto
Integrated Circuits
 Future of Electronics – Future of ICs

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 Costs Curves and Yield

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 Heat Problem..

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 State Encoding for a Counter
 Two-bit binary counter:
 State sequence, 00 → 01 → 10 → 11 → 00
 Six bit transitions in four clock cycles
 6/4 = 1.5 transitions per clock

 Two-bit Gray-code counter

 State sequence, 00 → 01 → 11 → 10 → 00
 Four bit transitions in four clock cycles
 4/4 = 1.0 transition per clock

 Gray-code counter is more power efficient.

G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:
Kluwer Academic Publishers (now Springer), 1998.

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 Binary Counter: Original
Encoding
a
Present
Next state
state A
b
a b A B B
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0

A = a’b + ab’ = a xor b CK

B = a’b’ + ab’ = b’ CLR
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 Binary Counter: Gray Encoding
Present a
Next state
state A
a b A B
B
0 0 0 1 b
0 1 1 1
1 0 0 0
1 1 1 0

A = a’b + ab = b CK
B = a’b’ + a’b = a’ CLR
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 Three-Bit Counters
Binary Gray-code
State No. of toggles State No. of toggles
000 - 000 -
001 1 001 1
010 2 011 1
011 1 010 1
100 3 110 1
101 1 111 1
110 2 101 1
111 1 100 1
000 3 000 1
Av. Transitions/clock = 1.75 Av. Transitions/clock = 1
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 Moore’s Law

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 Pentium 4
 Introduction date: November
20, 2000
 1.4 GHz clock
 fabricated in 180 nm process,
 42 mln transistors)

 In 2002 (2 GHz in 130 nm,

55 mln transistors)
 In 2005 (3.8 GHz in 90 nm,
125 mln transistors)
 Typical Use: Desktops and
entry-level workstations
Evolution of Electronics
SIA Roadmap for Processors (1999)
Year 1999 2002 2005 2008 2011 2014

Feature size (nm) 180 130 100 70 50 35

Logic transistors/cm2 6.2M 18M 39M 84M 180M 390M

Clock (GHz) 1.25 2.1 3.5 6.0 10.0 16.9

Chip size (mm2) 340 430 520 620 750 900

Power supply (V) 1.8 1.5 1.2 0.9 0.6 0.5

High-perf. Power (W) 90 130 160 170 175 183

Source: http://www.semichips.org
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Moore’s law in Microprocessors
1000

100 2X growth in 1.96 years!

Transistors (MT)

10
P6
Pentium® proc
1 486
386
0.1 286
8085 8086
0.01 8080
8008
4004
0.001
1970 1980 1990 2000 2010
Year
Transistors on Lead Microprocessors double every 2 years

Courtesy, Intel
 Frequency

CMOS
nMOS

Lead Microprocessors frequency doubles every 2 years

Courtesy, Intel
 Why Scaling?
 Technology shrinks by 0.7/generation
 With every generation can integrate 2x more functions
per chip for about the same $/chip
 Cost of a function decreases by 2x
 But …
 How to design chips with more and more functions?
 Design engineering population does not double
every two years…
 Hence, a need for more efficient design methods
 Exploit different levels of abstraction
 Moore’s Law
 Recent research predicts an end to
Moore’s Law in 2018
 Most of Moore’s law is based upon shrinking
the dimensions of the transistors on the chip
 But the laws of physics do not allow transistor
technology to operate be

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 Physical Limitations
 Current processors are starting to be
manufactured on a 0.045 micron process
 1 micron = 1 millionth of a meter
 0.045 micron process = 45 nanometers,
nanometers is a billionth of a meter
1 nanometers is the width of about 3 silicon atoms

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 Size

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 Physical Limitations
 Physical limitation at a 0.016 micron
process
 16 nanometers
 Smaller than this quantum effects begin to
take over, electronics becomes unpredictable
 If Moore’s Law continues to hold, we’ll hit
16nm in 2018

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 Recent Data

Source: http://www.eetimes.com/story/OEG20040123S0041
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 Physical Limitations
 At 16nm, the distance between the source
and drain is approximately 5 nm

Electron tunneling may occur with 50% probability from source to drain
even if the gate is closed. Heisenberg uncertainty principle. Analogy: A
light misty waterfall; some people may walk through, or go around.
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 Moore’s Law & Gate Length

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 Moore’s Law

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 Are we nearing end?
 Not necessarily! Lots of new contenders for the
(distant?) future

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 ISSCC, Feb. 2001, Keynote
“Ten years from now,
microprocessors will run at
10GHz to 30GHz and be capable
of processing 1 trillion operations
per second – about the same
number of calculations that the
world's fastest supercomputer
can perform now.
Patrick P. Gelsinger
Senior Vice President
General Manager
“Unfortunately, if nothing
Digital Enterprise Group changes these chips will produce
INTEL CORP. as much heat, for their
proportional size, as a nuclear
reactor. . . .”

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 Low-Power Design
 Design practices that reduce power
consumption by at least one order of
magnitude; in practice 50% reduction
is often acceptable.
 Low-power design methods:
 Algorithms and architectures
 High-level and software techniques
 Gate and circuit-level methods
 Test power
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 finFET based Design

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 Introduction
Double-gate FET (DGFET)

->Reduce Short Channel Effects (SCEs)

->Reduce Drain-Induced-Barrier-Lowering
->Improve Subthreshold Swing S

Medici-predicted DIBL and subthreshold swing versus

effective channel length for DG and bulk-silicon nFETs
 INTRODUCTION TO FINFET
 The term “FINFET” describes a non-
planar, double gate transistor built on an
SOI substrate, based on the single gate
transistor design.
 The important characteristics of FINFET is
that the conducting channel is wrapped by
a thin Si “fin”, which forms the body of the
device.
 The thickness of the fin determines the
effective channel length of the device.
 HISTORY OF FINFET
 FINFET is a transistor design first developed by Chenming Hu
and his colleagues at the University of California at Berkeley,
which tries to overcome the worst types of SCE(Short
Channel Effect).

 Originally, FINFET was developed for use on Silicon-On-

Insulator(SOI).

 SOI FINFET with thick oxide on top of fin are called “Double-
Gate” and those with thin oxide on top as well as on sides are
called “Triple-Gate” FINFETs
REASON FOR EVOLUTION OF
FINFET
 For the double gate SOI MOSFETs, the gates control the
energy barrier b/w source and drain effectively.

 Therefore, the Short Channel Effect(SCE) can be

suppressed without increasing the channel impurity
concentration.
 GENERAL LAYOUT & MODE OF
OPERATION
 The basic electrical layout and mode of operation of a FINFET
does not differ from a traditional FET.

 There is one source and one drain contact as well as a gate

to control the current flow.

 In contrast to planar MOSFET, the channel b/w source and

drain is build as 3D bar on top of the Si substrate and are
called fin.
 CONTINUED………
The gate electrode is then wrapped around the channel, so
that there can be formed several gate electrodes on each
side which leads to the reduction in the leakage currents and
an enhanced drive current.
 “FINS”
 The fin is used to form the raised channel.

 As the channel is very thin the gate has a great control over
carriers within it, but, when the device is switched on, the
shape limits the current through it to a low level.

 The thickness of the fin (measured in the direction from

source to drain) determines the effective length of the device.
Three Types of Double-gate FET

Quasi-CMOS structure
Relatively simple FAB
 Improved and reproducible fin height control while providing isolation
between source and drain regions of the FinFET device.

 A finFET device is fabricated using a conventional MOSFET technology. The

device is fabricated in a silicon layer overlying an insulating layer (SIMOX)
with the device extending from insulating layer as a fin.

 Double gates are provided over the sides of the channel to provide enhanced
drive current and effectively suppressed short channel effects. A plurality of
channels can be provided for increased current capacity.

 In one embodiment we can also use two transistors that can be stacked to a fin
to provide CMOS process having a shared gate
First FinFET - DELTA (DEpleted Lean-channel
TrAnsistor)
-> THE FIRST fabricated fin field-effect transistor (FinFET)-like
silicon- on-insulator (SOI) MOS device dates back to 1989,
which is known as the fully depleted lean-channel transistor.

-> With the continuous scaling of MOS devices into the 45-nm
technology node, non-planar double-gate (DG) MOSFETs (such as
FinFETs) have become attractive for their good control of
short channel effects and high current drive.

-> However, parasitic resistive or capacitive components become

comparable in magnitude to, or even much larger than intrinsic
ones.
 Design - Geometry
Hfin >> Tfin
Top gate oxide thickness >> sidewall oxide thickness

Effective channel length Leff = Lgate + 2×Lext

Effective channel width W = Tfin + 2×Hfin
 Fabrication
6.5 nm Si fin by Berkeley
Team
---- Smallest in 2002

Poly-Si

Si fin

43

Yang-Kyu Choi et al., Solid-State Electronics 46, p1595-1601, 2002

 Fabrication - Process Flow
“Easy in concept----Tough to build”

(a) SiN is deposited as a hard mask,

SiO2 cap is used to relieve the stress.

(b) Si fin is patterned

(c) A thin sacrificial SiO2 is grown

(d) The sacrificial oxide is stripped

completely to remove etch damage

(e) Gate oxide is grown

(f) Poly-Si gate is formed

10 nm gate length, 12 nm fin width

44

Chenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002

 Performance

45

Chenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002

 Performance - IV
Characteristics

•The drive currents are 446 uA/um for n-FinFET and 356 uA/um for
p-FinFET respectively

46

Chenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002

 Performance - Speed and
Leakage

•Gate Delay is 0.34 ps for n-FET and 0.43 ps for p-FET respectively at 10 nm Lg
•Gate leakage current is comparable to planar FET with the same gate oxide
thickness
47

Chenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002

 Performance - Short Channel
Effects

•The subthreshold slope is 125 mV/dec for n-FET and 101 mV/dec for p-FET
respectively
•The DIBL is 71 mV/V n-FET and 120 mV/V for p-FET respectively
48

Chenming Hu, et al. Dept. of EECS, UC-Berkeley, IEDM, p251-254, 2002

 Summary
“Easy in concept----Tough to build”

 Double-gate FET can reduce Short Channel

Effects and FinFET is the leading DGFET
 Optimization design includes geometry, S-D fin-
extension doping, dielectric thickness scaling,
threshold voltage control….
 Fabrication of FinFET is compatible with CMOS
process
 10 nm gate length, 12 nm fin width device has
been fabricated and shows good performance
49
 ADVANTAGES OF FINFET
 Higher technological maturity than planar
DG.
 Suppressed Short Channel Effect(SCE)
 Better in driving current
 More compact
 Low cost
DISADVANTAGES OF FINFET
 Reduced mobility for electrons
 Higher source and drain resistances
 Poor reliability
 CARBON NANO-TUBE FIELD
EFFECT TRANSISTOR

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 Definition:
Carbon Nanotube and Carbon fiber
 The history of carbon fiber goes way
back…

 The history of carbon nanotube starts from

1991

Institute of Optics, University of Rochester 53

 Carbon nanotube
CNT: Rolling-up a graphene sheet to form a
tube

Schematic STM image

of a CNT of CNT

Institute of Optics, University of Rochester 54

 Is there a DIGITAL future for nanotubes?

55
 Carbon nanotube FETs: model structures

SB-CNFET
K. Alam et al., APL, 87, 073104, 2005

C-CNFET
D.L. Pulfrey et al., IEEE TNT, 2007

56
 Si MOSFET and CNFET: comparison

W Lg Tox gm Cgg Ft
FET Status (um) (nm) (nm) (mS) (aF) (THz)

Si MOS Exptl. (IBM) 80 27 1.05 108 52 0.33

C-CN Theor.
coax (UBC) 80 7 2 448 37 1.93

Note the gm superiority is about four times

57
 CN biomolecular sensors

CARBON
NANOTUBES:
• size compatibility with
biomolecules,
• exposed surface,
• interactions that modify
band structure,
• change in LDOS.

Gruner, Anal. Bioanal.58

Chem., 384, 322, 2006
 Benefits of CNFETs

High single crystallinity

 Low defect density, grain boundary free
Predictable electron transport properties
 Reliable device performance
Unique properties due to quantum confinement effects
 Enhancement in device characteristics
Potential to revolutionize nano-scale science and technology

59
 Advantages of CNTs over Silicon
 As Silicon transistors are scaled down the doping of
the channel has to increase proportionately while its
volume decreases. The change in the number of
dopants produces important differences in switching
properties and degrades the overall performance of
the system.
 Nanotube transistors can operate even without
dopants and are less sensitive to differences in the
channel length. Instead, CNFETs depend on the
diameter of the tube and its chirality.

60
 CNT Challenges
 The production methods available for CNTs either
produce CNTs with widely varying sizes and chiralities or
are prohibitively expensive.
 Exposure to open air can cause an n-type CNT to revert
back to p-type.
 Placing CNTs on substrate is also a big challenge.
Some prospective solutions are DNA Self-Assembly and
using a electric field to direct CNT growth during
Chemical Vapor Deposition.
 The main obstacle to CNTs replacing Silicon transistors
is that there are no mass production methods available
for CNTs to rival the well-developed Silicon and
photolithography process at present.

61
 The Future
 Medium term (5-10 years)
- Memory devices
- Fuel cells, batteries
- Biosensors (CNT, molecular)
- Biomedical devices
- Advances in gene sequencing

 Long term (> 15 years)

- Nanoelectronics (CNT)
- Molecular electronics
- Use in new aerospace and automotive industry
composites
62
 Faster Transistors

 researchers hope to make graphene

transistors
 10 nm across and one atom high
 Faster than field-effect transistors.
 Lose very little energy from scattering or colliding
with atoms in the lattice, so less heat is generated
 Power Consumption Problems
1. Thermal management/package issues may
limit integration density.
2. IC usage of electricity at an inflection point.
• ICs use a few % of world’s electricity today and
growing exponentially.
• Power per chip is growing.
• IC units in use also growing.
3. Need to reduce IC power consumption with
architecture and circuit innovations, and a
low voltage transistor.

6/2009 Chenming Hu
 IC Power Consumption Rising Much Faster Than
Past Trend

 Because power consumption Vdd2

 and Vdd (operation voltage) scaling has
slowed.
Technology 0.25 0.18 0.13 90 65 45 32 22 16
Node μm μm μm nm nm nm nm nm nm

Vdd 2.5 V 1.8 V 1.3 V 1.2 V 1.1 V 1.0 V 0.9 V 0.8 V 0.7 V

High Performance ITRS Roadmap

6/2009 Chenming Hu
 Reversible Computation

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 Information is Physical
 Is some minimum amount of energy
required per one computation step?
A
B AB

• Rolf Landauer, 1961. Whenever we use a logically

irreversible gate we dissipate energy into the
environment.
A A
B reversible AB
 Information loss = energy loss
 The loss of information is associated with laws
of physics requiring that one bit of information
lost dissipates k T ln 2 of energy,
 where k is Boltzmann’ constant
 and T is the temperature of the system.

 Interest in reversible computation arises from

the desire to reduce heat dissipation, thereby
allowing:
 higher densities
 higher speed
 Solution = Reversibility
 Charles Bennett, 1973: There are no
unavoidable energy consumption
requirements per step in a computer.
 Power dissipation of reversible circuit, under
ideal physical circumstances, is zero.

• Tomasso Toffoli, 1980: There exists a reversible

gate which could play a role of a universal gate for
reversible circuits.
A Reversible A
and B
B
universal
C  AB
C
 Reversible computation
 Landauer/Bennett: all operations required in
computation could be performed in a reversible
manner, thus dissipating no heat!
 The first condition for any deterministic device to
be reversible is that its input and output be uniquely
retrievable from each other - then it is called logically
reversible.
 The second condition: a device can actually run
backwards - then it is called physically reversible.
 and the second law of thermodynamics guarantees
that it dissipates no heat. Billiard Ball Model
 Reversible logic
INPUTS OUTPUTS
Reversible are circuits
(gates) that have 000 000
2 4
one-to-one mapping 001 001
36
010 010
between vectors of
011 011 42
inputs and outputs; 100 100
thus the vector of 53
101 101
input states can be 110 110 65

always reconstructed 111 111

(2,4)
from the vector of (3,6,5)
output states.
 Feynman Gate P Q

 When A = 0 then Q = B, when A = +

1 then Q = B’.
 Every linear reversible function can
be built by composing only 2*2
Feynman gates and inverters
A B
 With B=0 Feynman gate is used as
a fan-out gate. (Copying gate)
A A
A A

+ +

A 0
A 1
 Fredkin Gate
 Fredkin Gate is a fundamental
concept in reversible and quantum
computing.
 Every Boolean function can be build
from 3 * 3 Fredkin gates:
P = A,
Q = if A then C else B,
R = if A then B else C.
 Useful Notation for Fredkin Gate

Fredkin Gate Inverse Fredkin Gate

C C C
C
P C’P+CQ P
C’P+CQ
Q CP+C’Q Q
CP+C’Q

In this gate the input signals P and Q are routed to the same or
exchanged output ports depending on the value of control signal C

Fredkin gate is conservative and it is its own invers

 Operation of the Fredkin gate
C C
0 0 1 1
A AC’+BC A A A B
B BC’+AC B B B A

A A A A A A
0 AB B A+B 0 A
B 1 1 A’
 A 4-input Fredkin gate
X 0 0
X
A AX’+CX A A
B BX’+AX
B B
CX’+BX
C C C

1 1 A A
A C B A+B
B A 0 AB
C B 1 A’
 Reversible logic:
Garbage

 A reversible circuit without constants on

inputs realizes on all outputs only balanced
functions.
 Therefore, reversible circuit can realize
unbalanced functions only with additional
inputs and garbage outputs.
Minimal Full Adder Using Fredkin Gates
A
carry
B

C
1
sum
0

In this gate the input signals P and Q are routed to

the same or exchanged output ports depending
on the value of control signal C

3 garbage bits
 Switch Gate
Switch Gate Inverse Switch Gate

CP CP

P C C P

C C’P C’P C

In this gate the input signal P is routed

to one of two output ports depending on
the value of control signal C
Interaction Gate
Inverse interaction
Interaction Gate
Gate
AB AB
A A
A’B A’B

B AB’ AB’ B
AB AB

In this gate the input signals are routed

to one of two output ports depending on
the values of A and B
 Gate Having 18 Distinct
Cofactors
P = 1  AB  AC  BC
Q = A  C  AB  AC  BC
R = A  B  AB  AC  BC
if A=0 then if A=1 then if B=0 then
P= 1  BC P=1  B  C  BC P=1  AC
Q=C  BC Q=1  B  BC Q=A  C 
AC
R=B  BC R=1  C  BC R=A  AC

if B=1 then if C=0 then if C=1 then

P=1  A  C  AC P=1  AB P=1  A  B 
AB
Q=AC Q=A  AB Q=1  B  AB
 3*3-gate, universal in two Output
Inputs
arguments (ULM-2)
A=1, B=0, C=y P=0
A=x, B=y, C=1 P=x’y’
A B C P Q R
A=x, B=y, C=1 Q=x’y
0 0 0 1 1 0
0 0 1 1 0 1 A=x, B=0, C=y P=x’

0 1 0 1 0 0 A=1, B=x, C=y P=xy’

0 1 1 0 1 1 A=x, B=1,C=y P=y’
1 0 0 0 1 0 A=x, B=1, C=y Q=x  y
1 0 1 0 0 0 A=0, B=x, C=y P=x’+y’
1 1 0 1 1 1 A=x, B=y, C=0 R=xy
1 1 1 0 0 1
A=0, B=x, C=y Q=(x  y)’
A=0, B=x, C=y R=y
A=x, B=y, C=0 P=x’+y
A=1, B=x, C=y R=x
A=x, B=y, C=0 Q=x+y’
A=x, B=1, C=y R=x+y
A=1, B=1, C=y R=1
 Goals of reversible logic
synthesis
1. Minimize the garbage
2. Minimize the width of the circuit
(the number of additional inputs)
3. Minimize the total number of gates
4. Minimize the delay
 Conclusions
Reversible
Computing is an
attractive research
area.
YOU’LL LIKE THEM!
 Reconfigurable Computing

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 Informal Definition

 A computer is a machine that computes

 add, subtract, logical operations, decisions

 What have we learned about computing –

Student grading?
 Calculating Class Grades*
grade = 0.1  mt1 + 0.2  mt2
+0.3  hw + 0.4  proj;

grade = 0;
tmp = 0.1  mt1;
grade = grade + tmp;
tmp = 0.2  mt2; Time
grade = grade + tmp;
tmp = 0.3  hw;
grade = grade + tmp;
tmp = 0.4  proj;
grade = grade + tmp;

*This is not how we are going to calculate your grades

 Computing Final Grade (2)
0.1 mt1 0.2 mt2 0.3 hw 0.4 proj

× × × ×

+ +
+ Time
grade

SPACE
 2 Ways to Compute
0.1 0.1 0.2 0.2 0.4 0.4

mt1 mt1 mt2 mt2 proj proj

tmp
× tmp
+ tmp
× tmp
+ tmp
+ tmp

grade grade grade grade grade grade

clock cycle 1 clock cycle 2 clock cycle 3 clock cycle n
TIME

× Processor (61C)
+
×
+
×
+ Application Specific Integrated Circuit
× ASIC (ee141)
 Processor vs ASIC

 Take longer to  Take shorter time to

compute compute
 slow  fast
 Flexible  Not Flexible
 Need instructions to  No instruction
determine what to do  Same calculation
on each cycle every cycle
 Space is bounded  Space unbounded
 Branches?
Temporal Computing Spatial Computing
 Visualizing Spatial Computing

Actual computation
 AMD Opteron 64-bit processor  Full Custom ASIC
 1MB L2 Cache  4x4 SVD Decomposition
 193 mm sq  3.5 mm sq
 0.18 micron CMOS  90nm CMOS
 89W @ 1.8GHz  34mW @ 100 MHz clock
 ~3 Op / cycle (int op)  70 GOPS = 700 Op / cycle
 Between Temporal & Spatial Computing

Single ASIC
Processor

Temporal
? Spatial

• Slow Reconfigurable • Fast

• Flexible Computing • Inflexible
 Reconfigurable Computing
 No standard definition
 “Computing via a post-fabrication and spatially
programmed connection of processing elements.”
-John Wawrzynek Sp04
 A computer that can RE-configure itself to
perform computation spatially as needed
 How often do we RE-configure?

 Example: FPGA
 Introduction to FPGA
 Field Programmable Gate Array
 Began as ASIC replacements
 ASIC that can be configured “in the field”
 At power up, configuration is load to the chip
 Chip acts as an ASIC until power down

 Modern FPGA more like computers

 Exploit dynamic, partial reconfiguration
 Embedded processors

 Xilinx, Altera are 2 major market leaders

 The LUT
 LUT: Lookup Table
 A direct implementation of a truth table
 Recall a TT uniquely defines a circuit
A B C D Q
0 0 0 0 0
0 0 0 1 0
…
1 1 0 1 1
1 1 1 0 0
1 1 1 1 0

 An n-LUT implements any n-input combinational

logic
 Depends on LUT configuration
 Sequential logic
 Connecting multiple LUT’s gives us ANY
combinational logic we want to implement
 We need Flip-Flop to build sequential circuits
CL CL
clk

 FF so important that they are included natively

on FPGA next to each LUT
 LUT + FF + … = LB (Logic Block)
 Logic Block
1
D3 OUT
D2 0
LUT FF
D1
D0

LUTCFG CLK MUXCFG

 Can build any 4-input circuit

 Synchronous OR Asynchronous
 Combining Logic Blocks => ANY synchronous
digital circuit
 How to we build bigger circuit?
 Routing of FPGA
LB LB LB LB

LB LB LB LB

LB LB LB LB

 With enough smartness in placement and

routing, we can implement any synchronous
digital circuits!
 Conclusion

 Processor is NOT the only way to compute

 Reconfigurable computers allows different
tradeoffs among speed, flexibility, cost,
power, etc
 FPGA offers fine-grain reconfigurability
 Executing algorithms
Hardware Reconfigurable Software-programmed
(Application Specific computing processors
Integrated Circuits)

Advantages: Advantages: Advantages:

•very high •fills the gap •software is very
performance and between hardware flexible to change
efficient and software Disadvantages:
Disadvantages: •much higher •performance can
•not flexible (can’t performance than suffer if clock is not
be altered after software fast
fabrication) •higher level of •fixed instruction set
• expensive flexibility than by hardware
S. Reda EN2911X FALL’07 hardware
 Reconfigurable devices
Programmable
interconnect

Programmable
logic blocks

• Field-Programmable Gate Arrays (FGPAs) are one example of

reconfigurable devices
• An FPGA consists of an array of programmable logic blocks whose
functionality is determined by programmable configuration bits
• The logic blocks are connected by a set of routing resources that
are also programmable
 Custom logic circuits can be mapped to the reconfigurable fabric
S. Reda EN2911X FALL’07
 Conclusion
 The Future?
 “No one knows how much of technology’s
promise will prove out. Technology prediction
has never been too reliable. In the March
1949 edition of Popular Mechanics… experts
predicted computer of the future would add as
many as 5000 numbers per second, weigh
only 3000 pounds, and consume only 10
kilowatts of power.” – Nanotechnology
conference