MEMORIES

Concept of Memory
• Data storage essential for processing
• Binary storage
• Switches Write

'0'
Read
'1'

• How do you implement this in Hardware?

 Requirements
• Easy reading
• Easy Writing
• High density
• Speed, more speed and still more speed
Memory Chip Configuration
Row Address
M
N bits 2 Cells

Memory Cell Array

Complete Address
N+M Bits
Cell
WL N
2 Cells
Row Dec

DL

Din
I/O Interface

din
I/O Control
Dout dout

Column Dec.
Control
Signals
Column Address
M Bits
Semiconductor Memory Classification

Non-Volatile
Read-Write Memory Read-Write Read-Only Memory
Memory
Random Non-Random EPROM Mask-Programmed
Access Access
2
E PROM Programmable (PROM)

SRAM FIFO FLASH

DRAM LIFO
Shift Register
CAM
 ROM
• Non-volatile Data
• Method of Data Writing
• Mask ROM
– Data written during chip fabrication
• PROM
– Fuse ROM: Non-rewritable
– EPROM: Erase data by UV rays
– EEPROM: Erase and write through electrical means
• Speed 2-3 times slower than RAM
• Upper limit on write operations
• Flash Memory – High density, Low Cost
 ROM
• Non-volatile Data
• Method of Data Writing
• Mask ROM
– Data written during chip fabrication
• PROM
– Fuse ROM: Non-rewritable
– EPROM: Erase data by UV rays
– EEPROM: Erase and write through electrical means
• Speed 2-3 times slower than RAM
• Upper limit on write operations
• Flash Memory – High density, Low Cost
 READ-ONLY MEMORIES(ROM)
The read-only memory is a type of semiconductor memory
designed to hold data that either are permanent or will not
change frequently.

For some ROMs, the data that are stored must be built-in
during the manufacturing process; for other ROMs, the data
can be entered electrically.

The process of entering data is called programming or

burning-in the ROM.
ROM Block Diagram
ROM ARCHITECTURE
ROM TIMING
TYPES OF READ-ONLY MEMORIES

 MROM
 PROM
 EPROM
 EEPROM
 FLASH MEMORY
Mask-Programmed ROM (MROM)
You send the ROM manufacturer your data and they
mask it directly to the ROM

Use only when you are selling large volume of a single

product
Positive
• becomes cheaper to use for approximately more than 2000 parts
• components come from chip manufacturer already programmed and tested
taking out a manufacturing step

Negative
• costs several thousand dollars for custom mask
• software changes are costly
• cannot be reprogrammed
Programmable ROMs (PROMs)
Uses fuses that are burned to disconnect a logic 1 and turn it
to a logic 0.
Written to by you using a programmer similar to EPROM
Once it's written to, the data is in there forever.

Positive
• cheaper than EPROM due to cheaper packaging
• more packaging options than EPROM due to less constraints like
erasure window
• standard "off-the-shelf" component
• cheaper than Custom masked ROM up to about 10,000 devices

Negative –
to reprogram, have to throw out the chip - Should only be used for

stable design
 EPROM
In current programmable logic devices, the fuses have been
replaced by floating gate MOS transistors.

The device looks much like an NMOS transistor, but with the
addition of thin floating gate between the usual gate and the
substrate. The floating gate has oxide layers on both sides of it,
which isolates it electrically from its surroundings.
 Non-Volatile Memories
The Floating-gate transistor (FAMOS)

Floating gate Gate

D
Source Drain

tox G

tox
S
n+ p n +_
Substrate

Device cross-section Schematic symbol

Written to only with a programmer.
Erased with ultraviolet light

Advantages
• non-volatile storage without battery
• can write to it, but only with aid of
programmer

Limitations
• programmer requirements
• Expensive
• locations must be erased before writing
 EEPROM

Written to with either

programmer or the
processor (electrically)

Erased with either a

programmer or the
processor (byte-by-byte
electrically)
Written to with either programmer or the processor
(electrically)

Erased with either a programmer or the processor

(byte-by-byte electrically)

Advantages
• non-volatile memory without batteries
• programmable a single-location at a time

Limitations
• Expensive
• only smaller sizes available
• extremely slow write times (10 mS vs. 100 to 200 nS)
 FLASH MEMORY
These memories are basically EEPROMs except that erasure
occurs at the block level in order to speed up the write process

Non-volatile

This makes FLASH work like a fast, solid state hard drive

Advantages
• non-volatile
• higher densities than both SRAM and DRAM

Limitations
• process of storing data is at a block level (and slower)
• data cell must be erased before writing data to it
Trade-offs for semiconductor nonvolatile memories
show that complexity and cost increase as erase and
programming flexibility increases.
 ROM APPLICATIONS

Embedded Microcontroller Program Memory

Bootstrap Memory
Data Tables
Data Converter
Function Generator
 RAM
• Random write and read operation for any cell
• Volatile data
• Most of computer memory

• DRAM
– Low Cost
– High Density
– Medium Speed
• SRAM
• High Speed
• Ease of use
• Medium Cost
 Basic Cells

• DRAM SRAM
VDD

WL
WL
WL

DL
DL
DL
 Static RAM
• SRAM consists essentially of internal latches that store the binary
information.
• The stored information remains valid as long as power is applied to the
unit.
• SRAM is easier to use and has shorter read and write cycles.
– Low density,
– low capacity,
– high cost,
– high speed,
– high power consumption.

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 Dynamic RAM
• DRAM stores the binary information in the form of electric
charges on capacitors.
• The capacitors are provided inside the chip by MOS transistors.
• The capacitors tends to discharge with time and must be
periodically recharged by refreshing the dynamic memory.

30
 Dynamic RAM
• DRAM offers reduced power consumption and larger storage
capacity in a single memory chip.
– High density,
– high capacity,
– low cost,
– low speed,
– low power consumption.

31
RAM ARCHITECTURE
 STATIC RAM (SRAM)
Typical bipolar and NMOS static-RAM cells.
 Static-RAM Timing

Read Cycle:
Write Cycle:
 SRAM IC
MCM6264C CMOS 8K * 8 RAM
 DYNAMIC RAM (DRAM)
Cell arrangement in a
16K * 1 dynamic RAM.
DYNAMIC RAM READ AND WRITE OPERATIONS

WRITE OPERATION : SW1 AND SW2 are closed.

READ AND REFRESH OPERATION: SW3,SW4 and SW2
are closed
Simplified architecture of the TMS44100 4M * 1 DRAM
(a) CPU address bus driving ROM or static-RAM memory;
(b) CPU addresses driving a multiplexer that is used to
multiplex the CPU address lines into the DRAM.
DRAM READ CYCLES
DRAM WRITE CYCLES
EXPANDING WORD SIZE
AND
CAPACITY
 Expanding Word Size

Combining
two 16 * 4
RAMs for a
16 * 8
module.
Eight 2125A 1K * 1RAM chips arranged as a 1K * 8
memory.
 Expanding Capacity
Two chips16*4 for a 32 * 4 memory.
Four 2K * 8 PROMs arranged to form a total capacity of 8K * 8
Memory map of the full system.
FUNDAMENTALS OF PLD CIRCUITRY
 PLD Symbology
The following
functions are
programmed as
 PLD Types

 PROM
 PLA
 PAL
 CPLD
 FPGA
PROM
architecture
makes it
suitable for
PLDs
fuses are blown to
program outputs for
given functions.
 Programmable logic arrays
• A ROM is potentially inefficient because it uses a decoder, which
generates all possible minterms. No circuit minimization is done.
• Using a ROM to implement an n-input function requires
– An n-to-2n decoder, with n inverters and 2n n-input AND gates.
– An OR gate with up to 2n inputs.
– The number of gates roughly doubles for each additional ROM
input.
• A programmable logic array , makes the decoder part of the ROM
“programmable” too. Instead of generating all minterms, you can
choose which products (not necessarily minterms) to generate.
 A blank 3 x 4 x 3 PLA
• This is a 3 x 4 x 3 PLA (3 Inputs
inputs, up to 4 product
terms, and 3 outputs),
ready to be programmed.
• The left part of the OR array
diagram replaces the
decoder used in a ROM.
• Connections can be made
in the “AND array” to
produce four arbitrary
products, instead of 8
minterms as with a ROM.
• Those products can then
be summed together in AND array
the “OR array.”

Outputs
 PLA minimization
• For a PLA, we should minimize the number of product terms
for all functions together.
• We could express V2, V1 and V0 with just four total products:

V2 = xy’z’ + x’z + x’yz’ V1 = x’yz’ + xy V0 = xy’z’ + xy

Y Y Y
0 1 1 1 0 0 0 1 0 0 0 0
X 1 0 0 0 X 0 0 1 1 X 1 0 1 1
Z Z Z

V2 = m(1,2,3,4)
V1 = m(2,6,7)
V0 = m(4,6,7)
 PLA Example
• So we can implement these three functions using a 3 x 4 x 3 PLA:

V2 = m(1,2,3,4) = xy’z’ + x’z + x’yz’

V1 = m(2,6,7) = x’yz’ + xy
V0 = m(4,6,7) = xy’z’ + xy
 Programmable Array Logic (PAL)
Typical PAL
architecture
 PAL
programmed
for the given
functions
 Complex PLD (CPLD)
– Complex Programmable Logic Devices (CPLD)

– SPLDs (PLA, PAL) are limited in size due to the small

number of input and output pins and the limited number
of product terms
• Combined number of inputs + outputs < 32 or so

– CPLDs contain multiple circuit blocks on a single chip

• Each block is like a PAL: PAL-like block
• Connections are provided between PAL-like blocks via an
interconnection network that is programmable
• Each block is connected to an I/O block as well
 Complex PLD (CPLD)
• CPLD architectures consists of
- Macrocells
- configurable flip-flop (D, T, JK or SR)
- Output enable/clock select
- Feedback select
• CPLD has predictable time delay because of hierarchical inter-
connection
• easy to route, very fast turnaround
• performance independent of netlist
• devices is erasable and programmable with non-volatile EPROM
or EEPROM configuration
• wide designer acceptance
• has more logic density than any classical PLDs device
• relatively mature technology, but some innovation still ongoing
Structure of a CPLD: A Closer Look
Section of a CPLD
 Field-Programmable Gate Arrays
• Xilinx FPGAs are based on Configurable Logic Blocks (CLBs)
• More generally called logic cells
• Programmable CLB CLB CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB CLB CLB

I/O blocks
not shown
 What is an FPGA?

• An FPGA is a general-purpose, multi-

level programmable logic device that is
customized in the package by the end
users.
 Field Programmable Gate Array(FPGA)
• FPGA is a general purpose, multi-level programmable logic device
• FPGA is composed of,
logic blocks to implement combinational and
sequential logic circuit

- programmable interconnect wire to connect input

- and output of logic blocks

- I/O blocks logic blocks at periphery of device for

the external connection

•“The routing resources are both the greatest strength and

weakness of the FPGA’s”
 Logic Lookup Table
• LUT is used instead of basic
gates or MUXs
• Specify logic functions to be
implemented as a simple truth
table
• n-input LUT can handle function
of 2n inputs
• A LUT is actually a small (1-bit)
RAM
– FPGA LUTs can be used as RAM
 A Two-Input Lookup Table
LUTs can be implemented using MUXs
We do not normally care about the implementation,
just the functioning
x1 x1

0/1 1
0/1 x1 x 2 f1 0
f f1
0/1 0 0 1 0
0 1 0 1
0/1
1 0 0
x2 1 1 1 x2

(a) Circuit for a two-input LUT (b) f 1 = x1 x2 + x1 x2 (c) Storage cell contents in the LUT
A Three-Input LUT
A simple x1
extension of the x2
two-input LUT 0/1
leads to the figure
0/1
at right
0/1
Again, at this
point we are 0/1
f
interested in 0/1
function and not 0/1
form 0/1
0/1
x3
Inclusion of a Flip-Flop with a LUT
A Flip-Flop can be selected for inclusion or not
Latches the LUT output
Select

Out
Flip-flop
In 1
In 2 LUT D Q
In 3
can program to
Clock bypass the FF
COMPARISON OF CPLD AND FPGA