I2C Communication Protocol
Contents
Introduction
Working
Circuit Diagram
Start and Stop conditions
Repeated start condition
Addressing
I2C packet format
Read/Write bit
ACK/NACK bit
Features
Pros and Cons
Introduction
I2C stands for Inter-Integrated Circuit.
It is a bus interface connection protocol incorporated into devices for serial
communication.
It was originally designed by Philips Semiconductor in 1982.
Recently, it is a widely used protocol for short-distance communication.
It is also known as Two Wired Interface(TWI).
Working
It uses only 2 bi-directional open-drain lines for data communication called SDA and SCL.
Both these lines are pulled high.
Serial Data (SDA) – Transfer of data takes place through this pin.
Serial Clock (SCL) – It carries the clock signal.
I2C operates in 2 modes –
• Master mode
• Slave mode
Each data bit transferred on SDA line is synchronized by a high to the low pulse of each
clock on the SCL line.
Working
According to I2C protocols, the data line can not change when the clock line is high, it can
change only when the clock line is low.
The data is transmitted in the form of packets which comprises 9 bits. The sequence of
these bits are –
1. Start Condition – 1 bit
2. Slave Address – 8 bit
3. Acknowledge – 1 bit
Circuit Diagram
Start and Stop Conditions
START and STOP can be generated by keeping the SCL line high and changing the level
of SDA. To generate START condition the SDA is changed from high to low while keeping
the SCL high. To generate STOP condition SDA goes from low to high while keeping the
SCL high, as shown in the figure below.
START condition plus address packet plus one more data packet plus STOP
condition collectively form a complete Data transfer.
I2C Packet Format
In the I2C communication protocol, the data is transmitted in the form of packets.
These packets are 9 bits long, out of which the first 8 bits are put in SDA line and the 9th
bit is reserved for ACK/NACK i.e. Acknowledge or Not Acknowledge by the receiver.
1. The master sends the start condition to every connected slave by switching the SDA line
from a high voltage level to a low voltage level before switching the SCL line from high to
low
2. The master sends each slave the 7 or 10 bit address of the slave it wants to communicate
with, along with the read/write bit.
3. Each slave compares the address sent from the master to its own address. If the address
matches, the slave returns an ACK bit by pulling the SDA line low for one bit. If the
address from the master does not match the slave’s own address, the slave leaves the SDA
line high.
4. The master sends or receives the data frame.
5. After each data frame has been transferred, the receiving device returns another ACK bit
to the sender to acknowledge successful receipt of the frame.
6. To stop the data transmission, the master sends a stop condition to the slave by
switching SCL high before switching SDA high.
Repeated Start Condition
Between each start and stop condition pair, the bus is considered as busy and no master can
take control of the bus.
If the master tries to initiate a new transfer and does not want to release the bus before
starting the new transfer, it issues a new START condition.
It is called a REPEATED START condition.
Addressing
The address frame is the first frame after the start bit.
The address of the slave with which the master wants to communicate is sent by the
master to every slave connected with it.
The slave then compares its own address with this address and sends ACK.
Read/Write Bit
A high Read/Write bit indicates that the master is sending the data to the slave, whereas a
low Read/Write bit indicates that the master is receiving data from the slave.
ACK/NACK Bit
After every data frame, follows an ACK/NACK bit. If the data frame is received
successfully then ACK bit is sent to the sender by the receiver.
Features
• Half-Duplex Communication Protocol –
Bi-directional communication is possible but not simultaneously.
• Synchronous Communication –
The data is transferred in the form of frames or blocks. Can be configured in a multi-
master configuration.
• Clock Stretching –
The clock is stretched when the slave device is not ready to accept more data by holding
the SCL line low, hence disabling the master to raise the clock line. Master will not be able
to raise the clock line because the wires are AND wired and wait until the slave releases
the SCL line to show it is ready to transfer next bit.
Features
• Arbitration –
I2C protocol supports multi-master bus system but more than one bus can not be used
simultaneously. The SDA and SCL are monitored by the masters. If the SDA is found high
when it was supposed to be low it will be inferred that another master is active and hence it
stops the transfer of data.
• Serial transmission –
I2C uses serial transmission for transmission of data.
• Used for low-speed communication.
Pros and Cons
Advantages :
• Can be configured in multi-master mode.
• Complexity is reduced because it uses only 2 bi-directional lines (unlike SPI
Communication).
• Cost-efficient.
• It uses ACK/NACK feature due to which it has improved error handling capabilities.
Limitations :
• Slower speed.
• Half-duplex communication is used in the I2C communication protocol.
