• We know that synchronous sequential circuits change (affect) their states for
every positive (or negative) transition of the clock signal based on the input. So,
this behavior of synchronous sequential circuits can be represented in the
graphical form and it is known as state diagram. A synchronous sequential
circuit is also called as Finite state machine (FSM) if it has a finite number of
states. There are two types of FSMs.
• Mealy State Machine
• Moore State Machine
State machine: A state machine is a digital device that traverses through a
predetermined sequence of states in an orderly fashion. It consists of a finite number of
states and is therefore also called finite-state machine (FSM). A state is a set of values
measured at different parts of the circuit.
Different types of Finite State Machines –
are two types of Finite State Machines , they are :-
1) Mealy machine
2) Moore machine
Mealy machine:A Finite State Machine is said to be Mealy state machine, if outputs
depend on both present inputs & present states.
Moore machine: A Finite State Machine is said to be Moore state machine, if outputs
depend only on present states.
Mealy state machine
A Finite State Machine is said to be Mealy state machine, if outputs depend on both present
inputs & present states. The block diagram of Mealy state machine is shown in the following
figure.
As shown in the figure, there are two parts present in Mealy state machine. Those are
combinational logic and memory. Memory is useful to provide some or part of previous
outputs (present states) as inputs of combinational logic.
So, based on the present inputs and present states, the Mealy state machine produces
outputs. Therefore, the outputs will be valid only at the positive (or negative) transition
of the clock signal.
Let us consider a 110 Mealy sequence detector with synchronous reset input which is used to
reset the machine.
• From the above Mealy machine
State s0: When input is 1, we have detected the first bit in the sequence, hence we have to
go to the next state to detect the next bit in the sequence. When input is 0, then
remain in the state 's0' because bit 0 is not the first bit in the sequence. In both
cases output is 0, since we have not yet detected all the bits in the sequence.
State s1: When input is 1, we have detected the second bit in the sequence, hence we
have to go to the next state to detect the next bit in the sequence.When input is 0,
we have to go to the state 's0' to detect the first bit in the sequence that's 1.
State s2: When input is 0, we have detected the last bit in the sequence, hence we have to
go to the initial statestate, to detect the next sequence and make output high
indicating sequence is detected. When input is 1, we have to go to the state 's1',
because 1 we have detected may start the sequence.
Moore Machine
• Fig (a) shows the block diagram of Moore model. All the outputs of Moore
machine are synchronized with the circuit clock. We consider a 110
Moore sequence detector. The Moore machine starts its search for the
sequence 110 on its input and once the sequence is received, the output
goes high 1 and retains that state for a complete clock period.
• State A: When input is 1, we have detected the first bit in the sequence,
hence we go to the next state to detect the next bit in the sequence.
When input is 0, we have to remain in the state 'a' because bit 0 is not the
first bit in the sequence. In both cases output is 0, since we have not yet
detected all the bits in the sequence.
• State B: When input is 1, we have detected the second bit in the
sequence, hence we have to go to the next state to detect the next bit in
the sequence. When input is 0, we have to go back to the state'a' output
is still 0.
• State C: Now when 0 input occurs the 110 sequence is completed and
output must equal to 1. Here we can't go back to state 'b' and hence we
have to create new state d with a output 0.
• State D: Since the sequence is detected this is the last state. When input is
1, we have detected the first bit in the next sequence, hence we have to
go to state 'b'. When input is 0, we have to go to state 'a'.
Steps to design FSMs using verilog HDL
The Basic steps to design FSMs using verilog HDL
1. Define state register logic for the current state and next state variables
ex: reg [1:0] state, nextstate;
2. Declare symbols for states with state assignment logic
ex: parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
3. Define next state function logic , i.e state by state case analysis
Ex: always @ (*)
case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: nextstate = S0;
4. Define output function logic, i.e state by state analysis to get the output
function, if it is
Moore machine : output determined by current state only
Mealy machine: output determined by current state and inputs
It describes the output of each state.
