MICROPROCESSOR &

MICROCONTROLLER
 CHAPTER 1
INTRODUCTION
Introduction
Microprocessor Definition
Microcontroller Definition
Operation of ALU
 Evolution of Microprocessors
Block Diagram of microprocessor
based system
Development cycle ,RISC and CISC
processors
2 ESI,AMG,BVCOE 08/13/2024
 In this Lecture ……
Overview
General physical & operational features
Block diagram
Pin assignments
Logic symbol
Hardware description
Pin description
Read-modify-write port instructions

3 ESI,AMG,BVCOE 08/13/2024
The 8051 microcontroller
a Harvard architecture (separate
instruction/data memories)
single chip microcontroller (µC)
developed by Intel in 1980 for use in
embedded systems.
today largely superseded by a vast
range of faster and/or functionally
enhanced 8051-compatible devices
manufactured by more than 20
independent manufacturers
Harvard and von Neumann
Architectures
Harvard Architecture—a type of computer
architecture where the instructions
(program code) and data are stored in
separate memory spaces
Example: Intel 8051 architecture

Von Neumann Architecture—another type

of computer architecture where the
instructions(program code) and data are
stored in the same memory space
Example: Intel 8085, Intel 8086 architecture
 Microprocessor (MPU)
MPU (CPU)
Read instructions
Process binary data

6 330_01
 Microprocessor-Based System

7
 MCU-Based Systems
 Includes microprocessor, memory, I/O
ports, and support devices (such as timers)
on a single semiconductor chip

 Buses are generally not available to a

system designer

 I/O ports are generally multiplexed and can

be programmed to perform different
functions

8 330_01
 Block Diagram

9 330_01
 MCU-Based system

10 330_01
 Computer Architectures
 Von neumann versus Harvard Architecture

 CISC versus RISC processors

 Microprocessors and Microcontrollers

11 330_01
Microprocessor vs. Microcontroller

Microprocessor Microcontroller
 CPU is stand-alone, RAM,  CPU, RAM, ROM, I/O and
ROM, I/O, timer are separate timer are all on a single chip
 designer can decide on the  fix amount of on-chip ROM,
amount of ROM, RAM and RAM, I/O ports
I/O ports.  Highly bit addressable
 expansive  for applications in which cost,
 versatility power and space are critical
 general-purpose  single-purpose
Three criteria in Choosing a Microcontroller
 meeting the computing needs of the task efficiently and cost
effectively
 speed, the amount of ROM and RAM, the number of I/O
ports and timers, size, packaging, power consumption
 easy to upgrade
 cost per unit
 availability of software development tools
 assemblers, debuggers, C compilers, emulator, simulator,
technical support
 wide availability and reliable sources of the microcontrollers.
 Comparison of the 8051 Family
 Members
ROM type
 8031 no ROM
 80xx mask ROM
 87xx EPROM
 89xx Flash EEPROM
 89xx
 8951
 8952
 8953
 8955
 898252
 891051
 892051
 Example (AT89C51,AT89LV51)
 AT= ATMEL(Manufacture)
 C = CMOS technology
 LV= Low Power(3.0v)
Comparison some of the 8051 Family
Members
ROM RAM Timer
8051 4K 128 2

8031 - 128 2

8751 4K EPROM 128 2

8052 8K 256 3

8032 - 256 3

8752 8K EPROM 256 3

 General Physical Features of 8051
4KB ROM
128 bytes internal RAM
4 register banks of 8 bytes each (R0-R7)
16 bytes of bit-addressable area
80 bytes of general purpose memory
Four 8-bit I/O ports (P0-P3)
Two 16-bit timers (Timer0 & Timer1)
One serial receiver-transmitter interface
Five interrupt sources (2 external & 3 internal)
One oscillator (generates clock signal)

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 General Operational
Features
Memory of 8051 can be increased
externally:
Increase memory space for codes (programs)
by 64K
Increase memory space for data by 64K
Boolean instructions work with 1 bit at a
time

17 ESI,AMG,BVCOE 08/13/2024
 The 8051 Block Diagram
External Interrupts

4K byte Timer 1
128 byte Timer
Interrupt Control ROM RAM Timer 0 Inputs

CPU

Bus Serial
OSC I/O Ports
Control Port

XTAL2 TXD RXD

XTAL1 ALE RST
EA PSEN P0 P2 P1 P3
(Address/Data)

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The 8051 Pin Assignments
P1.0 1 40 VCC
P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)
P1.4 5 36 P0.3 (AD3)
P1.5 6 8051 35 P0.4 (AD4)
P1.6 7 34 P0.5 (AD5)
P1.7 8 33 P0.6 (AD6)
RST 9 32 P0.7 (AD7)
(RXD) P3.0 10 31 EA/VPP
(TXD) P3.1 11 30 ALE/PROG
(INT0) P3.2 12 29 PSEN
(INT1) P3.3 13 28 P2.7 (A15)
(T0) P3.4 14 27 P2.6 (A14)
(T1) P3.5 15 26 P2.5 (A13)
(WR) P3.6 16 25 P2.4 (A12)
(RD) P3.7 17 24 P2.3 (A11)
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)
 The 8051 Logic Symbol

VSS VCC RST

P0.7
XTAL1 P0.6 P
P0.5 O ADDRESS
P0.4 R AND
XTAL2 P0.3 DATA BUS
P0.2 T
P0.1 0
P0.0
EA
PSEN P1.7
P1.6 P
ALE P1.5 O
P1.4 R
P1.3 T
P1.2 1
P1.1
P1.0

RxD P3.7 P2.7

TxD P P3.6 P2.6 P ADDRESS
SECONDARY INT0 O P3.5 P2.5 O BUS
INT1 P3.4 P2.4 R
FUNCTIONS R P3.3 P2.3
T0 T
T1 T P3.2 P2.2
WR 3 P3.1 P2.1 2
RD P3.0 P2.0
 Hardware Description
1. Oscillator circuit
2. Program counter (PC)
3. Data pointer (DPTR)
4. Accumulator (“A”) register
5. B register
6. Flags
7. Program status word (PSW)
8. Internal memory (ROM, RAM, additional
memory)
9. Stack & stack pointer (SP)
10. Special function register (SFR)
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Oscillator Circuit
A single machine cycle
The heart of the 8051 consists of 12 crystal pulses !
Produces clock pulses
Synchronize all 8051’s internal operations
Machine Cycle
 Machine cycle is the basic repetitive process that the CPU
performs once it is powered on. A machine cycle consists of a
fixed number of clock cycles (pulses). It is different for different
kinds of CPU.
 The 8051 family needs 12 clock cycles for a machine cycle.
 The CPU takes one or more machine cycles to complete an
instruction. More complex instructions require more number of
machine cycles to complete the instruction. The number of
machine cycles of the 8051 instructions are ranging from 1 to 4.
Example 4-1
Find the elapse time of the machine cycle for:
(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz
(c) XTAL = 20 MHz

Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz
T = 1 / 921.6 kHz = 1.085 s
(b) 16 MHz / 12 = 1.333 MHz
T = 1 / 1.333 MHz = 0.75 s
(c) 20 MHz / 12 = 1.667 MHz
T = 1 / 1.667 MHz = 0.60 s
 Program Counter (PC)
PC is a 16-bit register
PC is the only register that does not have an
internal address
Holds the address of the memory location to
fetch the program instruction
Program ROM may be on the chip at addresses
0000H to 0FFFH (4Kbytes), external to the chip
for addresses that exceed 0FFFH
Program ROM may be totally external for all
addresses from 0000H to FFFFH
PC is automatically incremented (+1) after
every instruction byte is fetched

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 Data Pointer (DPTR)
DPTR is a 16-bit register
DPTR is made up of two 8-bit registers: DPH
and DPL
DPTR holds the memory addresses for internal
and external code access and external data
access
(eg. MOVC A,@A+DPTR MOVX A,@DPTR MOVX
@DPTR,A )
DPTR is under the control of program
instructions and can be specified by its 16-bit
name, or by each individual byte name, DPH
and DPL
26 DPTR does not have a single internal address;
ESI,AMG,BVCOE 08/13/2024
 Accumulator (A Register)

Most versatile CPU register and is used for

many operations, including addition,
integer multiplication and division, and
Boolean bit manipulations
A register is also used for all data transfer
between the 8051 and any external
memory

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 B Register

B register is used with the A register for

multiplication and division operations
(eg. MUL AB DIV AB)
No other special function other than as a
location where data may be stored

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Flags
Flags are 1-bit registers provided to store the
results of certain program instructions
Other instructions can test the condition of the
flags and make decisions based on the flag states
Flags are grouped inside the program status
word (PSW) and the power control (PCON)
registers for convenient addressing
Math flags: respond automatically to the
outcomes of math operations (CY, AC, OV, P)
User flags: general-purpose flags that may be
used by the programmer to record some event in
the program (F0, RS0, RS1)
Program Status Word (PSW)

PSW contains the math flags, user program flag

F0, and the register select bits (RS1, RS0) that
identify which of the four general-purpose
register banks is currently in use by the program

7 6 5 4 3 2 1 0
CY AC F0 RS RS OV -- P
1 0
Program Status Word (PSW)
Bit Symbol Function
7 CY Carry Flag; used in arithmetic, JUMP,
ROTATE, and BOOLEAN instruction
6 AC Auxiliary carry flag; used for BCD
arithmetic
5 F0 User flag 0
4 RS1 Register bank select bit 1
3 RS0 Register bank select bit 0
2 OV Overflow flag; used in arithmetic
instructions
1 -- Reserved for future use
0 P Parity flag; shows parity of register A: 1
= Odd Parity
 Internal Memory
A functioning computer must have memory for
program code bytes, commonly in ROM, and
RAM memory for variable data that can be
altered as the program runs
8051 has internal RAM (128 bytes) and ROM
(4Kbytes)
8051 uses the same address but in different
memories for code and data
Internal circuitry access the correct memory
based on the nature of the operation in
progress
32
Can add memory externally if needed
ESI,AMG,BVCOE 08/13/2024
8051 Internal RAM Organisation
1F R7
1E R6 7F
1D R5
1C R4
Bank

1B R3
3

1A R2
19 R1
18 R0
17 R7
16 R6
15 R5
Bank 2

14 R4
13 R3
12 R2
11 R1
10 R0
0F R7 2F 7F 78
0E R6 2E 77 70
Bank 1

0D R5 2D 6F 68
0C R4 2C 67 60
0B R3 2B 5F 58
0A R2 2A 57 50
09 R1 29 4F 48
08 R0 28 47 40
07 R7 27 3F 38
06 R6 26 37 30
05 R5 25 2F 28
Bank 0

04 R4 24 27 20
03 R3 23 1F 18
02 R2 22 17 10
01 R1 21 0F 08
00 R0 20 07 00 30

Working Registers Bit Addressable General Purpose

 Example
State the contents of RAM locations after the
following program:
MOV R0, #99H
MOV R1, #85H
MOV R2, #3FH
MOV R7, #63H
MOV R5, #12H
After the execution of the above program we have
the following:
RAM location 0 has value 99H RAM location 1 has
value 85H
RAM location 2 has value 3FH RAM location 7 has
34
value 63H
ESI,AMG,BVCOE 08/13/2024
RAM location 5 has value 12H
Program Status Word (PSW)
Bank Select Bits, RS1, & RS0 to select 1 of 4 register bank

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 Example
Repeat Example using RAM addresses instead of register names.

This is called direct addressing mode and uses

the RAM address location for the destination
address.
MOV 00, #99H
MOV 01, #85H
MOV 02, #3FH
MOV 07, #63H
MOV 05, #12H

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 Example 2-7
State the contents of RAM locations after the
following program:
SETB PSW.4
MOV R0, #99H
MOV R1, #85H
MOV R2, #3FH 7 6 5 4 3 2 1 0
MOV R7, #63H PSW CY AC F0 RS RS OV -- P
MOV R5, #12H 1 0

By default, PSW.3=0 and PSW.4=0; therefore, the

instruction “SETB PSW.4” sets RS1=1 and RS0=0, thereby
selecting register bank 2. Register bank 2 uses RAM
locations 10H – 17H. After the execution of the above
program we have the following
RAM location 10 has value 99H RAM location 11 has
value 85H
37 RAM location 12 has value 3FH
ESI,AMG,BVCOE RAM location 1708/13/2024
has
value 63H
 Stack and Stack Pointer (SP)
SP is a 8-bit register used to hold an internal RAM
address that is called the “top of the stack”
Stack refers to an area of internal RAM that is
used in conjunction with certain opcodes to store
and retrieve data quickly
SP holds the internal RAM address where the last
byte of data was stored by a stack operation
When data is to be placed on the stack, the SP
increments before storing data on the stack so
that the stack grows up as data is stored
As data is retrieved from the stack, the byte is
read from the stack, and then the SP decrements
to point to the next available byte of stored data
SP = 07H after reset
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 Stack Operation
Store Data Get Data
SP = 0A Address SP = 0A
0A

Store Data Get Data

SP = 09 Address SP = 09
09

Store Data Get Data

SP = 08 Address SP = 08
08

SP = 07 Address SP = 07
07
Storing Data on the Stack Internal RAM Getting Data From the Stack
(Increment then store) (Get then decrement)

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 Example
Show the stack and stack pointer for the following.
Assume the default stack area.
MOV R6, #25H
MOV R1, #12H
MOV R4, #0F3H
PUSH 6
PUSH 1
PUSH 4

After PUSH 6 After PUSH 1 After PUSH 4

0B 0B 0B 0B
0A 0A 0A 0A F3
09 09 09 12 09 12
08 08 25 08 25 08 25
SP = 07 SP = 08 SP = 09 SP = 0A

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Example
Examine the stack, show the contents of the
registers and SP after execution of the following
instruction. All values are in hex.
POP 3 ;POP stack into R3
POP 5 ;POP stack into R5
POP 2 ;POP stack into R2
After POP 3 After POP 5 After POP 2
0B 54 0B 54 0B 54 0B 54
0A F9 0A F9 0A F9 0A F9
09 76 09 76 09 76 09 76
08 6C 08 6C 08 6C 08 6C
Start SP = 0B SP = 0A SP = 09 SP = 08
05 ?? 05 ?? 05 F9 05 F9
04 ?? 04 ?? 04 ?? 04 ??
03 ?? 03 54 03 54 03 54
02 ?? 02 ?? 02 ?? 02 76
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 Example
Show the stack and stack pointer for the following.
MOV SP, #5FH
MOV R2, #25H
MOV R1, #12H
MOV R4, #0F3H
PUSH 2
PUSH 1
PUSH 4

After PUSH 2 After PUSH 1 After PUSH 4

63 63 63 63
62 62 62 62 F3
61 61 61 12 61 12
60 60 25 60 25 60 25
Start SP = 5F SP = 60 SP = 61 SP = 62
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 Special Function Registers (SFR)

8051 has 21 SFRs which occupy the

addresses from 80H to FFH (128bytes)
Not all of the addresses from 80H to FFH
are used for SFRs
Attempt to use the “empty” addresses
may get unpredictable result

43 ESI,AMG,BVCOE 08/13/2024
 Special Function Registers

DATA registers

CONTROL registers

•Timers

•Serial ports

•Interrupt system

•Analog to Digital converter Addresses 80h – FFh

•Digital to Analog converter
etc.. Direct Addressing is used to
access SFRs
 Special Function Register Map
Bit addressable

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Bit Addressable RAM
 Value of SFR at Reset

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 Internal ROM
Internal ROM occupies the code address
space from 0000H to 0FFFH (Size = 4K
byte)
Program addresses higher than 0FFFH will
automatically fetch code bytes from
external program memory
Code bytes can also be fetched exclusively
from an external memory by connecting
the external access pin (EA) to ground

48 ESI,AMG,BVCOE 08/13/2024
 Memory mapping in 8051

ROM memory map in

8051 family
4k 8k 32k
0000H 0000H 0000H

0FFFH

DS5000-32
1FFFH
8051
8752 7FFFH

from Atmel from Dallas

Corporation Semiconductor
 Size of Address Bus and Memory:
The size of the address bus determines how
much memory the CPU can address directly. For
example, a 20-bit address bus can access up to
one megabyte (1MB); 24 bits reaches 16MB,
and 32 bits can handle four gigabytes (GB).
Address Bus stores the location of a byte of
memory. If an address bus is of size 32 bits, that
means it can hold upto 232 numbers and it hence
can refer upto 232 bytes of memory = 4GB of
memory and any memory greater than that is
useless. Data bus is used to send the value to be
written to/read off the memory.
50 ESI,AMG,BVCOE 08/13/2024
Memory Space
52 ESI,AMG,BVCOE 08/13/2024
 SECTION 14.2: MEMORY ADDRESS
DECODING
Simple logic gate address decoder

Figure 14–4 Logic Gate as Decoder

53
 Memory Map

54 ESI,AMG,BVCOE 08/13/2024
Address Multiplexing for External Memory
Accessing External Code Memory
 Accessing External Code
Memory
C000 ADD A,B ; 80H
10000000
Program For Addition of Two Numbers
MOV A,#11H ; Move 11h into A register
ADD A,#22H ; Add A register with 22h.result in A
register
HLT ; End of the Program
PC INSTRUCTI HEX Binary
ON CODE Code

C000 MOV A,#11H 36H 0011011

0
C001 11H 0001000
1
C002 ADD A,#22H 81H 1000000
1
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C003 22H 0010001
Memory
 Accessing External Data
Memory

C000 MOV DPTR,#8000H

C001 MOVX A, @DPTR
10000110

MEM. LOC. HEX

BINARY
PC C001H 86H
10000110
DPTR 8000H FFH
Three Operations When Instruction
11111111
Executed:
Opcode Fetch
Instruction Decoder
Instruction Execution
60 ESI,AMG,BVCOE 08/13/2024
 Instructions used for Memory
Accessing

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 Some Important Pins

VCC (pin 40 - provides supply voltage of

+5V)
GND (pin 20)
XTAL1 & XTAL2 (pins 19 & 18 - to crystal and
then caps)
RST (pin 9- reset)
EA (pin 31 - external access)
PSEN (pin 29 - program store enable)
ALE (pin 30 - address latch enable)
Ports 0-3
63 ESI,AMG,BVCOE 08/13/2024
 I/O Ports (P0 - P3)
One of the most useful features of the 8051
is that it consists of 4 I/O ports (P0 - P3)
All ports are bidirectional (they can take input
and to provide output)
All ports have multiple functions (except P1)
All ports are bit addressable
On RESET all the ports are configured as input
When a bit latch is to be used as an input, a
“1” must be written to the corresponding
latch by the program to configure it as input
(eg. MOV P1, #0FFH)
64 ESI,AMG,BVCOE 08/13/2024
 Port 0
Occupies a total of 8 pins (Pins 32-39)
Can be used for :
Input only
Output only
Input and output at the same time (i.e.
some pins for input and the others for
output)
Can be used to handle both address and
data
Need pull-up resistors
65 ESI,AMG,BVCOE 08/13/2024
I/O Port Circuitry
67 ESI,AMG,BVCOE 08/13/2024
 Port 0

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 Port 0 as an Output Port
The following code will continuously send out to
port 0 the alternating values 55H and AAH

MOV A, #55H
BACK: MOV P0, A
ACALL DELAY
CPL A
SJMP BACK

69 ESI,AMG,BVCOE 08/13/2024
 Port 0 as an Input Port

In the following code, port 0 is configured

first as an input port by writing 1s to it, and
then data is received from that port and
sent to P1
MOV A, #0FFH
MOV P0, A
BACK: MOV A, P0
MOV P1, A
SJMP BACK

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Dual Role of Port 0
When connecting an 8051 to an external memory, port 0
provides both address and data (AD0 – AD7)
When ALE = 0, it provides data D0 – D7
When ALE = 1, it provides Address A0 – A7.
ALE is used for demultiplexing address and data with the help
of
a 74LS373 latch

71 ESI,AMG,BVCOE 08/13/2024
Port 1
Occupies a total of 8 pins (Pins 1-8)
Can be used as input or output
Does not need any pull-up resistors
Upon reset, port 1 is configured as an
input port
No alternative functions

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 Port 1

73 ESI,AMG,BVCOE 08/13/2024
 Port 1 as an Output Port
The following code will continuously send out to
port 1 the alternating values 55H and AAH

MOV A, #55H
BACK: MOV P1, A
ACALL DELAY
CPL A
SJMP BACK

74 ESI,AMG,BVCOE 08/13/2024
 Port 1 as an Input Port
In the following code, port 1 is configured first as an
input port by writing 1s to it, and then data is
received from that port and saved in R7, R6, and R5

MOV
P1,#0FFH
MOV A, P1
MOV R7, A
ACALL DELAY
MOV A, P1
MOV R6, A
ACALL DELAY
MOV A, P1
MOV R5, A
75 ESI,AMG,BVCOE 08/13/2024
 Port 2

Occupies a total of 8 pins (Pins 21-28)

Similar function as Port 1
Can be used as input or output
Does not need any pull-up resistors
Upon reset, port 2 is configured as an
input port

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77 ESI,AMG,BVCOE 08/13/2024
 Port 2 as an Output Port
The following code will continuously send out to
port 2 the alternating values 55H and AAH

MOV A, #55H
BACK: MOV P2, A
ACALL DELAY
CPL A
SJMP BACK

78 ESI,AMG,BVCOE 08/13/2024
 Port 2 as an Input Port
In the following code, port 2 is configured first as
an input port by writing 1s to it, and then data is
received from that port and sent to P1

MOV P2,#0FFH
BACK: MOV A, P2
MOV P1, A
SJMP BACK

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 Dual Role of Port 2
When connecting an 8051 to an external memory, port 2
provides both address (A8 – A15)
It is used along with P0 to provide the 16-bit address
When P2 is used for the upper 8 bits of the 16-bit address, it
cannot be used for I/O

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 Port 3
Occupies a total of 8 pins (Pins 10-17)
Similar function as Port 1 and Port 2
Can be used as input or output
Does not need any pull-up resistors
Upon reset, port 3 is configured as an input port
Pins can be individually programmable for other
uses
Most commonly be used to provide some
important signals (e.g. interrupts)

81 ESI,AMG,BVCOE 08/13/2024
 Port 3

82 ESI,AMG,BVCOE 08/13/2024
Port 3 Alternate Functions
P3 Bit Function Pin
P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17
Read-Modify-Write Feature
A method used to access the 8051 ports
Combining all 3 actions in a single
instructions :
Read the data at the port
Modify (do operation on) the data at the
port
Write the results to P1,
MOV the port
#55H
AGAIN: XRL P1, #0FFH
ACALL DELAY
SJMP AGAIN

84 ESI,AMG,BVCOE 08/13/2024
Read-Modify-Write Feature
Example:
ANL P1, A
ORL P2, A
XRL P3, A
JBC P1.1, LABEL
CPL P3.0
INC P2
DEC P2
DJNZ P3, LABEL

When reading a port some instructions

read the latch and others read the pin
The instructions that read the latch rather
than the pin are the ones that read a value
(possibly change it), an then rewrite it to
the latch are called “read-modify-write”
instructions
 Single-bit Addressability of Ports

One of the most powerful features of

the 8051
Access only one or several bits of the
port instead of the entire 8 bits

BACK: CPL P1.2

ACALL DELAY
SJMP BACK

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 Write the following Program
1) Create a square wave of 50% duty
cycle on bit 0 of port 1.
2) Create a square wave of 66% duty
cycle on bit 3 of port1.
3) Keep monitoring pin P0.1 until it
becomes high when P0.1 becomes
high,read the data from the port 1 and
send low-to-high pulse on P0.2 to
indicate data has been read.
4) A switch is connected to pin P1.0 and
87
LED to pin P2.7.Write a program 08/13/2024
ESI,AMG,BVCOE to get
 Summary

General physical & operational features

8051 hardware description
8051 pin description
Read-modify-write port instructions

88 ESI,AMG,BVCOE 08/13/2024
 Read reference
The 8051 Microcontroller and Embedded
Systems - Using Assembly and C By Mazidi
 Chapter 1
 Chapter 4
Microcontroller Theory and Applications By
Ajay Deshmukh
 Chapter 1
 Chapter 3