Physical Design Flow
Presented by
Naresh R
3NG21EC020
Introduction
• The Physical Design Flow in VLSI (Very Large
Scale Integration) is a crucial process in chip
design.
• It involves transforming a synthesized netlist
into a physical layout that can be fabricated on
silicon.
1. Design entry.
• Design entry in VLSI (Very Large Scale
Integration) refers to the initial phase of the
chip design process where the design
specifications are captured and entered into a
design tool.
• This phase is crucial as it sets the
foundation for the entire design flow.
• The input is a logical description with no
physical information.
2. Initial synthesis
• . The initial synthesis contains little or no
information on any interconnect loading.
• The output of the synthesis tool (typically an
EDIF netlist) is the input to the floorplanner.
3. Initial floorplan.
• From the initial floorplan interblock
capacitances are input to the synthesis tool as
load constraints and intrablock capacitances
are input as wire-load tables
4. Synthesis with load constraints
• At this point the synthesis tool is able to
resynthesize the logic based on estimates of
the interconnect capacitance each gate is
driving.
• The synthesis tool produces a forward
annotation file to constrain path delays in the
placement step.
5. Timing-driven placement
• After placement using constraints from the
synthesis tool, the location of every logic cell
on the chip is fixed and accurate estimates of
interconnect delay can be passed back to the
synthesis tool.
6. Synthesis with in-place optimization
(IPO)
• The synthesis tool changes the drive strength
of gates based on the accurate interconnect
delay estimates from the floorplanner without
altering the netlist structure.
7.Detailed placement
• The placement information is ready to be
input to the routing step.
