20EVE2
SN
First Semester M.Tech. Degree Examination, Jan./Feb. 2021
ASIC Design
Time: 3 hrs. Marks: 100
Note: Answer any FIVE full questions, choosing ONE full questlon module.
Module-1
1 & Wiha neat diagram,explain ASIC design flow. (1O Marks)
b. Explain the folowing with relevant diagram:
i) Standard cell based ASIC (CBIC)
ii) Programmable logic devices. (10 Marks)
OR
2 Explain carry sclect adderand how it is extended to form-bit conditional sum adder.
(I0 Marks)
b. With a relevant cell diagram and equaions ExpaintCarry Look Ahcad adder (CLA
(10Marks)
Module-4
Explain /O andpower planning in ASIC floor plan. (1O Marks)
Discuss the measurement of delay in floor planning. (iOMarks)
of2
I
OR
8 a. With neat diagram, explain mincut placement algorithm.
b. Explain thephysical design flow with respect to placement
Module-5
9 a. Explain the global routing methods.
b. Explain global routing between blocks.
OR
10 a. Explain the following
i) Measurerment of channel density
ii) Left cdge algorithm
b. Write a note on circuit extraction andDRC.
USN
First Semester M.Tech. Degree Examination, Feb./Mar. 2022
ASIC Design
Time: 3 hrs. Marks 00
Note:Answer any FIVE full questions, choosing ONE full question fron ach odule.
Module-1
1 a. With neat flow diagram, explain the steps in volved in ASIC desig (10Marks)
b. Withneat sketches,explain the following :
i) Programmable logicdevices
ii)Structurcd gatc arrays. (10 Marks)
OR
2 a. With relevant diagram
Mention its linitations.
and cquations, explain the Conventiogal Ripple Carry Adder.
(10Marks)
b. Write a short note on
i) VOcells
ii)Cell compilers. (10Marks)
Module-4
7 Explain the measurement of delay in floor planning. o Marks)
b. Explain the following:
i) Power distribution scheme
ii) Clock planning. (10 Marks)
OR
8 Explain physical design flow with respect to placement, (10 Marks)
b. Briefly explain the following :
a.
i) Goals and objectives ofplacement
ii) Timing driven placement method.
Explain the following :
Module5
urce(10Marks)
i)Left cdge algorithm
ii) Hightower arca routing algorithm. (10Marks)
b. Explain circuit extraction and DRC. (10 Marks)
OR
10 a. Explain the following special routing techniques :
i) Clock routing
ii) Power routing. (10Marks)
b. Explain global routing bewaenblocks (10 Marks)
First Semester M.Tech. Degree Examination, Dec.2019/Jan.202
ASIC Design
Time: 3 hrs. Marks00
Note: Answer any FIVE full gquestions, choosing ONE full question fror kah mod le.
Module-1
11 a. Explain the following in brief with relevant diagram.
) Standard cell based ASICs
in) Gate array based AfIC (channelcd. channelless and structurcd
gets aray). (10Marks)
the steps involved in ASIC design. (10Marks)
b. Explain in detail
OR
2 a. Explain the functioning and limitation of conventional Ripple Carry Adder [RCAJ. with
relevant logic equations and cell diagram (10 Marks)
b. Explain Wallace tree multiplier. (10 Marks)
Module-4
7 Explain the following
i)Power planning
:
i)Clock planning. (10 Marks)
b. Explain the concept of measurementof de in floorpanning. (10Marks)
8
ORtl
Write an algorithm for ierative placemerimprovement method and cxplain brielly.
(10Marks)
b. Explain the following :
i) Placement using simulated annealing
iü) Timing driven placenebt nethod (10Marks)
Module-5
9 a. Explain the goals arnd oticctives of detailed routing and explain therouting method in an
ASIC physical design. (10Marks)
b. Explain the goals and objicctives of global routing in detail. (10Marks)
OR
10 a. Explajn the foluwing
i) ei dge algorithm
ii) Anea-roUting algorithm. (t0Marks)
b. Explai the following special routing techniques.
hcroutingW
ii) Pawer routing. (10 Marks)
T1TUTE OE 20EVE23
Feb./Mar.2022
SecohdsSemester M.Tech. Degree Exapigation,
Systemn Verilog Max. Marks: 100
Tme:3hs, questionfrom each module.
NoteAnswer any FIVE full questions, choosiug ONE full
Modme- (10Marks)
systeyi yerilog.
1 a. Explainthe verification process in
(10Marks)
in randomizing the stimulus to a design.
b. Explain factors
OR
(08 Marks)
2 a. Describe various array methods ith examples. (06 Marks)
b. Write a note on user definedata typesin system verilog,
(06 Marks)
with exaíple.
c. Explainconstants and strings system verilog
Module-2
(05 Marks)
n systemverilog.
3 a. Write the difference between Tasks and functions
with system verilog program example.
b. Explain Automatisforage and variable initializÂtion (08 Marks)
(07 Marks)
C. Describe how to specify time values in systmi verilog.
OR DUT with suitable diagram and
4 a Descrihe the communication between the test bench and
(10 Marks)
systam yerilog program.
Example. (10 Marks)
b. Explain different types ofsystemverilog assertions witi
Module-3,m
(10Marks)
5 a What randomization-Explain randomization nsystem verilog.
is
with
Describe conditional coàstraints and bidirectional constraints in system
verilog
b.
(10 Marks)
example.
(08Marks)
a. Write any fourandom number fupetjonswith example.
(06 Marks)
b. Describe commnon randomization poblems in systemyerilog.
(06 Marks)
c. Write a ngte on Pseudo randomhumber generatorsniystem verilog.
Module
a. Whate system verilog erent styles fork-jenin system verilog.
(10Marks)
(10Marks)
a. issystm y mail box2Exr Exchange of object using mail with suitable
(10Marks)
example.
Explain semaphore operation. (10Marks)
b. What is sýsem verilog semapho.
Module-5
a. coverage? Explain çoverageiypes in system verilog. (09Marks)
What is
b. Explain functionalcovrage inside class with program. (07Marks)
c. Writea note on Data Sampling. CMRIT LIBRARY (04 Marks)
037 - 560
OR BANGALORE
0 a. What is crosscoyérage? Write code for labeling cross coverage Bins and give its summary
report. (10Marks)
(10 Marks)
b. Explaingeneric cover groups in system verilog.
Second Semester M.Tech. Degree Examination, June/July 2019
System Verilog
Time: 3 hrs. Max. Marks: 100
Note: Ansswer any FIVE full questions, choosing ONEfull question from each module.
Module-1
1 Explain the verification process of system verilog. (10 Marks)
b. Draw the diagram of layered test bench of system verilog and describe the function of cach
layer. (10Marks)
OR
2 a. Describe fixed size arrays and dynamic arrays with examplc. (08 Marks)
(06 Marks)
b. Describevažous array methods with examples.
c. Describe typedef and enumerated data types with example. (06 Marks)
Module-2
3 Describe C-style routine arguments, argument direction, advanced argument types, and
(10 Marks)
argument values with systemn verilog program example.
default
b. Draw the diagram or Testhench-arbiter without interlace and write the system verilog code
for.the arbiter model using ports, testbench using ports, top-level net list without interface.
(10 Marks)
OR
4 (06 Marks)
a. Explain tasks, functions and void functions in syslem verilog.
(06 Marks)
b. How time values are specified in system verilog, describe with example.
c. Describe testbench-design race condition. Write system verilog code for race condition
(08 Marks)
between testbench and design.
Module-3
Module-3
(10 Marks)
5 a. Explain the concept of randomization in systen verilog with anexample.
b. Desoribe the solution probabilities in system verilog with example. (10Marks)
OR
6 a. Explain valid constraints and In-Ine constraints with example. (10Marks)
(05 Marks)
b. Discuss the common randomization problem with system verilog program.
it
(05 Marks)
c. Describe the operation of rand case statement with program.
Module-5
(10 Marks)
9 a. What coverage?Describe different coveragetypeS.
is
coVerage and give the coverage
b. What is cross coverage? Write the codefor basic croSs
(10 Marks)
summary report for baSIC croSs coverage.
OR
(10 Marks)
10 a. Describe coverage strafegies,
various functional
(10Marks)
b. Describe various coverage options with example.
