Module-2

Sequential Circuits
 Analysis of Clocked Sequential Circuits
• The behavior of a sequential circuit is determined from the inputs, the
outputs, and the states of its flip-flops.
• The analysis of sequential circuits obtained using:
• State Table
• State Diagram
• State Equations
• State Table- The time sequence of inputs, outputs, and flip-flop states may
be enumerated in a state table. It consists of three sections labeled
present state, next state, and output. The present state designates the
states of flip-flops before the occurrence of a clock pulse. The next state
shows the states of flip-flops after the application of a clock pulse, and the
output section lists the values of the output variables during the present
state. Both the next state and output sections have two columns, one for x
= 0 and the other for x = 1.
 Analysis of Clocked Sequential Circuits
• State Diagram- The information available in a state table may be
represented graphically in a state diagram. In this diagram, a state is
represented by a circle, and the transition between states is indicated by
directed lines connecting the circles.

• State Equations-A state equation (also known as an application equation)

is an algebraic expression that specifies the conditions for a flip-flop state
transition. The left side of the equation denotes the next state of a flip-
flop and the right side, a Boolean function that specifies the present state
conditions that make the next state equal to 1.
 Analysis of Clocked Sequential Circuits
An Example of a Sequential Circuit

B FF

A ff
 Analysis of Clocked Sequential Circuits
An Example of a Sequential Circuit
1. State Table

2. State Diagram
 Analysis of Clocked Sequential Circuits
An Example of a Sequential Circuit
3. State Equations

2. A(t+1)= Bx’+AB+Ax’ B(t+1) = A’x+A’B+Bx

=Bx’ + (B+x’)A = A’x+(A’+x)B
=Bx’ + (B’x)’A = A’x+(Ax’)’B
A(t+1)= S+R’A B(t+1) = S+ R’B

Reference: As S= Bx’, R= B’x Reference: As S= A’x, R= Ax’

1. A(t+1)= A’Bx’+AB’x’+ABx’+ABx
B(t+1) = A’Bx’+A’B’x+A’Bx+ABx
 Analysis of Clocked Sequential Circuits
• Flip-flop Input Functions :

This set of Boolean functions

fully specifies the logic
diagram:
• Variables SA and RA specify
RS flip-flop labeled A;
•variables SB and RB specify a
second RS flip-flop labeled B.
•Variable y denotes the output.
•The Boolean expressions for
the variables specify the
combinational circuit
part of the sequential circuit.
 State Reduction and Assignment
This section discusses certain properties of sequential circuits that may be
used to reduce the number of gates and flipflops during the design.
State assignment- assigning binary equivalents e.g.
If 3 states – a=00, b= 01, c=10 , if 4 states d=11, if five states e=100
(3 bits etc..)
• State Reduction:
• Check out of 7 states ,
any states is redundant- to
be eliminated,
Should be minimal states
• If next state and o/p is
same – reduce that state
State Reduction and Assignment

1. For state
e & g= next state and o/p same ,
e=g, g can be eliminated
State Reduction and Assignment
2 .For state
d & f = next state and o/p same ,
d =f , f can be eliminated

=e
State Reduction and Assignment
3 . Further cannot be eliminated, instead of 7
now 5 states

=d
=d
=d
State Reduction and Assignment
 Flip-flop Excitation Tables
1.RS ff
TT

2. D ff
 Flip-flop Excitation Tables
1.JK ff
TT

2. T ff
 State Assignment
• Design clocked sequential circuits who's state diagram is given in figure using JK
flipflop. (Note: not given o/p)

Ans: 1. Obtain state table

 State Assignment
Ans 2. obtain excitation table for sequential ckt. using exitation table of JK ff :
 State Assignment
Ans 3. Find simplified equation using K-map

KB= A’X’+AX
 State Assignment
Ans 4. Logic diagram of sequential ckt.
 Registers
• A register is a group of binary storage cells suitable for holding binary
information.
• A group of flip-flops constitutes a register, since each flip-flop is a binary cell
capable of storing one bit of information.
• An n-bit register has a group of n flip-flops and is capable of storing any binary
information containing n bits.

• The clock pulse input, CP, enables all flip-flops so that the information presently
available at the four inputs can be transferred into the 4-bit register.
• The four outputs can be sampled to obtain the information presently stored in the
register.
 Registers
• information present at a data (D) input is transferred to the Q output when the
enable (CP) is 1, and the Q output follows the input data as long as the CP signal
remains 1.
• When CP goes to 0, the information that was present at the data input just before
the transition is retained at the Q output.

• Note: A group of flip-flops sensitive to pulse duration (level triggering) is usually

called a latch
• A group of flip-flops sensitive to pulse transition (edge triggering)is called a
register.
 Registers
Register with Parallel Load

• The transfer of new information into a register is referred to as loading the

register.
• If all the bits of the register are loaded simultaneously with a single clock pulse,
we say that the loading is done in parallel.
Working: A 4-bit register with a load control input using RS flip-flops is shown in Fig.
7-2.
CP (triggering- positive edge of the pulse)
• CP input acts as an enable signal which controls the loading of new information
into the register.
• The CP input of the register receives continuous synchronized pulses which are
applied to ail flip-flops.
• The inverter in the CP path causes all flip-flops to be triggered by the negative
edge of the incoming pulses.
• The purpose of the inverter is to reduce the loading of the master-clock generator.
• This is because the CP input is connected to only one gate (the inverter) instead of
the four-gate inputs that would have been required if the connections were made
directly into the flip-flop clock inputs (marked with small triangles).
 Registers
Register with Parallel Load

Clear input:
• The clear input goes to a special terminal in each, flip-flop through a noninverting
buffer gate.
• When this terminal goes to 0, the flip-flop is cleared asynchronously. The clear
input is useful for clearing the register to all 0’s prior to its clocked operation. The
clear input must be maintained at 1 during normal clocked operations.
Load input:
• The load input goes through a buffer gate (to reduce loading) and through a series
of AND gates to the R and S inputs of each flip-flop. Although clock pulses are
continuously present, it is the load input that controls the operation of the
register.
• Operation
• The two AND gates and the inverter associated with each input I determine the
values of R and S.
• If the load input is 0, both R and S are 0, and no change of state occurs with any
clock pulse. Thus, the load input is a control variable which can prevent any
information change in the register as long as its input is 0.
• When the load control goes to 1, inputs I1, through I4 specify what binary
information is loaded into the register on the next clock pulse.
 Registers
Register with Parallel Load

• For each I that is equal to 1, the corresponding flip-flop inputs are S = 1,

R = 0.
• For each I that is equal to 0, the corresponding flip-flop inputs are S = 0, R
= 1,
• Thus, the input value is transferred into the register provided the load
input is 1, the clear input is 1, and a clock pulse goes from 1 to 0. This type
of transfer is called a parallel-load transfer because all bits of the register
are loaded simultaneously.

• Note: If the buffer gate associated with the load input is changed to an
inverter gate, then the register is loaded when the load input is 0 and
inhibited when the load input is 1.
• Buffer- temporary storing of data
 Registers
Register with Parallel Load
 Registers
Register with Parallel Load

A register with parallel load can be constructed with D flip-flops

 Registers
Register with Parallel Load

A register with parallel load can be constructed with D flip-flops

• The clock and clear inputs are the same as before.
• When the load input is 1, the I inputs are transferred into the register on the next
clock pulse. When the load input is 0, the circuit inputs are inhibited and the D flip-
flops are reloaded with their present vale, thus maintaining the con tent of the
register.

• The feedback connection in each Flip-flop is necessary when D type is used

because a D flip-flop does not have a “no-change” input condition.
• With each clock pulse, the D input determines the next state of the output.
• To leave the output unchanged, it is necessary to make the D input equal to the
present Q output in each flip-flop.
 Registers
Sequential Logic Implementation

• Block diagram of a sequential circuit that uses a register is shown in Fig. 7-4.
• The present state of the register and the external inputs determine the next state
of the register and the values of external outputs. Part of the combinational
circuit determines the next state and the other part generates the outputs. The
next state value from the combinational circuit is loaded into the register with a
clock pulse. If the register has a load input, it must be set to I; otherwise, if the
register has no load input (as in Fig. 7-1), the next state value will be transferred
automatically every clock pulse.
 Registers
Shift Registers

• A register capable of shifting its binary information either to the right or to the left
is called a shift register.
• The logical configuration of a shift register consists of a chain of flip-flops
connected in cascade, with the output of one flip-flop connected to the input of the
next flip-flop. All flip-flops receive a common clock pulse which causes the shift
from one stage to the next.
 Registers
Shift Registers

• Q output of a given flip-flop is connected to the D input of the flip-flop at its right.
Each clock pulse shifts the contents of the register one bit position to the right. The
serial input determines what goes into the leftmost flip-flop during the shift. The
serial output is taken from the output of the rightmost flip-flop prior to the
application of a pulse.
• Thus a unidirectional shift register can function either as a shift-right or as a shift-
left register. Thus a unidirectional shift register can function either as a shift-right
or as a shift-left register.
• The register in Fig. 7-7 shifts its contents with every clock pulse during the
negative edge of the pulse transition.
 Registers
Shift Registers

Serial Transfer
• The serial transfer of information from register A to register B is done with shift
registers, as shown in the block diagram of Fig. 7-8(a). The serial output (SO) of
register A goes to the serial input (SI) of register B. To prevent the loss of
information stored in the source register, the A register is made to circulate its
information by connecting the serial output to its serial input terminal.
• Suppose the shift registers have four bits each. The control unit that supervises the
transfer must be designed in such a way that it enables the shift registers, through
the shift-control signal, for a fixed time duration equal to four clock pulses. This is
shown in the timing diagram of Fig. 7-8(b).
• The shift-control signal is synchronized with the clock and changes value just after
the negative edge of a clock pulse. The next four clock pulses find the shift-control
signal in the I state, so the output of the AND gate connected to the CP terminals
produces the four pulses T1, T2, T3, and T4. The fourth pulse changes the shift
control to 0 and the shift registers are disabled
 Registers
Shift Registers

Serial Transfer
• Assume that the binary content of A before the shift is 1011 and that of B, 0010.
The serial transfer from A to B will occur in four steps as shown in Table 7-1. After
the first pulse T1, the rightmost bit of A is shifted into the leftmost bit of B and, at
the same time, this bit is circulated into the leftmost position of A. The other bits of
A and B are shifted once to the right.
• The previous serial output from B is lost and its value changes from 0 to 1. The next
three pulses perform identical operations, shifting the bits of A into S, one at a
time. After the fourth shift, the shift control goes to 0 and both registers A and B
have the value 1011. Thus, the content of A is transferred into B while the content
of A remains unchanged.
Registers
Shift Registers

Serial Transfer
 Bidirectional Shift Register with Parallel Load
• Shift registers can be used for convening serial data to parallel data, and
vice versa.
• The most general shift register has all the capabilities listed below.
Others may have only some of these functions, with at least one shift
operation.
1. A clear control to clear the register to 0.
2. A CP input for clock pulses to synchronize all operations.
3. A shift-right control to enable the shift-right operation and the serial
input and output lines associated with the shift-right.
4. A shift-left control to enable the shift-left operation and the serial input
and output lines associated with the shift-left.
5. A parallel-bad control to enable a parallel transfer and the n input lines
associated with the parallel transfer.
6. n parallel output lines.
7. A control state that leaves the information in the register unchanged even
though clock pulses are continuously applied.
 Bidirectional Shift Register with Parallel Load
• The s1 and s0 inputs control the mode of operation of the
register as specified in the function entries of Table 7-2.
• When s1s0 = 00. the present value of the register is applied to
the D inputs of the flip-flops. This condition forms a path from
the output of each flip-flop into the input of the same flip-flop.
The next clock pulse transfers into each flip-flop the binary
value it held previously, and no change of state occurs.
• When s1s0 = 01, terminals 1 of the multiplexer inputs have a
path to the D inputs of the flip-flops. This causes a shift-right
operation, with the serial input transferred into flip-flop A4.
• When s1s0= 10, a shift-left operation results, with the other
serial input going into flip-flop A1. Finally, when s1s0 = 11,
the binary information on the parallel input lines is transferred
into the register simultaneously during the next clock pulse.
 Counters

• An electronic counter is a sequential logic circuit that has a clock input

signal and a group of output signals that represent an integer "counts"
value.
MSI counters come in two categories:
Ripple counters (Asynchronous) and synchronous counters.
• In a synchronous counter, the input pulses are applied to all CP inputs of
all flip-flops. The change of state of a particular flip-flop is dependent on
the present state of other flip-flops.

• In a ripple counter, the flip-flop output transition serves as a source for

triggering other flip-flops. In other words, the CP inputs of all flip-flops
(except the first) are triggered not by the incoming pulses but rather by the
transition that occurs in other flip-flops.
 Asynchronous Counters

RIPPLE COUNTERS

Binary Ripple Counter

• The diagram of a 4-bit binary ripple counter is shown in Fig. 7-12.
• All J and K inputs are equal to 1.
• The small circle in the CP input indicates that the flip-flop complements during a
negative-going transition or when the output to which it is connected goes from 1
to 0.
 RIPPLE COUNTERS

Binary Ripple Counter

• To understand the operation of the binary counter, refer to its count sequence
given in Table 7-4.
• It is obvious that lowest-order bit A1 must be complemented with each count
pulse. Every time A1 goes from 1 to 0, it complements A2. Every time A2 goes from
1 to 0, it complements A3, and so on.
• For example, take the transition from count 0111 to 1000. The arrows in the table
emphasize the transitions in this case, A1 is complemented with the count pulse.
Since A1 goes from 1 to 0, it triggers A2 and complements it.
• As a result, A2 goes from 1 to 0, which in turn complements A3, A3 now goes from
1 to 0, which complements A4. The output transition of A4, if connected to a next
stage, will not trigger the next flip-flop since it goes from 0 to 1. The flip-flops
change one at a time in rapid succession, and the signal propagates through the
counter in a ripple fashion. Ripple counters are sometimes called asynchronous
counters.
 RIPPLE COUNTERS

Binary Ripple Counter

 RIPPLE COUNTERS

Binary Ripple Counter

• A binary counter with a reverse count is called a binary down-counter. In a down-
counter, the binary count is decremented by 1 with every input count pulse. The
count of a 4-bit down counter starts from binary 15 and continues to binary counts
14, 13, 12, .... 0 and then back to 15.
• The circuit of Fig. 7-12 will function as a binary down-counter if the outputs are
taken from the complement terminals Q’ of all flip-flops.
 Synchronous Counters
Design a mod – 5 synchronous counters using JK flip-flop.

• Step 1: The number of flip-flops required to design a mod-5 counter

can be calculated using the formula: 2n >= N, where n is equal to no.
of flip-flop and N is the mod number. In this case, the possible value
on n which satisfies the above equation is 3. Hence, the required
number of flip-flops is 3.
• Step 2: The type of flip-flop required to design the counter is JK
flip-flop.
• Step 3: We can draw the state diagram for mod-5 counter describing
the state flow in current and next state as:
Design a mod – 5 synchronous counters using JK flip-flop.
Design a mod – 5 synchronous counters using JK flip-flop.
 Synchronous Counters

• Design a mod – 4 synchronous counters using JK flip-flop.

• Design a mod – 6 synchronous counters using JK flip-flop.