Scan_Insertion
Presented by,
Edwin Lawrence
Content
Scan Design
Scan Styles
Scan Chain
Scan Chain operation
Scan Golden Rules
Scan Inputs and Outputs (Tessent)
Tessent Scan Insertion Flow
Sample Script
Scan Design Rule Violations
Scan Design
• Convert the sequential design into a scan design
• In structured DFT, extra logic and signals are added to the circuit so
as to allow the test according to some predefined procedure.
• Apart from the normal functional mode, such a design will have one
or more test modes.
• Commonly used structured methods are scan and built-in self-test
• The idea in scan design is to obtain controlability and observability
for flip-flops already present in the design.
Scan Styles
• Muxed D flip flop:
• Clocked scan cell
• LSSD scan cell
Muxed D FF
Clocked Scan Cell
• In the clocked scan cell design, input selection is conducted Using two
independent clocks, DCK and SCK.
• DCK- System clock/Functional clock
• SCK – Scan clock / Shift clock
LSSD Scan cell
An LSSD scan cell is used for level
sensitive latch base designs
This scan cell contains two
latches, a master 2 port D latch L1,
and a slave D latch L2. Clocks C, A
and B are used to select between
data input D and the scan input I
to drive +L1 and +L2.
In an LSSD design, either +L1 or
+L2 can be used to drive the
Combinational logic of the design.
How do we do Scan
Convert all flops to scan flops.
Stitch all scan flops to shift registers into scan chain to shift the data in and out to improve the
testability in the core logic.
What is scan insertion?
The process of converting the sequential elements to the scan cells and stitching them to a shift
register to have full controllability and observability in the design is called scan stitching/scan
insertion/scan stitching.
Scan Chain
Scan chains are the elements in scan-based designs that are used to shift-in
and shift-out test data.
A scan chain is formed by a number of flops connected back to back in a
chain with the output of one flop connected to another.
The input of first flop is connected to the input pin of the chip (called scan-
in) from where scan data is fed.
The output of the last flop is connected to the output pin of the chip (called
scan-out) which is used to take the shifted data out.
Scan Chain Operation
Applying scan patterns consists of the following steps:
Loading of the scan chains
Force the primary inputs
Measure the primary outputs
Pulse the capture clock.
Unloading of the scan chains
Unloading and loading of the scan chains steps are merged together for
multiple tests
Loading of Scan chains
Shift 3 times to
place scan data
“101” to scan chains
Active value to scan enable
shifting
Forcing Primary Inputs
Drive the known value
001 from the primary
Inputs
The entire circuit is loaded with
Known values
Measure PO
Pulsing Capture Clock
Change the scan enable to low,
Apply capture clock,
Circuit is in system/ functional mode
New values are captured
on the scan cells
Unloading Scan Chains
Shift 3 times to load
new data “011” to scan
chains
Active value to enable
scan shifting
Internal states are shifted
Out and measured at
Scan-output
Scan Operation Waveform
Scan Golden Rules
1. All internal clocks must be controlled by port level clock (Primary i/p) in Scan
Test mode
2. Asynchronous SET/RESET pins of the flop must be controlled by port level
pins (Primary i/p) in Scan Test mode
3. Gated clock must be enabled in scan test mode.
4. Avoid implementation of combinational feedback circuit. If present, break the
feedback loop for test.
5. Latches must be avoided as much as possible. If present make latch as
transparent.
6. Don’t replace flip-flops of the shift register structure with equivalent scan
flops
7. Clocks should not be used as data in Scan Test mode.
8. Bypass memory in scan test mode.
9. The Scan Enable signal must be buffered adequately.
10. Avoid multicycle paths as much as possible. Ideally Zero.
11. Negative edge flops should be placed in the start of the scan chain.
Basic Scan Insertion
Figure shows a normal digital design
which consists of ‘Combinational Logic’
being driven by a set of Flops and the
outputs registered by another set of Flops.
Step1: The input pattern is shifted
to the stitched flops. During this
mode scan_mode = 1
Basic Scan Insertion Contd...
Step2: The chip is operated for 1
clock cycle in functional mode and the
combinational output is ‘captured’ by
the Flops.
Step3: The results are then
shifted out to chip output
pins and compared against
the expected “good
machine” results
Scan inputs and outputs
Tessent Scan Insertion Flow
# SETUP
Sample Script # Set the context
>set_context dft -scan
# Read the verilog
>read_verilog ../design/cpu.v
# Read the library
>read_cell_library ../library/adk.tcelllib
>read_cell_library ../library/ram.lib
>set_current_design cpu
# Add clocks in the design
>add_clock 0 clk1
>add_clock 0 clk2
>add_clock 0 clk3
>add_clock 0 clk4
>add_clock 0 ramclk
//RUN DRC
>set_system_mode analysis
# Specify constraints to stitch up scan chains
>set_scan_insertion_options -chain_count 100
>analyze_scan_chains
>report_scan_chains
>insert_test_logic -write_in_tsdb On
>report_scan_chains
Scan Design Rule Violations
Violations that prevent Scan Insertion
Fixing Uncontrollable Clocks and Asynchronous Signals
Violations that prevent Data Capture
Contd...
Violations that reduce Coverage
Thank You
