98 Mixed Model Jobs in Tiruppur

You will be joining the Electronics and Technology - Mechatronics and ASIC Solutions team at Schaeffler as a SABER Simulation and Modeling Engineer. Your role will involve leveraging Synopsys SABER to create and integrate advanced simulation models for semiconductor devices and electromechanical systems, enhancing system performance and reliability. Your key responsibilities will include: - Developing simulation models for semiconductor devices like SiC, GaN, and electromechanical systems using SABER. - Engaging in analog component design and modeling using hardware description languages (HDL). - Specifying, designing, and verifying analog/mixed-signal circuits and systems. - Analyzing and optimizing circuit-block details. - Supporting layout processes. - Collaborating with international teams. - Driving innovative IP development. To qualify for this role, you should have: - BE/ME/MTech/MS in Electronics/Electrical Engineering or equivalent. - 2-5 years of experience. - Proficiency in Synopsys SABER and MATLAB. - Knowledge of HDL programming languages (MAST and VHDL AMS). - Familiarity with mathematical analysis tools, regression analysis tools, analog design principles, electronic devices, circuit theories, power electronics design, laboratory equipment, measurement techniques, electronic simulation software (LTSpice, PSpice), and programming languages (C, C++). - Commitment to continual learning. - Fluency in English. - Experience with HDL modeling, mathematical modeling, thermal analysis, signal integrity, EMC, and component testing is advantageous. Schaeffler offers a great company culture, a well-defined career path, opportunities to be a key part of a growing organization, and close collaboration with customers and project teams. The company values mutual respect, diverse perspectives, creativity, and innovation, with a commitment to sustainable value creation through innovation. Exciting assignments and exceptional development opportunities are waiting for you at Schaeffler. Apply now at www.schaeffler.com/careers.,

You will be responsible for designing analog blocks such as amplifiers, comparators, bandgap references, LDOs, ADCs, DACs, PLLs, and oscillators. Your role will involve translating system-level requirements into transistor-level circuit implementations and optimizing designs for performance, power, area, and reliability. You will perform pre-layout and post-layout simulations, conduct Monte Carlo, corner, and noise analysis to ensure robustness, and collaborate with layout engineers to ensure layout matches design intent and meets performance targets. Additionally, you will develop behavioral models (e.g., Verilog-A) for mixed-signal verification and document design specifications, simulation results, and design reviews. Qualifications required for this role include a Bachelors or masters degree in electrical engineering or a related field, along with at least 6 years of experience in analog/mixed-signal IC design. You should have proficiency in transistor-level design and simulation tools, as well as a strong understanding of CMOS/BiCMOS technologies and analog design fundamentals.,

Role Overview: You will be responsible for defining and guiding the architectural direction of complex wireless and multi-antenna system platforms as a Principal / Lead Wireless Communications System Architect at Omni Design. Your role will involve serving as the primary technical interface with customer system teams, leading system modeling and performance analysis, driving architectural decisions across mixed-signal and digital subsystems, and defining system-level specifications for silicon implementations. Key Responsibilities: - Define system architecture for next-generation multi-antenna and SDR-based communication platforms, influencing product strategy and long-term roadmap planning. - Lead technical engagement with strategic customers, representing system trade-offs, negotiating performance specifications, and aligning joint integration plans. - Architect and maintain MATLAB and analytical models capturing the full signal chain, including channel modeling, quantization noise allocation, SNR budgeting, interplay of RF non-linearities, and DSP algorithm design constraints. - Generate precise block-level specifications for digital baseband, calibration engines, channel processing, mixed-signal converters, and RF interfacing elements; ensure internal teams understand the architectural rationale behind these specifications. - Drive alignment between digital architecture, signal processing algorithms, mixed-signal circuit selections, ADC/DAC dynamic range decisions, LO/subsystem noise considerations, and thermal/power constraints. - Collaborate with validation and silicon bring-up teams to ensure post-silicon results trace back to modeled assumptions; define measurement-level KPIs and debug methodologies when deviations arise. - Provide architectural guidance to system engineers, signal processing developers, and hardware design teams; develop reusable models, internal best practices, and system-level methodologies. - Participate in internal architecture reviews, contribute to core IP innovation strategy, and represent the company in technical engagements, standards-relevant discussions, and key customer milestones. Qualifications: - Graduate degree in Electrical Engineering, Communications Engineering, or related field; PhD strongly preferred. - 15+ years of experience in wireless communications system architecture for advanced SDR systems. - Demonstrated ownership of end-to-end communication signal chains, including cascaded error budgeting, quantization trade-offs, and performance modeling across RF, ADC/DAC, and DSP blocks. - Deep expertise in MIMO and multi-user spatial processing architectures, channel estimation, SNR/phase-noise budgets and their mapping into mixed-signal design requirements, system-level modeling using MATLAB or Python. - Ability to articulate complex system decisions to both internal engineering teams and senior-level customers. - Proven leadership in defining specifications consumed by RTL design, mixed-signal design, verification, and system validation teams. - Strong customer communication skills and comfort presenting architectural trade-offs to VP- and CTO-level stakeholders.,

As an AMS Verification Engineer at our company, you will play a crucial role in the verification of complex IPs and SoCs using analog and mixed-signal methodologies. Your responsibilities will include: - Leading and executing AMS verification projects, ensuring high-quality results. - Developing and maintaining testbenches, UVM environments, and test cases. - Performing Model vs. Schematic (MVS) verification and correlating the results effectively. - Setting up and managing VManager regression environments for automated testing. - Collaborating with design, modeling, and system teams to ensure functional correctness. - Debugging simulation failures, identifying root causes, and driving corrective actions. - Providing technical mentorship and contributing to continuous flow improvements. - Working independently and coordinating with global verification teams for project success. Qualifications required for this role include: - Bachelors or Masters degree in Electronics, Electrical Engineering, Microelectronics, or Computer Science. - 8+ years of hands-on experience in SoC/IP-level AMS verification. - Strong knowledge of Verilog AMS, SystemVerilog, Real Number Modeling (RNM), Verilog, and/or VHDL. - Good understanding of UVM methodology and test case development. - Proficiency in Analog/RF design fundamentals and analog block specifications. - Hands-on experience in Model vs. Schematic (MVS) verification flow. - Strong working experience with Cadence design and verification tools. - Proficiency in C, Tcl, and Perl programming; knowledge of Python or SystemC is a plus. - Familiarity with SoC architecture, directed and constrained-random verification methodologies. - Strong analytical and debugging skills; ability to work independently with minimal supervision. - Excellent communication skills to collaborate effectively with cross-functional and global teams. Additionally, it would be beneficial if you have experience in SystemC or mixed-signal co-simulation, exposure to high-speed analog IPs such as SerDes, DDR, or PLLs, and knowledge of scripting for automation and verification flow optimization. Please note that the company's additional details were not provided in the job description.,

As an ML Ops Engineer at GenAI & ML Solutions, your role will involve developing and managing efficient MLOps pipelines tailored for Large Language Models. You will be responsible for automating the deployment and lifecycle management of models in production. Your key responsibilities will include: - Deploying, scaling, and monitoring LLM inference services across cloud-native environments using Kubernetes, Docker, and other container orchestration frameworks. - Optimizing LLM serving infrastructure for latency, throughput, and cost, including hardware acceleration setups with GPUs or TPUs. - Building and maintaining CI/CD pipelines specifically for ML workflows, enabling automated validation and seamless rollouts of continuously updated language models. - Implementing comprehensive monitoring, logging, and alerting systems (e.g., Prometheus, Grafana, ELK stack) to track model performance, resource utilization, and system health. - Collaborating cross-functionally with ML research and data science teams to operationalize fine-tuned models, prompt engineering experiments, and multi-agentic LLM workflows. - Handling integration of LLMs with APIs and downstream applications, ensuring reliability, security, and compliance with data governance standards. - Evaluating, selecting, and incorporating the latest model-serving frameworks and tooling (e.g., Hugging Face Inference API, NVIDIA Triton Inference Server). - Troubleshooting complex operational issues impacting model availability and degradation, implementing fixes and preventive measures. - Staying up to date with emerging trends in LLM deployment, optimization techniques such as quantization and distillation, and evolving MLOps best practices. Qualifications required for this role include: - 3 to 5 years of professional experience in Machine Learning Operations or ML Infrastructure engineering, including experience deploying and managing large-scale ML models. - Proven expertise in containerization and orchestration technologies such as Docker and Kubernetes, with a track record of deploying ML/LLM models in production. - Strong proficiency in programming with Python and scripting languages such as Bash for workflow automation. - Hands-on experience with cloud platforms (AWS, Google Cloud Platform, Azure), including compute resources (EC2, GKE, Kubernetes Engine), storage, and ML services. - Solid understanding of serving models using frameworks like Hugging Face Transformers or OpenAI APIs. - Experience building and maintaining CI/CD pipelines tuned to ML lifecycle workflows (evaluation, deployment). - Familiarity with performance optimization techniques such as batching, quantization, and mixed-precision inference specifically for large-scale transformer models. - Expertise in monitoring and logging technologies (Prometheus, Grafana, ELK Stack, Fluentd) to ensure production-grade observability. - Knowledge of GPU/TPU infrastructure setup, scheduling, and cost-optimization strategies. If you are eager to push the boundaries of AI in financial analytics and thrive in a global, fast-paced environment, this opportunity at GenAI & ML Solutions is for you!,

As a dynamic and motivated candidate at AnjX, you will play a crucial role in transforming global supply chains through AI-driven solutions that enhance efficiency and decision-making. Your primary responsibility will involve developing mathematical models to optimize production planning and inventory management. You will collaborate with the product team to define constraints, objectives, and optimization goals to streamline processes and ensure reliable planning. Key Responsibilities: - Develop mathematical models to optimize production planning and inventory management - Define constraints, objectives, and optimization goals in collaboration with the product team - Perform simulations and scenario analysis to evaluate different planning strategies - Work with the software engineering team to implement linear programming and mixed-integer programming models - Provide research support for new optimization techniques to enhance the software's capabilities Qualifications Required: - Strong understanding of linear programming, optimization techniques, and operations research concepts - Proficiency in tools such as Python, MATLAB, R, or Gurobi for optimization - Mathematical and problem-solving skills to translate business problems into mathematical models effectively - Background in mathematics, engineering, or operations research preferred; knowledge of supply chain and production planning advantageous This is a paid internship opportunity at AnjX, offering a monthly stipend of 8000. If you are passionate about driving operational excellence and reducing environmental impact through innovative solutions, we invite you to join our team in Chennai Office and contribute to our mission of creating platforms that drive speed, reliability, and transparency in supply chain management.,

Role Overview: As an Optimization and ML Modelling Engineer at Sustainability Economics.ai, you will be responsible for designing, developing, and deploying prescriptive models to identify optimal solutions under complex business and operational constraints. Your role will involve formulating and solving optimization problems using advanced mathematical programming and numerical methods. By combining strong analytical thinking with hands-on Python development, you will build models that drive intelligent, data-informed decision-making. Key Responsibilities: - Design, develop, and implement optimization and forecasting models for complex analytical problems. - Apply mathematical programming (linear, nonlinear, integer, and mixed-integer optimization) to operational and decision-making scenarios. - Build, train, and fine-tune machine learning and statistical models for regression, classification, and clustering. - Conduct feature selection, hyperparameter tuning, and performance evaluation using systematic validation techniques. - Integrate ML and optimization algorithms within business or system logic for intelligent decision-making. - Collaborate with cross-functional teams to ensure models are scalable, interpretable, and production-ready. - Stay updated with advancements in optimization algorithms, ML model architectures, and applied AI techniques. Qualifications Required: - Bachelors or Masters degree in Computer Science, Engineering, Applied Mathematics, or related quantitative fields. - 12 years of hands-on experience in machine learning, optimization. - Strong background in mathematical modeling, statistics, or operations research. - Experience in production-grade model deployment and performance monitoring. Additional Company Details: Sustainability Economics.ai is a global organization pioneering the convergence of clean energy and AI. By integrating AI-driven cloud solutions with sustainable energy, the company creates scalable, intelligent ecosystems driving efficiency and innovation across industries. The company is guided by exceptional leaders with expertise in finance, policy, technology, and innovation, committed to making long-term efforts towards sustainable energy solutions. What You'll Do: - Build and train ML and optimization models for production-scale use cases. - Design intelligent data workflows and pipelines to support predictive and prescriptive analytics. - Translate business objectives into mathematical formulations for effective optimization. - Collaborate with engineering and research teams to develop scalable ML solutions. - Develop APIs and tools to make ML capabilities accessible across systems. - Continuously monitor, maintain, and enhance model accuracy and scalability. What You Will Bring: - Proven track record of implementing ML and optimization models in production environments. - Strong mathematical and statistical foundation. - Passion for scalable systems, automation, and applied problem-solving. - Startup DNA with a bias for action, comfort with ambiguity, love for fast iteration, and a flexible and growth mindset. Why Join Us: - Shape a first-of-its-kind AI + clean energy platform. - Work with a small, mission-driven team obsessed with impact. - An aggressive growth path. - A chance to leave your mark at the intersection of AI, Optimization, and sustainability.,

You are being hired for the role of Sr. Structural Design Manager at a top MNC with a focus on Architecture, structural, MEP, and Interior design background. With exposure to UAE projects including residential, commercial, mixed-use, and institutional buildings, the job is based in Bangalore. You are expected to have a Master's degree in Civil Engineering or Structural Engineering and a minimum of 25 years of experience, with at least 10 years in Structural design and 5 years in a managerial role. Strong knowledge of UAE codes, authority procedures, and construction practices is required. Expertise in software tools like Revit Structure, AutoCAD, ETABS, STAAD Pro, and SAFE is mandatory. Your role involves leadership and management of the structural design team, overseeing workload, ensuring timely delivery, and providing design direction for various projects. **Key Responsibilities:** - **Leadership and Management** - Lead and manage the structural design team in Bangalore. - Oversee team workload, performance, mentoring, and professional development. - Ensure timely delivery of design packages as per Dubai office requirements and project schedules. - Conduct team performance reviews and promote professional development. - Manage workload allocation and resource planning for multiple ongoing projects. - **Design & Technical Coordination** - Review, guide, and approve structural design concepts, calculations, models, and drawings. - Ensure compliance with UAE building codes, authority regulations, and international standards. - Provide design direction for reinforced concrete and steel structures used in UAE projects. - Supervise design at all stages - concept, schematic, detailed design, and IFC. - Coordinate closely with architects and MEP teams for structural integration and constructability. - Act as the primary liaison between Bangalore and Dubai structural departments. - **Project Management & Delivery** - Manage multiple projects from concept to IFC stage. - Establish project design schedules, monitor progress, and maintain quality control. - Coordinate directly with the Dubai office for project milestones, design updates, and technical clarifications. - Support the Dubai project management team in client presentations and design reviews. - Coordinate design submissions for Dubai-based authority approvals. - Ensure timely delivery of all structural deliverables for multiple projects. - **Quality & Standards** - Follow company design standards, templates, and QA/QC procedures. - Review design deliverables before submission to ensure accuracy and compliance. - Maintain proper documentation and revision control across all project stages. - Conduct internal audits and peer reviews to maintain design excellence. - Promote sustainability and energy-efficient design practices in line with UAE Green Building standards. If you are interested in this opportunity, please share your resume with Asha G at asha.g@inspirationmanpower.co.in or contact her at 7624836555.,

As an ASIC Verification Engineer, you will collaborate with design and verification engineers to develop and execute robust verification strategies. You will be responsible for creating and maintaining testbenches and test cases aligned with test plans and design specifications. Additionally, you will develop, enhance, and maintain UVM-based verification frameworks to ensure the reliability of ASIC design. Your role will involve delivering automated regression suites to reduce risk and contribute to unit-level and system-level verification deliverables for complete test coverage. Furthermore, you will design and maintain a verification environment for testing RTL implementations against reference models developed in MATLAB and Python. You will also execute and automate regression test runs across design iterations and analyze code and functional coverage to provide detailed feedback and recommendations to the design and verification teams. Your responsibilities will include generating and presenting verification reports, highlighting test results, coverage metrics, and improvement areas. Qualifications: - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. - 5+ years of experience in ASIC verification or digital design verification. - Strong proficiency in SystemVerilog for functional verification. - Hands-on experience with UVM (Universal Verification Methodology). - Familiarity with Cadence Xcelium or similar industry-standard simulators. - Excellent analytical and problem-solving skills with a strong attention to detail. Preferred Skills: - Experience working in Linux-based environments. - Proficiency in scripting languages such as Python or TCL for test automation. - Understanding of DSP algorithms and mixed-signal verification concepts. The company provides dental insurance, health insurance, and vision insurance as part of the benefits package. This is a full-time, contract position with an in-person work location.,

Role Overview: As a Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on cutting-edge technologies to develop world-class products, collaborating with cross-functional teams, and meeting performance requirements to drive digital transformation and create a smarter, connected future for all. Key Responsibilities: - Hands-on experience in analog circuit design - Architecture, design, and development of analog/mixed signal hard macros for the PLL IP Design team - Designing multiple analog building blocks such as Bias, References, Op-amp, LDOs, VCO/DCO, and High-Speed custom digital components - Custom circuit design in the latest FinFET CMOS processes technologies and support customer integration and testing - Setting up, running, and analyzing circuit simulations (spice) and creating behavior models - Collaborating with Layout, Digital designer, PD & HSIO Bench/ATE Team - Participating in internal customer requirements discussions to create design specifications Qualifications Required: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years of Hardware Engineering or related work experience - OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 5+ years of Hardware Engineering or related work experience - OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years of Hardware Engineering or related work experience Additional Details: Qualcomm Mixed-Signal IP team in Bangalore, India is actively seeking analog circuit designers with 3-12 years of experience to work on delivering analog and mixed-signal integrated circuits for high-speed PLL/DLL/LDO IP for SoC products. The design goals include addressing low-power & low voltage analog designs for Qualcomm's wireless products, focusing on leading-nodes like finfets & beyond. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require accommodation during the application/hiring process, you may contact disability-accommodations@qualcomm.com or Qualcomm's toll-free number.,

As a Senior AMS Verification Lead & Architect at Eximietas Design, you will play a crucial role in verifying pre-silicon designs and ensuring compliance with specifications. Your responsibilities will include: - Leading AMS verification by reviewing design specifications and defining/ executing a verification plan. - Architecting, implementing, and automating analog, digital, and AMS test benches. - Creating System Verilog real number analog behavioral models, monitors, and checkers. - Collaborating with analog, digital, and system designers to verify the implementation meets system requirements. - Working with digital design verification engineers to architect and implement tests for analog/digital interfaces. - Leading the development of AMS simulation and verification methodologies. For this role, you should meet the following minimum qualifications: - Bachelor's degree in Electrical Engineering, relevant technical field, or equivalent practical experience. - 15+ years of AMS design verification experience. - Proficiency in System Verilog and real number modeling. - Experience with Cadence Spectre and AMS simulator. - Strong understanding of analog IPs like Bandgap, oscillator, ADC/DAC, LDO, PLL, and Serdes. - Proficiency in a scripting language like Python, Tcl, or Perl is mandatory. Preferred qualifications for this role include: - Experience in developing verification methodology, flows, and automation. - Hands-on experience with AMS chip bring-up and debug. - Analog/Mixed Signal Circuit verification experience with tape-out experience in various analog IPs. - Good understanding of CMOS and VLSI technologies including device physics, layout effects, sub-micron effects, and device reliability. If you are passionate about advancing analog layout design and have the required qualifications, we encourage you to share your updated resume at maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are excited to connect with talented engineers like you who can contribute to our team at Eximietas Design.,

As a Digital Design Manager at Omni Design Technologies, you will play a crucial role in managing the digital team and leading the development of mixed-signal System-on-Chip (SOC) solutions for next-generation automotive and space applications. Your responsibilities will include: - Managing the digital team by hiring and retaining top talent - Leading the SOC integration design team to develop and productize next-generation mixed-signal RF/communication SOCs - Collaborating with cross-functional project teams to define product specifications, system architecture, HW/SW partitioning, and execution plan - Implementing best SoC development practices and enhancing design methodology for improved efficiency and predictability - Delivering chip architecture, design, integration, programming model, verification, and managing hand-off to backend - Supporting Silicon and System Validation, system integration, and production testing - Driving innovation and providing leadership to ensure world-class system solutions and flawless execution Qualifications: - BSEE Required, MSEE Preferred - Proven track record in the high-performance/high-volume semiconductor industry - Expertise in SoC, embedded CPU and bus architectures, networking, control interfaces, and communications/DSP algorithms - Proficiency in digital IC design, design for low power and high speed, design for test (DFT), and system modeling - Strong experience in RTL coding, verification methodologies, power analysis, timing analysis, and design environments like Cadence/Synopsys - Experience in directed and constrained random verification, UVM methodology, FPGA emulation, lab debug, and chip validation - Ability to plan and execute projects, make design tradeoffs, and achieve performance, power, die size, and schedule targets - Self-motivated with excellent communication skills and the capability to excel in a fast-paced environment - Senior Management experience preferred Experience: - 10+ years in RTL design and verification of silicon - At least 3+ years leading low-power mixed-signal SOC design - Proficiency in FPGA architecture specification and design for high-speed serial protocols - Experience working with Analog/RF team in developing SERDES, CDR, and PLL/DLL designs - Strong background in analog/mixed-signal integrated SOC Development - Knowledge of Verilog/System Verilog, C/C++/SystemC, UVM, Scripting languages like Perl/Python - Excellent technical documentation skills and interpersonal skills - Experience in a startup environment Expectations: - Putting together the RTL for the Full chip - Evaluating IP licenses like PCIe, LPDDR4, JESD 204C PHY - Developing BIST and RTL for state machines and interfaces - Collaborating with the Verification Team on FC Simulation test suites - Assisting with FC simulations debug and timing issues resolution - Mentoring and leading a team of Digital design engineers - Working with Systems and Test engineering team for part validation and production release You can contact Uday at Mulya Technologies via muday_bhaskar@yahoo.com for further information.,

As a Data Science Optimization role at Tata Insights and Quants, you will be responsible for applying Optimization/ Simulation algorithms using a variety of tools to enhance process efficiency across business functions. Your key responsibilities will include: - Performing detailed analysis of business problems and technical environments to design solutions - Converting business problems into mathematical models using techniques like Linear/Mixed Integer Programming - Applying various Optimization/ Simulation algorithms such as Simplex, Interior Point, Cutting Plain, Dynamic Program, among others - Implementing Optimization/ Simulation in areas like Logistics/ Inventory planning, Job Scheduling, Stock Cutting, and Network Optimization - Building mathematical optimization models using tools like AIMMS, CPLEX, GLPK - Leading Proof of Concepts, documenting solutions, and working in a problem-solving environment - Collaborating with different functional teams to implement models and monitor outcomes - Identifying opportunities for leveraging organization data and applying Optimization/ Simulation techniques to improve process efficiency across various business functions In terms of experience and skills, you should have: - Experience in Manufacturing, Aviation, and Logistics - 3+ years of work experience in optimization, simulation, and data science - Proficiency in tools like AIMMS, CPLEX, GLPK, GUROBI - Knowledge of building Predictive models and Forecast models will be beneficial - Familiarity with Python and R will be an added advantage Education qualification required for this role is a Bachelors/ Master degree in Operations Research, (Applied) Mathematics, (Applied) Statistics, Industrial Engineering, or other relevant disciplines with significant experience in mathematical optimization. Please feel free to reach out to us at careers@tataiq.com for further information.,

Job Description You will be working as a Mixed-Signal Verification Engineer focusing on advanced DSP-based communication and AI interconnect chips. Your role will involve developing behavioral models for analog blocks, conducting mixed-signal dynamic verification, and collaborating with analog and digital design teams to validate next-gen coherent DSP solutions. Key Responsibilities - Perform behavioral modeling (BM) of analog designs to enable digital verification. - Conduct mixed-signal dynamic verification using chip-level digital design tools. - Write, simulate, and debug Verilog/SystemVerilog code for verification. - Use Cadence Virtuoso Schematics to interface with analog designs. - Develop test plans, verification strategies, and scalable testbench automation. - Collaborate with DSP, analog, and digital engineering teams to validate high-speed designs. - Present verification results, maintain coverage metrics, and ensure first-pass success in silicon. Minimum Qualifications - 5+ years of mixed-signal verification experience. - Strong background in Behavioral Modelling (BM) for analog-to-digital verification. - Hands-on Verilog/SystemVerilog verification coding. - Familiarity with Virtuoso Schematics. - Basic understanding of analog design fundamentals. Preferred Qualifications - Experience with UVM (Universal Verification Methodology). - Background working with both Synopsys and Cadence verification tools. - Understanding of advanced verification infrastructure such as simulators, waveform viewers, coverage, and execution automation. - Proven track record of building portable/scalable test environments. - Strong communication skills; ability to write test plans, document results, and present to multi-functional teams. Job Description You will be working as a Mixed-Signal Verification Engineer focusing on advanced DSP-based communication and AI interconnect chips. Your role will involve developing behavioral models for analog blocks, conducting mixed-signal dynamic verification, and collaborating with analog and digital design teams to validate next-gen coherent DSP solutions. Key Responsibilities - Perform behavioral modeling (BM) of analog designs to enable digital verification. - Conduct mixed-signal dynamic verification using chip-level digital design tools. - Write, simulate, and debug Verilog/SystemVerilog code for verification. - Use Cadence Virtuoso Schematics to interface with analog designs. - Develop test plans, verification strategies, and scalable testbench automation. - Collaborate with DSP, analog, and digital engineering teams to validate high-speed designs. - Present verification results, maintain coverage metrics, and ensure first-pass success in silicon. Minimum Qualifications - 5+ years of mixed-signal verification experience. - Strong background in Behavioral Modelling (BM) for analog-to-digital verification. - Hands-on Verilog/SystemVerilog verification coding. - Familiarity with Virtuoso Schematics. - Basic understanding of analog design fundamentals. Preferred Qualifications - Experience with UVM (Universal Verification Methodology). - Background working with both Synopsys and Cadence verification tools. - Understanding of advanced verification infrastructure such as simulators, waveform viewers, coverage, and execution automation. - Proven track record of building portable/scalable test environments. - Strong communication skills; ability to write test plans, document results, and present to multi-functional teams.

As a Designer at FXCollaborative, you will be part of an established architectural, interior design, planning, and urban design firm based in Brooklyn, NY. Our firm is known for its dedication to sustainable design and has received recognition through various design awards and publications. We work on a wide range of projects including corporate, civic, cultural, educational, transportation, residential, hospitality, office, retail, and mixed-use developments. **Key Responsibilities:** - Demonstrate strong conceptual design ability and advanced graphic representation skills. - Conduct programming research, zoning research, massing, orientation studies, and design studies. - Create presentation drawings to convey design intent effectively. - Produce scale drawings, 3-D models, sketches, illustrations, and physical models to visualize design ideas. - Research materials, products, and furnishings aligned with project design goals. - Assist in the development of construction documents and coordinate the review of shop drawings during the construction phase. **Qualifications Required:** - Bachelor's Degree in a related field. - 3-5 years of post-graduation experience. - Ability to prioritize tasks and handle multiple responsibilities. - Proactive, detail-oriented, and self-motivated individual. - Strong teamwork ethic and excellent interpersonal, written, and verbal communication skills. - Proficiency in Rhino, Grasshopper, AutoCAD, Revit/BIM, Adobe Graphics Suite, and other design software. If you are passionate about design and meet the qualifications for the Designer position at FXCollaborative, we encourage you to submit your application online. As a Designer at FXCollaborative, you will be part of an established architectural, interior design, planning, and urban design firm based in Brooklyn, NY. Our firm is known for its dedication to sustainable design and has received recognition through various design awards and publications. We work on a wide range of projects including corporate, civic, cultural, educational, transportation, residential, hospitality, office, retail, and mixed-use developments. **Key Responsibilities:** - Demonstrate strong conceptual design ability and advanced graphic representation skills. - Conduct programming research, zoning research, massing, orientation studies, and design studies. - Create presentation drawings to convey design intent effectively. - Produce scale drawings, 3-D models, sketches, illustrations, and physical models to visualize design ideas. - Research materials, products, and furnishings aligned with project design goals. - Assist in the development of construction documents and coordinate the review of shop drawings during the construction phase. **Qualifications Required:** - Bachelor's Degree in a related field. - 3-5 years of post-graduation experience. - Ability to prioritize tasks and handle multiple responsibilities. - Proactive, detail-oriented, and self-motivated individual. - Strong teamwork ethic and excellent interpersonal, written, and verbal communication skills. - Proficiency in Rhino, Grasshopper, AutoCAD, Revit/BIM, Adobe Graphics Suite, and other design software. If you are passionate about design and meet the qualifications for the Designer position at FXCollaborative, we encourage you to submit your application online.

Role Overview: You will be responsible for developing, maintaining, and optimizing analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. Additionally, you will create, modify, and optimize SKILL scripts for automation of layout, schematic, verification, and design environment tasks. Your role will also involve managing Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries. Key Responsibilities: - Develop, maintain, and optimize analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. - Create, modify, and optimize SKILL scripts for automation of layout, schematic, verification, and design environment tasks. - Manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries. - Work extensively with the OpenAccess (OA) database API (using C++, Python, Tcl) to read, write, and manipulate design data including schematic, layout, connectivity, and library information. - Develop automation tools and workflows leveraging OpenAccess to integrate schematic and layout views, support PDK/CDK validation, and assist design data migration or QA. - Integrate and validate foundry PDK/CDK devices, parameterized cells (pCells), symbols, DRC/LVS decks, and simulation models with EDA tools. - Troubleshoot issues related to PDK integration, OA database consistency, schematic-layout synchronization, and environment setups. - Document technical processes, create reusable automation scripts, and contribute to team best practices. - Collaborate with AI and software teams to integrate EDA tools into Maieutics AI co-pilot platform and support continuous improvement of design automation. Qualification Required: - 38 years hands-on experience working with Cadence Virtuoso analog/mixed-signal design flows. - Strong proficiency in SKILL scripting for automation within Cadence layout and schematic environments. - Proven experience managing and customizing CDF files for parametric device libraries in Cadence. - Hands-on experience with OpenAccess (OA) database API: Familiarity with OA schema, ability to program in C++, Python, or Tcl to develop tools/scripts that access and modify OA layout and schematic data. - Deep understanding of foundry PDK/CDK structures, including parameterized cells, symbols, device models, layout generators, and associated design-rule decks. - Experience automating schematic and library processes using scripting languages (SKILL, Tcl, Python). - Solid knowledge of schematic editors/viewers and maintaining schematic-layout synchronization (LVS/Schematic Driven Layout). - Strong UNIX/Linux command-line skills and scripting abilities. - Experience with version control systems/tools used in EDA environments (Git, SOS, or equivalent). - Excellent communication skills and ability to operate effectively in a startup team environment.,

Role Overview: Chiplogic Technologies is looking for a skilled Senior AMS (Analog Mixed-Signal) Design Verification Engineer with expertise in Power Management ICs (PMICs) to join their semiconductor design team. As a Senior AMS Design Verification Engineer, you will be responsible for developing and executing verification strategies for complex AMS designs, ensuring functionality, performance, and reliability across process, voltage, and temperature variations. You will collaborate with various teams to deliver high-quality verification for cutting-edge PMIC products. Key Responsibilities: - Develop and implement comprehensive AMS verification plans and testbenches for PMIC and mixed-signal designs. - Create behavioral models of analog blocks using Verilog-AMS, SystemVerilog, or wreal modeling techniques. - Perform top-level mixed-signal simulations integrating analog and digital domains. - Drive functional verification of PMIC features such as regulators, DC-DC converters, LDOs, battery chargers, power sequencing, etc. - Define test coverage goals, verification strategies, and methodologies in collaboration with analog and digital design teams. - Develop automated regression environments for mixed-signal verification. - Debug simulation issues and identify root causes with cross-functional teams. - Ensure verification completeness through functional coverage analysis and formal methods. - Support silicon validation teams during post-silicon bring-up and debugging. - Contribute to methodology improvements and best practices in AMS verification. Qualifications Required: - Bachelors or Masters degree in Electrical, Electronics, or VLSI Engineering. - 6-12 years of experience in AMS design verification within the semiconductor industry. - Strong understanding of PMIC architectures, analog circuits (LDOs, DC/DC converters, ADCs, references), and power sequencing. - Hands-on experience with Verilog-AMS / SystemVerilog / UVM-MS environments. - Proficiency in Cadence Virtuoso, Spectre, AMS Designer, Synopsys VCS AMS, or equivalent EDA tools. - Good understanding of digital verification flows, coverage-driven verification, and scripting automation (Python, Perl, or TCL). - Familiarity with model abstraction, corner analysis, and mixed-signal co-simulation techniques. - Excellent problem-solving, analytical, and debugging skills. - Strong communication and collaboration abilities across analog, digital, and system teams. Additional Details: Chiplogic Technologies is an IP and Product Engineering Services company founded in 2018, specializing in high-quality services in the Semiconductor, Systems, IoT, and AI/ML domains. The company offers turnkey solutions spanning from concept to silicon, along with system-level IoT and AI/ML services. Leveraging its proprietary VISARD framework, Chiplogic drives innovation in video synthesis and real-time dynamics. Chiplogic is committed to delivering dependable engineering solutions for its clients. What We Offer: - Opportunity to work on industry-leading PMIC and AMS designs. - Collaborative and innovation-driven work culture. - Competitive compensation with performance-based rewards. - Professional development and career growth in advanced semiconductor design. Role Overview: Chiplogic Technologies is looking for a skilled Senior AMS (Analog Mixed-Signal) Design Verification Engineer with expertise in Power Management ICs (PMICs) to join their semiconductor design team. As a Senior AMS Design Verification Engineer, you will be responsible for developing and executing verification strategies for complex AMS designs, ensuring functionality, performance, and reliability across process, voltage, and temperature variations. You will collaborate with various teams to deliver high-quality verification for cutting-edge PMIC products. Key Responsibilities: - Develop and implement comprehensive AMS verification plans and testbenches for PMIC and mixed-signal designs. - Create behavioral models of analog blocks using Verilog-AMS, SystemVerilog, or wreal modeling techniques. - Perform top-level mixed-signal simulations integrating analog and digital domains. - Drive functional verification of PMIC features such as regulators, DC-DC converters, LDOs, battery chargers, power sequencing, etc. - Define test coverage goals, verification strategies, and methodologies in collaboration with analog and digital design teams. - Develop automated regression environments for mixed-signal verification. - Debug simulation issues and identify root causes with cross-functional teams. - Ensure verification completeness through functional coverage analysis and formal methods. - Support silicon validation teams during post-silicon bring-up and debugging. - Contribute to methodology improvements and best practices in AMS verification. Qualifications Required: - Bachelors or Masters degree in Electrical, Electronics, or VLSI Engineering. - 6-12 years of experience in AMS design verification within the s

You will be responsible for developing and executing AMS verification plans for mixed-signal IP and SoCs. This will involve creating and validating behavioral models using Verilog-A for analog and mixed-signal blocks. You will also implement and optimize AMS testbenches in the Xcelium simulation environment. Collaboration with analog and digital designers to verify top-level integration and system performance will be a key aspect of your role. In addition, you will be expected to debug and resolve complex AMS simulation and modeling issues. Your contribution to the development of AMS verification methodologies and best practices is crucial. Regression testing and coverage analysis must be performed to ensure design robustness. Lastly, documenting verification plans, results, and technical reports will be part of your responsibilities. ,

Role Overview As an EDA Engineer, you will be responsible for developing, maintaining, and optimizing analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. You will create, modify, and optimize SKILL scripts for automation of layout, schematic, verification, and design environment tasks. Additionally, you will manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries. Your role will involve extensive work with the OpenAccess (OA) database API to read, write, and manipulate design data using C++, Python, and Tcl. Key Responsibilities - Develop, maintain, and optimize analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. - Create, modify, and optimize SKILL scripts for automation of layout, schematic, verification, and design environment tasks. - Manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries. - Work extensively with the OpenAccess (OA) database API (using C++, Python, Tcl) to read, write, and manipulate design data including schematic, layout, connectivity, and library information. - Develop automation tools and workflows leveraging OpenAccess to integrate schematic and layout views, support PDK/CDK validation, and assist design data migration or QA. - Integrate and validate foundry PDK/CDK devices, parameterized cells (pCells), symbols, DRC/LVS decks, and simulation models with EDA tools. - Troubleshoot issues related to PDK integration, OA database consistency, schematic-layout synchronization, and environment setups. - Document technical processes, create reusable automation scripts, and contribute to team best practices. - Collaborate with AI and software teams to integrate EDA tools into Maieutics AI co-pilot platform and support continuous improvement of design automation. Required Skills & Experience - 3-8 years of hands-on experience working with Cadence Virtuoso analog/mixed-signal design flows. - Strong proficiency in SKILL scripting for automation within Cadence layout and schematic environments. - Proven experience managing and customizing CDF files for parametric device libraries in Cadence. - Hands-on experience with OpenAccess (OA) database API, with the ability to program in C++, Python, or Tcl to develop tools/scripts that access and modify OA layout and schematic data. - Deep understanding of foundry PDK/CDK structures, including parameterized cells, symbols, device models, layout generators, and associated design-rule decks. - Experience automating schematic and library processes using scripting languages (SKILL, Tcl, Python). - Solid knowledge of schematic editors/viewers and maintaining schematic-layout synchronization (LVS/Schematic Driven Layout). - Strong UNIX/Linux command-line skills and scripting abilities. - Experience with version control systems/tools used in EDA environments (Git, SOS, or equivalent). - Excellent communication skills and ability to operate effectively in a startup team environment. Preferred Qualifications - Previous work experience at Cadence or semiconductor companies specializing in Virtuoso toolchains. - Experience with Spectre, ADE simulation, and analog verification flows. - Understanding of semiconductor process technology and device physics applicable to analog/mixed-signal design. - Familiarity with AI/ML integration in design tools is a plus.,

Role Overview: You will be responsible for structural Revit modelling of building structures across various typologies like mixed-use, residential, retail, and commercial developments. Your role will involve collaborating with multidisciplinary teams to ensure successful project delivery in line with quality, program, and budget expectations. Key Responsibilities: - Collaborate with architectural, MEP, interior design, landscape, facade, and other multidiscipline teams to develop integrated Structural BIM models aligning with architectural design intent. - Create detailed 3D models of structural systems in Revit using automated digital workflows. - Perform daily drafting duties for all structural design requirements. - Produce accurate record drawings and provide CAD/BIM related assistance for project and Discipline engineers. - Assist in document preparation and submission to local authorities for approvals. - Prepare detailed drawings as per project requirements. - Communicate and coordinate with all disciplines and stakeholders, including Clients, on a daily basis. - Develop parametric families and components for structural elements to enhance modelling efficiency. - Support the development of digital automation. - Ensure accuracy and completeness of structural systems representation in the BIM model according to local standards in the Middle East. - Stay updated with international and UAE regional codes, standards, and best practices in structural engineering digital delivery. - Conduct regular clash detection and quality checks on BIM models to ensure coordination and compliance with project standards, industry best practices, and regulatory requirements. - Review model elements for accuracy, consistency, and constructability. Qualifications Required: - Bachelors degree in Civil or Structural Engineering from an accredited institution. - Minimum of 12 years of experience in structural design modelling, preferably with active involvement in Middle East region projects within international multidisciplinary consultancies. - Strong knowledge of regional authority requirements, local construction practices, and Middle East design codes and regulations. Additional Company Details: This section is omitted as no additional details of the company are present in the provided job description.,