11 Vmm Jobs nearby Mysore

Role Overview: You will be part of the Hardware Platform Group, specializing in FPGA verification. Your responsibilities will include crafting the DV architecture, test plan, coverage plan, and ensuring bug-free RTL for first-pass success on the board. Collaboration with remote teams based in the US and Italy will be a key part of your role. Key Responsibilities: - Lead and mentor a team of verification engineers to develop robust test benches, coverage plans, and constrained random tests. - Ensure high-quality FPGA/ASIC designs through sophisticated verification techniques and comprehensive debugging. - Contribute to the adoption and evolution of verification methodologies like UVM/VMM to improve team efficiency. - Partner with architects, logic designers, and software engineers to align on requirements and deliver high-performance products. - Strengthen product reliability and performance to enhance Cisco's reputation and customer trust in hardware solutions. Qualifications Required: - Bachelor's Degree / Master's Degree in Electrical or Computer Engineering with 7+ years of experience in design verification. - Proficiency in OOPs, Verilog & System Verilog. - Confirmed verification skills in FPGA, planning, debugging, and testing. - Project-based work experience with UVM/VMM methodologies. - Experience in architecting the testplan & test bench. Additional Details of the Company: Cisco is a company where every individual brings their unique skills and perspectives to power an inclusive future for all. Employees are encouraged to learn and develop at every stage, with a focus on unlocking potential. The company's technology, tools, and culture support hybrid work trends, allowing employees to give their best. Cisco values bringing communities together, with employees collaborating in employee resource organizations to foster belonging, learn to be informed allies, and make a difference. Paid time off to volunteer is offered to allow employees to give back to causes they are passionate about. Cisco's purpose is driven by its people, making it a worldwide leader in technology that powers the internet. The company's focus is on helping customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet sustainability goals for a more inclusive future.,

As a Verification Engineer, you will be responsible for designing and developing test benches using HVLs like System Verilog, Specman, etc. Your deep expertise in Verification Methodologies such as OVM, UVM, VMM will be crucial in creating verification environments and test plans. Additionally, having domain expertise in Networking protocols, Interface protocols like PCIe, USB, SATA, or SoC Verification will be a plus. Your familiarity with scripting languages and good communication skills will enable you to excel in this role. If you have a BE/B.Tech/ME/M.Tech or equivalent in ECE/EEE, this position is perfect for you. - Design and develop test benches using HVLs like System Verilog, Specman, etc. - Utilize expertise in Verification Methodologies like OVM, UVM, VMM to create verification environments and test plans. - Apply domain expertise in Networking protocols, Interface protocols like PCIe, USB, SATA, or SoC Verification. - Use scripting languages to enhance verification processes. - Communicate effectively and collaborate as a valuable team player. - BE/B.Tech/ME/M.Tech or equivalent in ECE/EEE. - Deep expertise in Verification Methodologies like OVM, UVM, VMM. - Experience in creating verification environment and test plans. - Domain expertise in Networking protocols / Interface protocols like PCIe, USB, SATA, SoC Verification is a plus. - Familiarity with scripting languages. - Good communication skills with the ability and desire to work as a good team player.,

Role Overview: You are part of the Hardware Platform Group, specializing in FPGA verification. Your responsibilities include crafting DV architecture, test plans, and coverage plans for sophisticated data-path and challenging control-path FPGAs. You will work with industry-standard tools for simulation, linting, coverage, and assertions to ensure a robust verification process. Collaboration with remote teams in the US and Italy is essential for the successful delivery of bug-free RTL for first-pass success on the board. Key Responsibilities: - Lead and mentor a team of verification engineers to develop robust test benches, coverage plans, and constrained random tests. - Ensure high-quality FPGA/ASIC designs through sophisticated verification techniques and comprehensive debugging. - Contribute to the adoption and evolution of groundbreaking verification methodologies like UVM/VMM to enhance team efficiency and performance. - Partner with architects, logic designers, and software engineers to align on architecture, micro-architecture, and system-level requirements. - Play a pivotal role in delivering next-generation, high-performance FPGA and ASIC products for Cisco's networking solutions. - Ensure product reliability and performance to strengthen Cisco's reputation and customer trust in its hardware solutions. Qualifications Required: - Bachelor's Degree / Master's Degree in Electrical or Computer Engineering with a minimum of 7 years of experience in design verification. - Proficiency in Object-Oriented Programming, Verilog, and System Verilog. - Confirmed verification skills in FPGA, planning, problem-solving, debugging, adversarial testing, and random testing. - Project-based work experience with UVM/VMM methodologies. - Experience in architecting the test plan and test bench. Additional Details: Cisco is committed to creating an inclusive future where every individual's unique skills and perspectives contribute to the company's purpose. Employees at Cisco experience continuous learning and development opportunities, supported by a culture that pioneered hybrid work trends. Collaboration is encouraged through employee resource organizations, fostering belonging, learning to be informed allies, and making a difference. Paid time off for volunteering allows employees to give back to causes they are passionate about, with nearly 86% participation.,

As a Verification Engineer at our company, your role will involve developing test plans for features related to Block/Core/SOC and writing functional coverage for these features. You will be responsible for architecting and developing scalable and re-usable testbenches within the verification methodology framework. Your tasks will also include building pseudo-random tests to ensure full functional coverage, debugging regression failures, analyzing functional coverage gaps, and enhancing tests to cover these gaps effectively. You will be expected to think creatively to stress the DUT and verify it efficiently. In addition, you will lead the documentation of the verification strategy, including test plans, verification environment, pseudo-random tests, and more. You will also lead reviews with design and architecture teams to drive improvements in verification quality and efficiency. Key Responsibilities: - Develop test plans for features related to Block/Core/SOC - Write functional coverage for the developed features - Architect and develop scalable and re-usable testbenches - Build pseudo-random tests to achieve full functional coverage - Debug regression failures and analyze functional coverage gaps - Lead documentation of verification strategy - Lead reviews with design and architecture teams - Drive improvements in verification quality and efficiency Qualifications Required: - Bachelor's degree in Electrical Engineering or related field with 8+ years of experience, or Master's degree with 6+ years of experience - 6+ years of experience in writing and debugging complex test benches - Deep understanding of verification aspects including testbench building, test plan development, pseudo-random tests, and functional coverage - Proficiency in System Verilog and verification methodologies like UVM/VMM/OVM - Strong command over fundamental OOP principles - Understanding of complex protocols such as PCIe or other multi-layered protocols - Ability to work independently and deliver results - Knowledge of PCI Express protocol is desired Thank you for considering a career with our company.,

You will be the NPQ Lead - Metallurgy & Metrology at Ather, based in IBC, Bangalore. Aligned with the Lead - New Product Quality, you will be a member of the New Product Quality team. **Role Overview:** - Establish Metrology and Metallurgy labs and lead their functions for faster and accurate test data. - Develop measurement methods for components and continuously improve measurement technology. - Approve material, process, heat treatment, and surface modification techniques based on applications. - Provide technical support for root cause analysis and failure analysis using a methodological approach. - Lead periodic DFMEA reviews and implement control mechanisms to reduce RPN. - Review and approve standards, specifications, and process controls associated with Material technology during manufacturing. - Coordinate with staff members to resolve technical problems related to Metallurgy and Materials. **Key Responsibilities:** - Strong fundamentals on Measurement technology, first principles based measurement. - Competent in interpreting drawings and making measurement plans. - Strong fundamentals on Metallurgy of Steels and Aluminum alloys. - Fundamentals on Heat treatment and Surface coating technologies. - Knowledge of Plastics, Rubbers, and Paints. - Knowledge of castings, Forging, fabrication, welding. - Operation of measurement equipment like CMM, FARO, VMM, scanning techniques. - Operation of Material characterization techniques including Optical microscopes, Hardness testers, Tensile testers. - Operation of SEM, DSC, TGA. - Knowledge of characterization techniques for evaluating material properties. **Qualifications Required:** - B.Tech/BE or M.Tech/ME/MS in Metrology & Metallurgy or a related field. - 10 to 15 years of experience in Metrology & Metallurgy. *Note: No additional details about the company were provided in the job description.*,

Role Overview: You will be part of the Common Hardware Group specializing in FPGA development, involving sophisticated data-path and challenging control-path FPGAs. Your responsibilities will include crafting the FPGA functional specification document, RTL coding, image generation, and validation. Collaboration with remote teams in the US and Italy is essential. The ultimate goal is to deliver bug-free RTL for first-pass success on the board. Key Responsibilities: - Design and implement FPGAs - Participate in architecture definition, implementation, and verification phases - Develop detailed design specifications and test plans - Implement block-level RTL, perform synthesis, and achieve timing closure - Work with multi-functional teams including hardware, software, diagnostics, and signal integrity groups - Assist in complex subsystem level lab bring-up, integration, and unit test validation - Contribute to the design process adoption within the team - Promote continuous improvement in design methodologies and processes - Lead and mentor junior design engineers, offer technical guidance, and drive successful project execution - Facilitate/encourage knowledge sharing in the team Qualification Required: - Educational Background: 12+ years of experience in FPGA designs with MTech/BTech in EE/EC domain - Experience with Xilinx, Altera, and Microsemi FPGAs or proficiency in HDL languages (Verilog, VHDL, System Verilog) - Hands-on experience with FPGA vendor tools like Vivado, Quartus, and Libero - Hands-on experience with Ethernet-based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART, etc. Familiarity with simulation flow like UVM and VMM is advantageous - Basic knowledge of Unix system and script tool - Knowledge of signal integrity and system bring-up preferred - Good English written and verbal communications - Self-motivation, partnership, and strong interpersonal skills are required Additional Details: At Cisco, innovation has been a core value for 40 years, revolutionizing how data and infrastructure connect and protect organizations in the AI era and beyond. Cisco solutions provide unparalleled security, visibility, and insights across the digital footprint. The collaborative environment encourages growth, innovation, and building meaningful solutions globally. Cisco's impact is felt everywhere, driven by a worldwide network of experts working together to create significant advancements.,

As an experienced candidate with 4 - 18 years of work expertise, you should have a strong background in digital verification, functional verification, and SOC / IP verification. Your expertise should also include working on system Verilog assertions & test benches, as well as OVM / UVM / VMM based verification flow. Additionally, you should be well-versed in working on ARM processors and AMBA bus protocols such as AXI, AHB, and APB. Furthermore, your role will require expertise in PCIe Protocol Verification and simulation tools like VCS, ModelSim, and Questa. You will be responsible for driving Verification Strategy, writing Test Plans, developing Test Benches, and Test Cases. It is essential that you have experience in analyzing Code Coverage, Functional Coverage, and Assertions, as well as verification of complex SoCs. Your responsibilities will also involve Test Plan creation and utilizing Verification technologies like Code Coverage, Functional coverage, and assertion-based verification to ensure the successful verification of various projects.,

Role Overview: You will be part of the Common Hardware Group, specializing in FPGA development, focusing on both sophisticated data-path and challenging control-path FPGAs. Your responsibilities will include crafting FPGA functional specifications, RTL coding, image generation, and validation. You will use industry-standard tools for FPGA design, incorporating quality metrics to ensure a robust process. Your main goal will be to deliver bug-free RTL for first-pass success on the board. Additionally, you will collaborate closely with remote teams based in the US and Italy. Key Responsibilities: - Create and review test & coverage plans. - Design and implement DV Architecture. - Develop constrained random test cases. - Specify and analyze coverage. - Design and implement reference models. - Automate the regression test suite. - Collaborate with architects, designers, and software engineers in a remote team setup. - Contribute to adopting new methodologies in the team. - Provide lab debug simulation support. Qualification Required: - Proficiency in Verilog & System Verilog. - Strong verification skills including planning, problem-solving, debugging, adversarial testing, and constraint random testing. - Hands-on experience with UVM & VMM methodologies. - Ability to architect the test-plan & test bench. - Knowledge of OTN, Ethernet-based protocols, PCIe, AXI, I2C, SPI, MDIO, and memory controllers is advantageous. - Familiarity with VCS simulation flow, Verdi, coverage, and assertions is desirable. Relevant Experience: - 4 to 7 years of hands-on experience in functional verification. Additional Details: Cisco is revolutionizing how data and infrastructure connect and protect organizations in the AI era and beyond. With 40 years of fearless innovation, Cisco creates solutions that empower the collaboration between humans and technology in the physical and digital worlds. These solutions offer customers unparalleled security, visibility, and insights across the digital footprint. Cisco's depth of technology fuels experimentation and the creation of meaningful solutions. The global network of experts provides limitless opportunities to grow and build impactful solutions collaboratively. Working at Cisco means collaborating with empathy to make significant global achievements. Cisco's solutions have a global impact, and your journey with Cisco starts here.,

As a Manager, DFT, you will be responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug, and diagnostics needs of the memories in design. You will work closely with the design, design-verification, and backend teams to enable the integration and validation of the test logic in all phases of the design and backend implementation flow. The job requires you to have good scripting skills and the ability to design and debug with minimal oversight. Additionally, you will be involved in high-quality pattern release to the test team and support silicon bring-up and yield improvement. Key Responsibilities: - Implement hardware Memory BIST (MBIST) features to support ATE, in-system test, debug, and diagnostics needs - Collaborate with design, design-verification, and backend teams for integration and validation of test logic - Design and debug with minimal oversight - Release high-quality patterns to the test team - Support silicon bring-up and yield improvement Qualifications Required: - ASIC Design DFT engineer with 10+ years of related work experience - Knowledge of the latest trends in Memory testing and silicon engineering - Hands-on experience in JTAG & IJTAG protocols, MBIST, and scan architectures - Verification skills in System Verilog, LEC, and validating test timing of the design - Experience in gate-level simulations and debug with VCS and other simulators - Understanding of the testbench in System Verilog, UVM/VMM is an addon - Post-silicon validation and debug experience, ability to work with ATE patterns - Strong verbal communication skills and ability to thrive in a dynamic environment - Scripting skills in Python/Perl (Note: Additional details about the company were not provided in the job description.),

You will join a team of extremely talented engineers who design and develop world-class routing and optical products using industry leading edge tools. - Design and implementation of complex FPGAs. - Participate in the architecture definition, implementation and verification phases. - Detailed design specification and test plan development. - Develop and implement block level RTL, perform synthesis and achieve timing closure. - Work with cross-functional teams (hardware, software, diagnostics and signal integrity groups). - Assist in complex subsystem level lab bring-up, integration, and unit test validation. - Contribution to the design process adoption within the team. - Work on improving design, development and verification methodologies. Networking and system design background Experienced in designing with Xilinx, Microsemi and Altera FPGAs Proficiency in HDL languages (Verilog, VHDL and System Verilog) Hands on experience with Ethernet based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART etc. Familiarity with simulation flow like UVM and VMM will be an added advantage Knowledge in the signal integrity and system bring-up is a plus Basic knowledge on Unix system and script tool is a big plus Work independently, provide mentorship and have strong leadership skills Self-motivation, teamwork and strong communication skills are essential Typically requires 12+ years of experience in FPGA designs with MTech/BTech in EE/EC domain.,

As a Metrology Engineer for our client, a Leading Global Specialist in Energy Management and Automation, you will be responsible for the following: - Inspecting components and subassemblies according to design records and drawings. - Performing measurements following GD&T ISO8015 and ASTM Y14.5 standards. - Conducting geometrical measurements using CMM (Mitutoyo, Zeiss), VMM (Mitutoyo), and conventional measuring instruments. - Selecting the appropriate measurement instrument based on dimensional specifications. - Acknowledging measurement requests and prioritizing workload based on priority. - Performing statistical process capability studies and interpreting the results. - Conducting basic troubleshooting in case of measurement errors, identifying the root cause, and proposing action plans. - Meeting measurement turnaround time requirements and delivering error-free reports. - Ensuring measurement accuracy and precision while preparing inspection reports. Skills Required: - Proficiency in CMM programming - Knowledge of SPC (Statistical Process Control) and MSA (Measurement System Analysis) - Familiarity with GD&T standards such as ISO8015, ISO1101, and ISO2768 - Experience with I2P / 8D Problem Solving methodologies - Proficient in Microsoft Excel, PowerPoint, and Word - 2 to 5 years of experience in a metrology lab - Experience in measuring plastic, stamping, and machined components - Knowledge of supply chain, logistics, and purchasing is an added advantage This project is for a duration of 4 months (extendable) and requires your full-time commitment on-site in Bengaluru.,