Aditya Ranjan Jha

Personal Homepage

About Me

I am a third-year PhD student at the School of Computing, National University of Singapore, advised by Professor Prateek Saxena and Professor Umang Mathur.

Recently, I have developed an interest in programming language design and formal verification.

I am a member of the KISP Lab and the FOCS Lab.

Currently, I am working on tools and techniques for safer yet expressive hardware design. This work started with Anvil, a new hardware description language that guarantees timing safety at compile time.

You can learn other things about me here.

Contact Me

Feel free to reach out through any of the platforms below:

LinkedIn GitHub Email

Or in person at:

B51, Security Lab, COM3
School of Computing,
National University of Singapore
11 Research Link, Singapore 119391

Professional Updates

DateDescriptionResources
Nov 14, 2026 Checkout Pact, a type system for communication-safe hardware design in Anvil!
Read more

Pact extends Anvil with types that describe a component's communication behaviour, control flow, and latency. Each component is checked locally, and compatible types guarantee the composed design is communication-safe, even before the full design exists. Types are inferred automatically. POPL 2027.

Communication safety

Communication safety ensures two properties: (1) synchronization safety, components exchange values synchronously; and (2) liveness, components keep communicating and making progress without deadlocking each other.

Cite

Aditya Ranjan Jha*, Jason Zhijingcheng Yu*, Umang Mathur, and Prateek Saxena. A Type System for Communication-Safe Hardware Design. POPL 2027 (to appear).

@article{jha2027pact,
  title         = {A Type System for Communication-Safe Hardware Design},
  author        = {Jha, Aditya Ranjan and Yu, Jason Zhijingcheng and
                   Mathur, Umang and Saxena, Prateek},
  journal       = {Proceedings of the ACM on Programming Languages},
  number        = {POPL},
  year          = {2027},
  note          = {To appear},
  eprint        = {2610.26599},
  archivePrefix = {arXiv}
}
Jun 23, 2026 Checkout the RTL implementation of Caplifive by our group!
Dec 23, 2025 I completed my PhD Qualifying Exam! —
Dec 7, 2025 Checkout Anvil, a new HDL that guarantees timing safety at compile time!
Read more

Anvil is a general-purpose HDL where components exchange values through messages, each with an explicit lifetime. Its type system enforces timing safety at compile time, while keeping full RTL control over registers and clock-cycle latency. ASPLOS 2026.

Timing safety

In hardware designs, each wire derived from a register (akin to a reference in software) has a lifetime during which its value must stay stable. Anvil's type system checks that (1) a wire's value is used only within its lifetime, and (2) a register is not modified while a wire borrows it. This property is analogous to temporal memory safety.

Cite

Jason Zhijingcheng Yu*, Aditya Ranjan Jha*, Umang Mathur, Trevor E. Carlson, and Prateek Saxena. Anvil: A General-Purpose Timing-Safe Hardware Description Language. ASPLOS 2026.

@inproceedings{yu2026anvil,
  title     = {Anvil: A General-Purpose Timing-Safe Hardware
               Description Language},
  author    = {Yu, Jason Zhijingcheng and Jha, Aditya Ranjan and
               Mathur, Umang and Carlson, Trevor E. and Saxena, Prateek},
  booktitle = {Proceedings of the 31st ACM International Conference on
               Architectural Support for Programming Languages and
               Operating Systems, Volume 2},
  series    = {ASPLOS '26},
  pages     = {110--136},
  year      = {2026},
  publisher = {Association for Computing Machinery},
  doi       = {10.1145/3779212.3790125}
}
Dec 30, 2024 Attended the convocation for my undergraduate! —
Aug 5, 2024 Started PhD at SoC NUS —

Curriculum Vitae

For a detailed CV, including past experience, ongoing projects, and manuscripts under review, please reach out to me. Here is a brief rundown of my recent academic activities.

Education

PhD in Computer Science 2024 – Present
School of Computing, National University of Singapore
Advisors: Prof. Prateek Saxena, Prof. Umang Mathur
B.Tech. in Electrical Engineering 2020 – 2024
Indian Institute of Technology, Kharagpur
Micro Specialization in Embedded Control Modelling Software and Design

Publications

* indicates equal contribution

  1. Aditya Ranjan Jha*, Jason Zhijingcheng Yu*, Umang Mathur, and Prateek Saxena. “A Type System for Communication-Safe Hardware Design.” To appear at Symposium on Principles of Programming Languages (POPL 2027). [pdf] [code]
    • Short paper titled “Language-based Hardware Communication Safety and Liveness” at the Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE 2026), co-located with ASPLOS 2026. [pdf]
  2. Jason Zhijingcheng Yu*, Aditya Ranjan Jha*, Umang Mathur, Trevor E. Carlson, and Prateek Saxena. “Anvil: A General Purpose Timing-Safe Hardware Description Language.” In Proceedings of the 31st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2026). [doi] [code] [website] [docs]

Service

  • Artifact Evaluation Committee POPL 2027, PLDI 2026, CAV 2026, ASPLOS 2026 (Reserved)
  • Sub/External Reviewer SETTA 2026
  • Teaching Assistant CS3235 Computer Security (AY 2024–25, AY 2025–26)

Skills and Interests

  • Research PL/Formal Methods, Computer Architecture, Security, Operating Systems
  • Languages C, C++, Python, OCaml, Rust, SystemVerilog
  • Tools Anything with documentation :P

More About Me

Apart from my professional life, here is a non-exhaustive list of things I enjoy currently:

  1. I enjoy learning new concepts, partly because I like understanding how things work, and partly because I like being the most knowledgeable person in the room.

  2. I enjoy most sports and games. Note that I enjoy them; I never said I was good at them.

  3. Since most sports require the presence of other people, and I don’t want to feel too guilty about eating too much, I work out sometimes.

  4. I enjoy comedy in all its forms.

  5. I enjoy food. Usually, I find something I like and eat it until I am bored of it.