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7th Asian Test Symposium 1998: Singapore
- 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore. IEEE Computer Society 1998, ISBN 0-8186-8277-9
Keynote Address
- Thomas W. Williams:
The New Frontier for Testing: Nano Meter Technologies. 2-
BIST I
- Jacob Savir:
BIST Diagnostics, Part 1: Simulation Models. 8-14 - Frank Mayer, Albrecht P. Stroele:
Configuring Arithmetic Pattern Generators and Response Compactors from the RT-Modules of a Circuit. 15-20 - Bechir Ayari, Prab Varma:
Test Cycle Count Reduction in a Parallel Scan BIST Environment. 21-26 - Vladimir Castro Alves, Felipe M. G. França
, Edson do Prado Granja:
A BIST Scheme for Asynchronous Logic. 27-32 - Paulo Sérgio Cardoso, Marius Strum, José Roberto de A. Amazonas, Jiang Chau Wang:
A Methodology for Minimum Area Cellular Automata Generation. 33-
High-Level Synthesis
- Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara:
A High-Level Synthesis Method for Weakly Testable Data Paths. 40-45 - Marie-Lise Flottes, R. Pires, Bruno Rouzeyre:
Alleviating DFT Cost Using Testability Driven HLS. 46-51 - Fabian Vargas, Eduardo A. Bezerra, L. Wulff, Daniel Barros Jr.:
Optimizing HW/SW Codesign towards Reliability for Critical-Application Systems. 52-57 - Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita:
An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification. 58-63 - Junichi Hirase:
Economical Importance of the Maximum Chip Area. 64-
Delay Testing
- Cheng-Wen Wu, Chih-Yuang Su:
A Probabilistic Model for Path Delay Faults. 70-75 - Zhongcheng Li, Yinghua Min, Robert K. Brayton:
A New Low-Cost Method for Identifying Untestable Path Delay Faults. 76-81 - Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell:
False-Path Removal Using Delay Fault Simulation. 82-87 - Yuan-Chieh Hsu, Sandeep K. Gupta:
An Automatic Test Pattern Generator for At-Speed Robust Path Delay Testing. 88-95 - Huawei Li, Zhongcheng Li, Yinghua Min:
Delay Testing with Double Observations. 96-
Fault Modeling & Simulation
- Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi:
On a Logical Fault Model H1SGLF for Enhancing Defect Coverage. 102-107 - Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu:
Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation. 108-112 - Kuen-Jong Lee, Jing-Jou Tang, Wern-Yih Duh:
On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation. 113-118 - S. M. Aziz, Joarder Kamruzzaman:
Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits. 119-
Software Testing
- Haiying Tu, Fangmei Wu, Xiaoxu Ren:
Rough-Hierarchical Testing for Safety Critical Software. 126-130 - Eric Mouchel La Fosse:
A Structured Testing Approach for DSP Software. 131-
Current Testing
- Mukund R. Patel, Julian Fierro, Steve Pico:
IDDQ Test Methodology and Tradeoffs for Scan/Non-Scan Designs. 138-143 - Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita:
Design for Diagnosability of CMOS Circuits. 144-149 - Sandip Kundu:
IDDQ Defect Detection in Deep Submicron CMOS ICs. 150-152 - Mark G. Faust:
ATE Features for IDDQ Testing. 153-
Test Engineering
- Peng-Cheng Koo, San-Liek Pang:
A New Technique to Ensure Quality of Test Patterns. 160-164 - S. R. Sabapathi:
Testing CPU Based Boards for Functionality Using Bus Cycle Signature System. 165-171 - Vikram Devdas, André Ivanov:
Non-Intrusive Testing of High-Speed CML Circuits. 172-178 - Terry Corpuz:
Fast Window Test Method of Hysteresis Test. 179-183 - Kin Wee Choo, Guoxiao Guo, Ben M. Chen:
Development of a Multi-Channel PC-Based Hard Disk Drive Bode-Plot Generator. 184-
Sequential Circuit Testing
- Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara:
An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits. 190-197 - Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. 198-203 - Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara:
A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency. 204-211 - J. Th. van der Linden, M. H. Konijnenburg, Ad J. van de Goor:
Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection. 212-
Defect Analysis & Fault Diagnosis
- Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa:
On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates. 222-227 - Sumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell:
Testing for Floating Gates Defects in CMOS Circuits. 228-236 - Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu:
Electron Beam Tester Aided Fault Diagnosis for Logic Circuits Based on Sensitized Paths. 237-
Boundary Scan & Interconnect Testing
- Chen-Huan Chiang, Sandeep K. Gupta:
BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. 244-252 - Wenyi Feng, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi:
Fault Detection in a Tristate System Environment. 253-258 - Chauchin Su, Yue-Tsung Chen:
Comprehensive Interconnect BIST Methodology for Virtual Socket Interface. 259- - Yasunori Sameshima, Tomoo Fukazawa:
A DFT Methodology for High-Speed MCM Based on Boundary-Scan Techniques. 521-
FPGA Testing
- Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. 266-271 - Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita:
Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA. 272-277 - Yinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi:
A Diagnosis Method for Interconnects in SRAM Based FPGAs. 278-282 - Sying-Jyan Wang, Chao-Neng Huang:
Testing and Diagnosis of Interconnect Structures in FPGAs. 283-
On-Line Testing & Fault Tolerance
- Jaime Velasco-Medina
An Approach to the On-Line Testing of Operational Amplifiers. 290-295 - Vladimir V. Saposhnikov, Valerij V. Saposhnikov, Alexej Dmitriev, Michael Gössel:
Self-Dual Duplication for Error Detection. 296-300 - Yu-Chun Chuang, Cheng-Wen Wu:
On-Line Error Detection Schemes for a Systolic Finite-Field Inverter. 301-305 - Sumito Nakano, Naotake Kamiura, Yutaka Hata:
Fault Tolerance of a Tree-Connected Multiprocessor System and its Arraylike Layout. 306-
IDDQ Testing
- Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita:
Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. 312-317 - Md. Altaf-Ul-Amin, Zahari Mohamed Darus:
An Off-Chip Current Sensor for IDDQ Testing of CMOS ICs. 318-322 - Koichi Nose, Takayasu Sakurai:
Integrated Current Sensing Device for Micro IDDQ Test. 323-326 - Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita:
A High-Speed IDDQ Sensor for Low-Voltage ICs. 327-
Memory Testing
- Jörg E. Vollrath, Markus Huebl, Ernst Stahl:
Power Analysis of DRAMs. 334-339 - Said Hamdioui, Ad J. van de Goor:
Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories. 340-347 - Jian Liu, Rafic Z. Makki, Ayman I. Kayssi:
Dynamic Power Supply Current Testing of SRAMs. 348-353 - Vyacheslav N. Yarmolik, Yuri V. Klimets, Serge N. Demidenko:
March PS(23N) Test for DRAM Pattern-Sensitive Faults. 354-
Analog & Mixed Signal Test
- Sam D. Huynh, Seongwon Kim, Mani Soma, Jinyan Zhang:
Dynamic Test Set Generation for Analog Circuits and Systems. 360-365 - Mike W. T. Wong, Matthew Worsman:
DC Nonlinear Circuit Fault Simulation With Large Change Sensitivity. 366-371 - Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand:
BISTing Switched-Current Circuits. 372-377 - Yue-Tsang Chen, Chauchin Su:
Analog Module Metrology Using MNABST-1 P1149.4 Test Chip. 378-382 - Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand:
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. 383-387 - Kolin Paul, A. Roy, Prasanta Kumar Nandi, B. N. Roy, M. Deb Purkayastha, Santanu Chattopadhyay, Parimal Pal Chaudhuri:
Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis. 388-
Design Verification
- Chryssa Dislis, Gerry Musgrave, Roger B. Hughes:
Formal Design Techniques - Theory and Engineering Reality. 394-398 - J. Gong, Eddie M. C. Wong:
Verification of Asynchronous Circuits with Bounded Inertial Gate Delays. 399-401 - Shing-Wu Tung, Jing-Yang Jou:
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. 402-407 - Shin'ichi Nagano, Hiroyuki Fujita, Yoshiaki Kakuda, Tohru Kikuno:
Application of Real-Time Temporal Logic to Design Fault Detection in Responsive Communication Protocols. 408-412 - Zhen Guo, He Li, Shuling Guo, Dongsheng Wang:
Design and Simulation of a RISC-Based 32-bit Embedded On-Board Computer. 413-
BIST II
- Christophe Fagot, Olivier Gascuel, Patrick Girard
A Ring Architecture Strategy for BIST Test Pattern Generation. 418-423 - Xiaowei Li, Paul Y. S. Cheung:
Exploiting BIST Approach for Two-Pattern Testing. 424-429 - C. P. Ravikumar, N. Satya Prasad:
Evaluating BIST Architectures for Low Power. 430-434 - Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel:
A BIST Structure to Test Delay Faults in a Scan Environment. 435-439 - Ismet Bayraktaroglu, K. Udawatta, Alex Orailoglu:
An Examination of PRPG Selection Approaches for Large, Industrial Designs. 440-
Sequential Circuit Testing
- Irith Pomeranz, Sudhakar M. Reddy:
Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements. 446-451 - Michael S. Hsiao, Srimat T. Chakradhar:
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits. 452-457 - Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy:
Vector Restoration Using Accelerated Validation and Refinement. 458-466 - Ruifeng Guo
On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits . 467-471 - Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth:
Synthesis of Sequential Circuits with Clock Control to Improve Testability. 472-
Test Program Generation
- Silvia Chiusano, Fulvio Corno, Paolo Prinetto:
A Test Pattern Generation Algorithm Exploiting Behavioral Information. 480-485 - Irith Pomeranz, W. Kent Fuchs:
A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination. 486-491 - Madhavi Karkala, Nur A. Touba, Hans-Joachim Wunderlich:
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. 492-499 - Pingying Zeng, Zhigang Mao, Yizheng Ye, Yuliang Deng:
Test Pattern Generation for Column Compression Multiplier. 500-503 - Shiyi Xu, Jianhua Gao:
An Efficient Random-like Testing. 504-
Microsystem Testing: Challenge or Common Knowledge?
- Hans G. Kerkhoff:
Microsystem Testing: Challenge or Common Knowledge? 510-511 - Michel Renovell:
Microsystems Testing: A Challenge. 512 - Marcelo Lubaszewski:
Bridging the Gap between Microelectronics and Micromechanics Testing. 513
Testing Embedded Memories: Is BIST the Ultimate Solution?
- Cheng-Wen Wu
Testing Embedded Memories: Is BIST the Ultimate Solution? 516-517 - Marcel Jacomet:
An ASIC Designer's Point of View. 518- - Rafic Z. Makki:
Testing of Embedded Memories - The Aggregate. 519 - Ad J. van de Goor:
Answers to the Key Issues. 520
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