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ARC 2007: Mangaratiba, Brazil
- Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, João M. P. Cardoso
:
Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007. Lecture Notes in Computer Science 4419, Springer 2007, ISBN 978-3-540-71430-9
Architectures [Regular Papers]
- Frank Bouwens, Mladen Berekovic
Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array. 1-13 - Mazen A. R. Saghir, Rawan Naous:
A Configurable Multi-ported Register File Architecture for Soft Processor Cores. 14-25 - Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Berekovic:
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture. 26-38 - Je-Hoon Lee, Seung-Sook Lee, Kyoung-Rok Cho:
Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture. 39-48 - Jae Young Hur, Stephan Wong, Stamatis Vassiliadis:
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs. 49-60 - Jae Young Hur, Todor P. Stefanov
Systematic Customization of On-Chip Crossbar Interconnects. 61-72 - Saar Drimer:
Authentication of FPGA Bitstreams: Why and How. 73-84
Architectures [Short Papers]
- Jae-Jin Lee, Dong-Guk Hwang, Gi-Yong Song:
Design of a Reversible PLD Architecture. 85-90 - Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis:
Designing Heterogeneous FPGAs with Multiple SBs. 91-96
Mapping Techniques and Tools [Regular Papers]
- Joonseok Park, Pedro C. Diniz:
Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations. 97-109 - Yazhuo Dong, Yong Dou, Jie Zhou:
Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware. 110-121 - Rainer Scholz:
Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations. 122-129 - Carlo Galuzzi, Koen Bertels, Stamatis Vassiliadis:
A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions. 130-141 - Kazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi:
Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping. 142-154 - Yong Dou, Jinhui Xu, Guiming Wu:
The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining. 155-166 - César Torres-Huitzil, Bernard Girau, Adrien Gauffriau:
Hardware/Software Codesign for Embedded Implementation of Neural Networks. 167-178 - João Bispo
Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues. 179-190
Mapping Techniques and Tools [Short Papers]
- Nicolas Hervé, Daniel Ménard, Olivier Sentieys:
About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations. 191-200
Arithmetic [Regular Papers]
- Ruzica Jevtic
Switching Activity Models for Power Estimation in FPGA Multipliers. 201-213 - Jean-Luc Beuchat
Multiplication over Fpm on FPGA: A Survey. 214-225 - Francisco Rodríguez-Henríquez, Guillermo Morales-Luna, Nazar Abbas Saqib, Nareli Cruz Cortés:
A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm. 226-237 - Edgar Ferrer, Dorothy Bollman, Oscar Moreno:
A Fast Finite Field Multiplier. 238-246
Applications [Regular Papers]
- Rayan Chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton:
Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval. 247-258 - Javier Díaz, Eduardo Ros, Sonia Mota, Richard R. Carrillo:
Image Processing Architecture for Local Features Computation. 259-270 - Günter Knittel:
A Compact Shader for FPGA-Based Volume Rendering Accelerators. 271-282 - Yong-Min Lee
Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications. 283-292 - Xiaodong Yang, Shengmei Mou, Yong Dou:
FPGA-Accelerated Molecular Dynamics Simulations: An Overview. 293-301 - David B. Thomas, Wayne Luk, Michael Stumpf:
Reconfigurable Hardware Acceleration of Canonical Graph Labelling. 302-313 - Nilton B. Armstrong, Heitor S. Lopes
Reconfigurable Computing for Accelerating Protein Folding Simulations. 314-325 - Edson Pedro Ferlin, Heitor S. Lopes
Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits. 326-336
Applications [Short Papers]
- Sonia Mota, Eduardo Ros, Javier Díaz, Rafael Rodríguez-Gómez, Richard R. Carrillo:
A Space Variant Mapping Architecture for Reliable Car Segmentation. 337-342 - Shinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads. 343-349 - Séamas McGettrick, Dermot Geraghty, Ciarán McElroy:
Searching the Web with an FPGA Based Search Engine. 350-357 - Yoshiki Yamaguchi, Kenji Kanazawa, Yoshiharu Ohke, Tsutomu Maruyama:
An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma. 358-364 - Matteo Tomasi, Javier Díaz, Eduardo Ros:
Real Time Architectures for Moving-Objects Tracking. 365-372 - Patrick Rocke, Brian McGinley, Fearghal Morgan, John Maher:
Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller. 373-378 - Carlos Raimundo Erig Lima, Heitor S. Lopes
Multiple Sequence Alignment Using Reconfigurable Computing. 379-384 - Wagner Rodrigo Weinert, César Manuel Vargas Benítez
Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing. 385-390
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