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ASP-DAC 2005: Shanghai, China
- Tingao Tang:
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005. ACM Press 2005, ISBN 0-7803-8737-6
Keynote address
- Rajeev Madhavan:
Silicon compilation: the answer to reducing IC development costs. - Jan M. Rabaey:
Design at the end of the silicon roadmap. - Zhenghua Jiang:
The development of integrated circuit industry in China.
Tree construction and buffering
- Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan:
The polygonal contraction heuristic for rectilinear Steiner tree construction. 1-6 - Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan:
An-OARSMan: obstacle-avoiding routing tree construction with good length performance. 7-12 - Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Making fast buffer insertion even faster via approximation techniques. 13-18 - Zhong-Ching Lu, Ting-Chi Wang:
Concurrent flip-flop and buffer insertion with adaptive blockage avoidance. 19-22 - Tianpei Zhang, Sachin S. Sapatnekar:
Buffering global interconnects in structured ASIC design. 23-26
System level design methodology for network-on-chip
- Srinivasan Murali, Luca Benini, Giovanni De Micheli:
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. 27-32 - César A. M. Marcon
, André Borin Suarez, Altamiro Amadeu Susin, Luigi Carro, Flávio Rech Wagner:
Time and energy efficient mapping of embedded applications onto NoCs. 33-38 - Liang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou:
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip. 39-44 - Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski:
System-level communication modeling for network-on-chip synthesis. 45-48 - Luciano Ost, Aline Mello, José Palma, Fernando Gehm Moraes
MAIA: a framework for networks on chip generation and verification. 49-52
Test and DFT (1)
- Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li:
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. 53-58 - Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. 59-64 - Jin-Fu Li:
Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs. 65-70 - Feng Shi, Yiorgos Makris:
SPIN-PAC: test compaction for speed-independent circuits. 71-74 - Michihiro Shintani
A Huffman-based coding with efficient test application. 75-78
DFM
- Vijay Pitchumani:
Embedded tutorial I: design for manufacturability. - Rouying Zhan, Haolu Xie, Haigang Feng, Albert Z. Wang:
ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress. 79-82 - Xiaolang Yan, Ye Chen, Zheng Shi, Yue Ma:
A new method for model based frugal OPC. 83-86
Clock, power grid and thermal analysis and optimization
- Yong Zhan, Sachin S. Sapatnekar:
Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up. 87-92 - Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan:
Analysis of buffered hybrid structured clock networks. 93-98 - Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu:
Clock network minimization methodology based on incremental placement. 99-102 - Hongyu Chen, Chung-Kuan Cheng:
A multi-level transmission line network approach for multi-giga hertz clock distribution. 103-106 - Zhixin Tian, Huazhong Yang, Rong Luo:
Gibbs sampling in power grid analysis. 107-110 - Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan:
A wideband hierarchical circuit reduction for massively coupled interconnects. 111-114
Routing and interconnects
- Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. 115-120 - Jason Cong, Yan Zhang:
Thermal-driven multilevel routing for 3-D ICs. 121-126 - Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen:
Wave-pipelined on-chip global interconnect. 127-132 - Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu
Evaluation of on-chip transmission line interconnect using wire length distribution. 133-138
System level modeling and embedded software
- Samar Abdi, Daniel Gajski:
A formalism for functionality preserving system level transformations. 139-144 - KiSeun Kwon, Youngmin Yi, Dohyung Kim, Soonhoi Ha:
Embedded software generation from system level specification for multi-tasking embedded systems. 145-150 - Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya:
Scheduler implementation in MP SoC design. 151-156 - G. Chen, Mahmut T. Kandemir:
Optimizing embedded applications using programmer-inserted hints. 157-160 - Dohyung Kim, Soonhoi Ha:
Static analysis and automatic code synthesis of flexible FSM model. 161-165
Test and DFT (2)
- Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Cheng
Constraint extraction for pseudo-functional scan-based delay testing. 166-171 - Hafizur Rahaman, Debesh K. Das:
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. 172-177 - Xijiang Lin, Janusz Rajski:
Propagation delay fault: a new fault model to test delay faults. 178-183 - Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Oscillation ring based interconnect test scheme for SOC. 184-187 - Junhao Shi, Görschwin Fey, Rolf Drechsler:
Bridging fault testability of BDD circuits. 188-191
TCAD
- Debjit Sinha, Hai Zhou:
Yield driven gate sizing for coupling-noise reduction under uncertainty. 192-197 - Yun-Ru Wu, Ming-Chao Tsai, Ting-Chi Wang:
Maze routing with OPC consideration. 198-203 - Masahiro Murakawa, Mitiko Miura-Mattausch, Tetsuya Higuchi:
Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithm. 204-207 - Xiren Wang, Wenjian Yu, Zeyi Wang:
Substrate resistance extraction with direct boundary element method. 208-211 - Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang:
An efficient combinationality check technique for the synthesis of cyclic combinational circuits. 212-215 - Ke Cao, Puneet Dhawan, Jiang Hu:
Library cell layout with Alt-PSM compliance and composability. 216-219 - Rasit Onur Topaloglu
Forward discrete probability propagation method for device performance characterization under process variations. 220-223
Simulation and modeling techniques for RF/analog circuits
- Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He:
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction. 224-229 - Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri
Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. 230-235 - Xiaochun Duan, Kartikeya Mayaram:
A new approach for ring oscillator simulation using the harmonic balance method. 236-239 - Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh:
Efficient transient simulation for transistor-level analysis. 240-243 - Bang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles C. Chiang, Dian Zhou:
Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits. 244-249 - Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen:
Block based statistical timing analysis with extended canonical timing model. 250-253
Logic synthesis
- Lin Yuan, Gang Qu, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli:
FSM re-engineering and its application in low power state encoding. 254-259 - Aiqun Cao, Ruibing Lu, Cheng-Kok Koh:
Post-layout logic duplication for synthesis of domino circuits with complex gates. 260-265 - Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch:
Detecting support-reducing bound sets using two-cofactor symmetries. 266-271 - Vivek V. Shende
Synthesis of quantum logic circuits. 272-275 - Stephen Plaza, Valeria Bertacco:
STACCATO: disjoint support decompositions from BDDs through symbolic kernels. 276-279
System level architecture design
- Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel:
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. 280-285 - Naoki Tomono, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A processor core synthesis system in IP-based SoC design. 286-291 - Koushik Niyogi, Diana Marculescu
Speed and voltage selection for GALS systems based on voltage/frequency islands. 292-297 - Christian Haubelt, Stephan Otto, Cornelia Grabbe, Jürgen Teich:
A system-level approach to hardware reconfigurable systems. 298-301 - Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao
High-level synthesis for DSP applications using heterogeneous functional units. 302-304
Test and verification
- Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara:
Evaluation of the statistical delay quality model. 305-310 - Wenjing Rao, Alex Orailoglu, Ramesh Karri
Fault tolerant nanoelectronic processor architectures. 311-316 - Shireesh Verma, Kiran Ramineni, Ian G. Harris:
An efficient control-oriented coverage metric. 317-322 - Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. 323-326 - Jin Yang, Avi Puder:
Tightly integrate dynamic verification with formal verification: a GSTE based approach. 327-330
Special Session
- Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen:
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
Placement techniques
- Satoshi Ono, Patrick H. Madden:
On structure and suboptimality in placement. 331-336 - Pradeep Ramachandaran, Ameya R. Agnihotri, Satoshi Ono, Purushothaman Damodaran, Krishnaswami Srihari, Patrick H. Madden:
Optimal placement by branch-and-price. 337-342 - Puneet Gupta
Detailed placement for improved depth of focus and CD control. 343-348 - Chen Li, Cheng-Kok Koh, Patrick H. Madden:
Floorplan management: incremental placement for gate sizing and buffer insertion. 349-354
Security processor design
- Yi-Ping You
Low-power techniques for network security processors. 355-360 - Chih-Pin Su, Chia-Lung Horng, Chih-Tsun Huang, Cheng-Wen Wu
A configurable AES processor for enhanced security. 361-366 - Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang:
Power estimation starategies for a low-power security processor. 367-371 - Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu
Design and test of a scalable security processor. 372-375 - Yung-Chia Lin, Chung-Wen Huang, Jenq Kuen Lee:
System-level design space exploration for security processor prototyping in analytical approaches. 376-380
(Special session) embedded tutorial II
- David T. Blaauw, Anirudh Devgan, Farid N. Najm:
Leakage power: trends, analysis and avoidance.
(Special session) CAD for microarchitecture designs
- Bill Grundmann:
Challenges to covering the high-level to silicon gap. 1 - Todd M. Austin, Valeria Bertacco, David T. Blaauw, Trevor N. Mudge:
Opportunities and challenges for better than worst-case design. 2-7 - Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong:
Microarchitecture evaluation with floorplanning and interconnect pipelining. 8-15
University design contest
- Hongxia Wang, Samuel Rodríguez, Cagdas Dirik, Amol Gole, Vincent Chan, Bruce L. Jacob:
TERPS: the embedded reliable processing system. 1-2 - Dimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, Kostas Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis:
AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. 3-4 - Hongyan Jian, Zhangwen Tang, Jie He, Jinglan He, Min Hao:
Standard CMOS technology on-chip inductors with pn junctions substrate isolation. 5-6 - Hao-Yun Chin, Chao-Chung Cheng, Yu-Kun Lin, Tian-Sheuan Chang:
A bandwidth efficient subsampling-based block matching architecture for motion estimation. 7-8 - Akinori Shinmyo, Masanori Hashimoto, Hidetoshi Onodera:
Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. 9-10 - Chi Huang, Xinyu Wu, Jinmei Lai, Chengshou Sun, Gang Li:
A design of high speed double precision floating point adder using macro modules. 11-12 - Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch:
A low-power video segmentation LSI with boundary-active-only architecture. 13-14 - Ningyi Xu, Shaohua Li, Wei Yu, Guanghui He, Hao Zhang, Fei Luo, Zucheng Zhou:
The design and implementation of a DVB receiving chip with PCI interface. 15-16 - Dehui Zhang, Quan Liang Zhao, Jun Gang Han:
Design and implementation of an SDH high-speed switch. 17-18 - Arias Tanti Hapsari, Eniman Y. Syamsudin, Imron Pramana:
Design of vehicle position tracking system using short message services and its implementation on FPGA. 19-20 - Fei Wang, Jianyu Zhang, Xuan Wang, Jinmei Lai, Chengshou Sun:
Design of A 2.4-GHz integrated frequency synthesizer. 21-22 - Jianhua Feng, Jieyi Long, Wenhua Xu, Hongfei Ye:
An improved test access mechanism structure and optimization technique in system-on-chip. 23-24
(Special session) embedded tutorial III
- Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Designing reliable circuit in the presence of soft errors. 1
Design optimization for high-performance digital circuits
- Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen:
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation. 381-386 - Zhaojun Wo, Israel Koren:
Effective analytical delay model for transistor sizing. 387-392 - Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Anirudh Devgan:
Achieving continuous VT performance in a dual VT process. 393-398 - Dongwoo Lee, David T. Blaauw, Dennis Sylvester:
Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. 399-404
Floorplanning and partitioning
- Lei Cheng, Liang Deng, Martin D. F. Wong
Floorplanning for 3-D VLSI design. 405-411 - Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong
Optimal redistribution of white space for wire length minimization. 412-417 - Yongseok Cheon, Martin D. F. Wong
Crowdedness-balanced multilevel partitioning for uniform resource utilization. 418-423 - Ramprasad Ravichandran, Michael T. Niemier, Sung Kyu Lim:
Partitioning and placement for buildable QCA circuits. 424-427 - Chanseok Hwang, Massoud Pedram:
PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits. 428-431
Advances in SAT technology and application
- Jinbo Huang:
MUP: a minimal unsatisfiability prover. 432-437 - Domagoj Babic, Alan J. Hu:
Integration of supercubing and learning in a SAT solver. 438-444 - Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Dynamic symmetry-breaking for improved Boolean optimization. 445-450 - ShengYu Shen, Ying Qin, Sikun Li:
A fast counterexample minimization approach with refutation analysis and incremental SAT. 451-454 - Wei Huang, Pushan Tang, Min Ding:
Sequential equivalence checking using cuts. 455-458
Analysis and simulation techniques
- Xiaolue Lai, Yayun Wan, Jaijeet S. Roychowdhury:
Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise. 459-464 - Fang Liu, Sule Ozev:
Hierarchical analysis of process variation for mixed-signal systems. 465-470 - Xuan Zeng, Bang Liu, Jun Tao, Charles C. Chiang, Dian Zhou:
A novel wavelet method for noise analysis of nonlinear circuits. 471-476 - Mengmeng Ding, Glenn Wolfe, Ranga Vemuri:
An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. 477-482
Interconnect modeling and analysis and system level design methodology
- Yu Du, Wayne Dai:
Partial reluctance based circuit simulation is efficient and stable. 483-488 - Krishnan Srinivasan, Karam S. Chatha:
SAGA: synthesis technique for guaranteed throughput NoC architectures. 489-494 - Sudeep Pasricha, Nikil D. Dutt
Automated throughput-driven synthesis of bus-based communication architectures. 495-498 - Jae-Gon Lee
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. 499-502 - Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Statistical modeling of cross-coupling effects in VLSI interconnects. 503-506 - Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong:
Compact and stable modeling of partial inductance and reluctance matrices. 507-510
High-level synthesis
- Rami Beidas, Jianwen Zhu:
Scalable interprocedural register allocation for high level synthesis. 511-516 - Azadeh Davoodi, Ankur Srivastava:
Simultaneous floorplanning and resource binding: a probabilistic approach. 517-522 - Anup Hosangadi, Farzan Fallah, Ryan Kastner:
Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions. 523-528 - René Krenz, Elena Dubrova:
A fast algorithm for finding common multiple-vertex dominators in circuit graphs. 529-532
Low power
- Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Low-power domino circuits using NMOS pull-up on off-critical paths. 533-538 - Shengqi Yang, Wayne H. Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie:
Low-leakage robust SRAM cell design for sub-100nm technologies. 539-544 - Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen:
Studying interactions between prefetching and cache line turnoff. 545-548 - Wei Han, Ahmet T. Erdogan
The development of high performance FFT IP cores through hybrid low power algorithmic methodology. 549-552 - Newton Cheung, Sri Parameswaran, Jörg Henkel:
Battery-aware instruction generation for embedded processors. 553-556 - Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura:
A variation-aware low-power coding methodology for tightly coupled buses. 557-560
Formal verification: theory and practice
- Dong Wang, Jeremy R. Levitt:
Automatic assume guarantee analysis for assertion-based formal verification. 561-566 - Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi:
TED+: a data structure for microprocessor verification. 567-572 - René Krenz, Elena Dubrova:
Improved Boolean function hashing based on multiple-vertex dominators. 573-578 - Rüdiger Ebendt, Rolf Drechsler:
Lower bounds for dynamic BDD reordering. 579-582 - Xiushan Feng, Alan J. Hu, Jin Yang:
Partitioned model checking from software specifications. 583-587
Special session
- Jason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan M. Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe:
Are we ready for system-level synthesis?
Robust and low-power clock design
- Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Register placement for low power clock network. 588-593 - Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu:
Skew scheduling and clock routing for improved tolerance to process variations. 594-599 - Vinil Varghese, Tom Chen, Peter Michael Young:
Stability analysis of active clock deskewing systems using a control theoretic approach. 600-605 - Wai-Ching Douglas Lam, Cheng-Kok Koh:
Process variation robust clock tree routing. 606-611
DSP
- Nacer-Eddine Zergainoh, Katalin Popovici, Ahmed Amine Jerraya, Pascal Urard:
IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems. 612-618 - Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera:
A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. 619-622 - Lingfeng Li, Satoshi Goto, Takeshi Ikenaga:
An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC. 623-626 - Yanjun Zhang, Hu He, Yihe Sun:
A new register file access architecture for software pipelining in VLIW processors. 627-630 - Minho Kim, Ingu Hwang, Soo-Ik Chae:
A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264. 631-634 - Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousias, Tughrul Arslan:
Automatic synthesis and scheduling of multirate DSP algorithms. 635-638
Low power and special purpose FPGAs
- Zhenyu Liu, Tughrul Arslan, Sami Khawam, Iain Lindsay:
A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines. 639-644 - Yan Lin, Fei Li, Lei He:
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. 645-650 - Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia
Exploiting temporal idleness to reduce leakage power in programmable architectures. 651-656 - Vijay Degalahal, Tim Tuan:
Methodology for high level estimation of FPGA power consumption. 657-660 - Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan:
Leakage control in FPGA routing fabric. 661-664
RF circuit design and design methodology
- K. Praveen Jayakar Thomas, Ram Singh Rana, Yong Lian
A 1GHz CMOS fourth-order continuous-time bandpass sigma delta modulator for RF receiver front end A/D conversion. 665-670 - Min Chu, David J. Allstot:
An elitist distributed particle swarm algorithm for RF IC optimization. 671-674 - Min Chu, David J. Allstot:
Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimization. 675-678 - Miao Li, Tad A. Kwasniewski, Shoujun Wang, Yuming Tao:
A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology. 679-682 - Kenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu
A dynamic reconfigurable RF circuit architecture. 683-686 - Zhangwen Tang, Jie He, Hongyan Jian, Haiqing Zhang, Jie Zhang, Hao Min:
Prediction of LC-VCOs' tuning curves with period calculation technique. 687-690
Design techniques in embedded and real-time system
- Zhihui Xiong, Jihua Chen, Sikun Li:
Hardware/software partitioning for platform-based design method. 691-696 - Ernesto Wandeler, Lothar Thiele:
Abstracting functionality for modular performance analysis of hard real-time systems. 697-702 - Dongkun Shin, Jihong Kim:
Optimizing intra-task voltage scheduling using data flow analysis. 703-708 - John Conner, Yuan Xie, Mahmut T. Kandemir, Robert P. Dick, Greg M. Link:
FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection. 709-712 - G. Chen, Mahmut T. Kandemir, Mary Jane Irwin, Gokhan Memik:
Compiler-directed selective data protection against soft errors. 713-716
Crosstalk noise avoidance and power/ground network optimization
- Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet Meiling Wang Roveda:
A perturbation-aware noise convergence methodology for high frequency microprocessors. 717-722 - Takashi Sato
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. 723-728 - Raid Ayoub, Alex Orailoglu:
A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses. 729-734 - Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan:
VLSI on-chip power/ground network optimization considering decap leakage currents. 735-738 - Jinjun Xiong
Probabilistic congestion model considering shielding for crosstalk reduction. 739-742
Others in leading edge designs
- Ozcan Ozturk, Mahmut T. Kandemir, G. Chen, Mary Jane Irwin, Mustafa Karaköy:
Customized on-chip memories for embedded chip multiprocessors. 743-748 - Rutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli:
Performance driven reliable link design for networks on chips. 749-754 - Yuvraj Agarwal, Curt Schurgers, Rajesh Gupta:
Dynamic power management using on demand paging for networked embedded systems. 755-759 - Lei Yang, Manyuan Shen, Hui Liu, Chuanjin Richard Shi:
An FPGA implementation of low-density parity-check code decoder with multi-rate capability. 760-763 - Yong Xiao, Runde Zhou:
Single-track asynchronous pipeline controller design. 764-768 - Mahmut T. Kandemir, Guangyu Chen, Feihui Li, I. Demirkiran:
Using data replication to reduce communication energy on chip multiprocessors. 769-772
Synthesis for FPGAs
- Cristinel Ababei, Hushrav Mogal, Kia Bazargan:
Three-dimensional place and route for FPGAs. 773-778 - Wai-Kei Mak:
Modern FPGA constrained placement. 779-784 - Chang Woo Kang, Massoud Pedram:
Clustering techniques for coarse-grained, antifuse FPGAs. 785-790 - Vivek Garg, Vikram Chandrasekhar
A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. 791-794 - Somsubhra Mondal, Seda Ogrenci Memik:
Resource sharing in pipelined CDFG synthesis. 795-798
Analog circuit design
- Hong Zhang, Guican Chen, Ning Li:
A 2.4-GHz linear-tuning CMOS LC voltage-controlled oscillator. 799-802 - Guoqiang Hang:
Adiabatic CMOS gate and adiabatic circuit design for low-power applications. 803-808 - Osamu Matsumoto, Hisashi Harada, Yasuo Morimoto, Toshio Kumamoto, Takahiro Miki, Masao Hotta:
An 11-bit 160-MS/s 1.35-V 10-mW D/A converter using automated device sizing system. 809-814 - Hai Chen, Xiaobo Wu:
A class D audio power amplifier with high-efficiency and low-distortion. 815-818 - Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang:
Substrate noise modeling in early floorplanning of MS-SOCs. 819-823
Low power design for embedded and real-time systems
- Shu Xiao, Edmund Ming-Kit Lai:
Instruction scheduling of VLIW architectures for balanced power consumption. 824-829 - Shaoxiong Hua, Gang Qu:
Power minimization techniques on distributed real-time systems by global and local slack management. 830-835 - Jaewon Seo, Nikil D. Dutt
A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors. 836-841 - Van R. Culver, Sunil P. Khatri:
A dynamic voltage scaling algorithm for energy reduction in hard real-time systems. 842-845 - Jianli Zhuo, Chaitali Chakrabarti:
An efficient dynamic task scheduling algorithm for battery powered DVS systems. 846-849
Synthesis for low power
- Deming Chen, Jason Cong, Junjuan Xu:
Optimal module and voltage assignment for low-power. 850-855 - Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang
Bitwidth-aware scheduling and binding in high-level synthesis. 856-861 - Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu:
Functionality directed clustering for low power MTCMOS design. 862-867 - Azadeh Davoodi, Ankur Srivastava
Wake-up protocols for controlling current surges in MTCMOS-based technology. 868-871 - Hsueh-Chih Yang, Lan-Rong Dung:
On multiple-voltage high-level synthesis using algorithmic transformations. 872-876
New circuit and methodology
- Jong-Chul Lim, Hye-Seung Yu, Jae-Suk Choi, Soo-Won Kim:
An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin. 877-882 - Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham:
Constructing zero-deficiency parallel prefix adder of minimum depth. 883-888 - Zhangwen Tang, Jie He, Hongyan Jian, Hao Min:
An accurate 1.08-GHz CMOS LC voltage-controlled oscillator. 889-892 - Anru Wang, Wayne Wei-Ming Dai:
Area-IO DRAM/logic integration with system-in-a-package (SiP). 893-896 - Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li:
Design of an efficient memory subsystem for network processor. 897-900 - Zhenxin Sun, Weng-Fai Wong
Design of clocked circuits using UML. 901-904
FPGA circuits and architectures
- Vivek Garg, Vikram Chandrasekhar
A function generator-based reconfigurable system. 905-909 - Hongbing Fan, Yu-Liang Wu:
Crossbar based design schemes for switch boxes and programmable interconnection networks. 910-915 - Cheng Zhan, Tughrul Arslan, Sami Khawam, Iain Lindsay:
A domain specific reconfigurable Viterbi fabric for system-on-chip applications. 916-919 - Chu Chao, Qin Zhang, Yingke Xie, Chengde Han:
Design of a high performance FFT processor based on FPGA. 920-923 - Guangyu Chen, Feihui Li, Mahmut T. Kandemir, I. Demirkiran:
Increasing FPGA resilience against soft errors using task duplication. 924-927 - Gaurav Mittal, David Zaretsky, Gokhan Memik, Prith Banerjee:
Automatic extraction of function bodies from software binaries. 928-931
(Special session) EDA market in China
- David Chen, Nancy Wu, Wayne Dai, Jun Tan, Weiping Liu, Hao Min, Jian-yue Pan:
Panel III: EDA market in China.
Poster session I
- Xi Chen, Jianhua Lu, Zucheng Zhou, YaoHui Shang:
Modeling SystemC design in UML and automatic code generation. 932-935 - M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Enabling RTOS simulation modeling in a system level design language. 936-939 - Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems. 940-943 - Lukai Cai, Andreas Gerstlauer, Daniel Gajski:
Multi-metric and multi-entity characterization of applications for early system design exploration. 944-947 - Yongxin Zhu, Weng-Fai Wong
An integrated performance and power model for superscalar processor designs. 948-951 - Zhe Ma, Francky Catthoor, Johan Vounckx:
Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms. 952-955 - Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel:
A flexible framework for communication evaluation in SoC design. 956-959 - Zhonghai Lu, Axel Jantsch, Ingo Sander:
Feasibility analysis of messages for on-chip networks using wormhole routing. 960-964 - Junyu Peng, Samar Abdi, Daniel Gajski:
A clustering technique to optimize hardware/software synchronization. 965-968 - Aimen Bouchhima, Iuliana Bacivarov, Wassim Youssef, Marius Bonaciu, Ahmed Amine Jerraya:
Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration. 969-972 - Chunhui Zhang, Fadi J. Kurdahi:
On combining iteration space tiling with data space tiling for scratch-pad memory systems. 973-976 - Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari:
REMIC: design of a reactive embedded microprocessor core. 977-981 - Thilo Streichert, Christian Haubelt, Jürgen Teich:
Online hardware/software partitioning in networked embedded systems. 982-985 - Lisane B. de Brisolara, Leandro Buss Becker
Comparing high-level modeling approaches for embedded system design. 986-989 - Hai Zhou:
Deriving a new efficient algorithm for min-period retiming. 990-993 - Kuo-Hua Wang, Jia-Hung Chen:
K-disjointness paradigm with application to symmetry detection for incompletely specified functions. 994-997 - Petra Färm, Elena Dubrova, Andreas Kuehlmann:
Logic optimization using rule-based randomized search. 998-1001 - Guowu Yang, Xiaoyu Song, William N. N. Hung, Marek A. Perkowski:
Fast synthesis of exact minimal reversible circuits using group theory. 1002-1005 - Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone:
Design and design automation of rectification logic for engineering change. 1006-1009 - Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh:
Power minimization for dynamic PLAs. 1010-1013 - Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng:
Integrated algorithmic logical and physical design of integer multiplier. 1014-1017 - Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida:
Arrival time aware scheduling to minimize clock cycle length. 1018-1021 - William B. Toms, David A. Edwards:
Efficient synthesis of speed-independent combinational logic circuits. 1022-1026 - Peter Suaris, Dongsheng Wang, Nan-Chi Chou:
A practical cut-based physical retiming algorithm for field programmable gate arrays. 1027-1030 - Dennis Wu, Jianwen Zhu:
BDD-based two variable sharing extraction. 1031-1034
Poster session II
- Eduard Cerny, Ashvin Dsouza, Kevin Harer, Pei-Hsin Ho, Hi-Keung Tony Ma:
Supporting sequential assumptions in hybrid verification. 1035-1038 - Tun Li, Dan Zhu, Lei Liang, Yang Guo, Sikun Li:
Automatic functional test program generation for microprocessor verification. 1039-1042 - Georgios Logothetis:
Forward symbolic model checking for real time systems. 1043-1046 - Yinlei Yu, Sharad Malik
Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice. 1047-1051 - Hao Shen, Yuzhuo Fu:
Priority directed test generation for functional verification using neural networks. 1052-1055 - Miroslav N. Velev
Comparison of schemes for encoding unobservability in translation to SAT. 1056-1059 - Guowu Yang, Jin Yang, William N. N. Hung, Xiaoyu Song:
Implication of assertion graphs in GSTE. 1060-1063 - Qing Xu, Carl Tropper:
XTW, a parallel and distributed logic simulator. 1064-1069 - Rong Jiang, Charlie Chung-Ping Chen:
Comprehensive frequency dependent interconnect extraction and evaluation methodology. 1070-1073 - Takashi Sato
On-chip thermal gradient analysis and temperature flattening for SoC design. 1074-1077 - Akira Tsuchiya, Masanori Hashimoto
Return path selection for loop RL extraction. 1078-1081 - Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Anestis Dounavis:
Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects. 1082-1085 - Yongjun Xu, Jinghua Chen, Zuying Luo, Xiaowei Li:
Vector extraction for average total power estimation. 1086-1089 - Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu:
Relaxed hierarchical power/ground grid analysis. 1090-1093 - Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan:
Sleep transistor sizing using timing criticality and temporal currents. 1094-1097 - Masanori Hashimoto
Timing analysis considering temporal supply voltage fluctuation. 1098-1101 - G. Peter Fang, David C. Yeh, David T. Zweidinger, Lawrence A. Arledge Jr., Vinod Gupta:
Fast, accurate MOS table model for circuit simulation using an unstructured grid and preserving monotonicity. 1102-1106 - Chiu-Wing Sham
Congestion prediction in floorplanning. 1107-1110 - Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong
CMP aware shuttle mask floorplanning. 1111-1114 - Renshen Wang, Sheqin Dong, Xianlong Hong:
An improved P-admissible floorplan representation based on Corner Block List. 1115-1118 - Jason Cong, Michail Romesis, Joseph R. Shinnerl:
Fast floorplanning by look-ahead enabled recursive bipartitioning. 1119-1122 - Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu:
LFF algorithm for heterogeneous FPGA floorplanning. 1123-1126 - Mongkol Ekpanyapong, Michael B. Healy, Sung Kyu Lim
Placement for configurable dataflow architecture. 1127-1130 - Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, Sung Kyu Lim
Wire congestion and thermal aware 3D global placement. 1131-1134 - Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang:
Placement with symmetry constraints for analog layout design using TCG-S. 1135-1137
Poster session III
- Qingzhou (Ben) Wang, John Lillis, Shubhankar Sanyal:
An LP-based methodology for improved timing-driven placement. 1139-1143 - Charles J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz:
Placement stability metrics. 1144-1147 - Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong
Redundant-via enhanced maze routing for yield improvement. 1148-1151 - Jia Wang, Hai Zhou:
Interconnect estimation without packing via ACG floorplans. 1152-1155 - Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra:
Timing driven track routing considering coupling capacitance. 1156-1159 - Tai-Chen Chen, Yao-Wen Chang:
Multilevel full-chip gridless routing considering optical proximity correction. 1160-1163 - Ruibing Lu, Aiqun Cao, Cheng-Kok Koh:
Improving the scalability of SAMBA bus architecture. 1164-1167 - Jeng-Liang Tsai, Charlie Chung-Ping Chen:
Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. 1168-1171 - Ho Fai Ko, Qiang Xu
Register-transfer level functional scan for hierarchical designs. 1172-1175 - Yu Huang, Wu-Tung Cheng, Greg Crowell:
Using fault model relaxation to diagnose real scan chain defects. 1176-1179 - Baosheng Wang, Josh Yang, Yuejian Wu, André Ivanov:
A retention-aware test power model for embedded SRAM. 1180-1183 - Chih-Feng Li, Shao-Sheng Yang, Tsin-Yuan Chang:
On-chip accumulated jitter measurement for phase-locked loops. 1184-1187 - Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang:
SoC test scheduling using the B-tree based floorplanning technique. 1188-1191 - Tongquan Wei, Kaijie Wu, Ramesh Karri
Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. 1192-1195 - Ying Chen, Dennis Abts, David J. Lilja:
Efficiently generating test vectors with state pruning. 1196-1199 - E. Syam Sundar Reddy, Vikram Chandrasekhar
Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. 1200-1203 - Dong Feng, Bingxue Shi:
Comprehensive analysis and optimization of CMOS LNA noise performance. 1204-1207 - Junghyun Cho, Suk-Byung Chai, Chung-Gi Song, Kyung-Won Min, Shiho Kim:
An analog front-end IP for 13.56MHz RFID interrogators. 1208-1211 - Ali Zahabi, Omid Shoaei, Yarallah Koolivand, Parviz Jabedar Maralani:
A two-stage genetic algorithm method for optimization the Sigma-Delta modulators. 1212-1215 - Gong Qian, Yuan Guo-shun:
A novel differential VCO circuit design for USB Hub. 1216-1219 - M. S. Bhat, H. S. Jamadagni:
Static power minimization in current-mode circuits. 1220-1223 - A novel transmitter for 1000Base-T physical transceiver. 1224-1227
- Yongjian Tang, Lenian He, Xiaolang Yan:
A novel data processing circuit in high-speed serial communication. 1228-1231 - Ziqiang Wang, Baoyong Chi, Min Lin, Shuguang Han, Lu Liu, Jinke Yao, Zhihua Wang:
A monolithic CMOS L band DAB receiver. 1232-1235 - Yonggang Tao, Yongsheng Xu, Wei Jin, Hui Yu, Zongsheng Lai:
A bipolar IF amplifier/RSSI for ASK receiver. 1236-1239
Poster session IV
- Rajarshi Mukherjee, Seda Ogrenci Memik:
Evaluation of dual VDD fabrics for low power FPGAs. 1240-1243 - Jae-Jin Lee, Gi-Yong Song:
Design of an application-specific PLD architecture. 1244-1247 - Mitsuru Tomono, Masaki Nakanishi, Katsumasa Watanabe, Shigeru Yamashita:
Event-oriented computing with reconfigurable platform. 1248-1251 - Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
Reconfigurable adaptive FEC system with interleaving. 1252-1255 - Adeoye Olugbon, Sami Khawam, Tughrul Arslan, Ioannis Nousias, Iain Lindsay:
An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks. 1256-1259 - Xin Jia, Ranga Vemuri
Using GALS architecture to reduce the impact of long wire delay on FPGA performance. 1260-1263 - Tiejun Li, Sikun Li, Cheng-Dong Shen:
A novel configurable motion estimation architecture for high-efficiency MPEG-4/H.264 encoding. 1264-1267 - Chang Hoon Kim, Soonhak Kwon, Chun Pyo Hong:
A fast digit-serial systolic multiplier for finite field GF(2m). 1268-1271 - Zhu Xiangbin, Shi-liang Tu:
Adaptive fuzzy control scheduling of window-constrained real-time systems. 1272-1275 - Bo Shen, Junhua Tian, Zheng Li, Jianing Su, Qianling Zhang:
A high performance QAM receiver for digital cable TV with integrated A/D and FEC decoder. 1276-1279 - Lin Xie, Peiliang Qiu, Qinru Qiu:
Partitioned bus coding for energy reduction. 1280-1283 - Yanju Han, Chao Xu, Yizhen Zhang:
An improved bit-plane and pass dual parallel architecture for coefficient bit modeling in JPEG2000. 1284-1287 - Yi-Ran Sun, Svante Signell:
A generalized quadrature bandpass sampling in radio receivers. 1288-1291 - Xin Lu, Yuzhuo Fu:
Reducing leakage power in instruction cache using WDC for embedded processors. 1292-1295 - Qiang Wu, Jinian Bian, Hongxi Xue:
System-level architectural exploration using allocation-on-demand technique. 1296-1298 - Pooya Torkzadeh, Armin Tajalli
A fractional delay-locked loop for on chip clock generation applications. 1300-1309 - Jaehwan John Lee
A novel O(n) parallel banker's algorithm for System-on-a-Chip. 1304-1308 - Zhihui Xiong, Sikun Li, Jihua Chen:
Hardware/software co-design using hierarchical platform-based design method. 1309-1312 - Yan Zhang:
Architecture and performance comparison of a statistic-based lottery arbiter for shared bus on chip. 1313-1316 - Sri Hari Krishna Narayanan, Seung Woo Son, Mahmut T. Kandemir, Feihui Li:
Using loop invariants to fight soft errors in data caches. 1317-1320
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