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ASP-DAC 2000: Yokohama, Japan
- Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan. ACM 2000, ISBN 0-7803-5974-7
- Michael C.-J. Lin, Youn-Long Lin:
A VLSI implementation of the blowfish encryption/decryption algorithm. 1-2 - Oliver Yuk-Hang Leung, Chi-Ying Tsui
, Roger S. Cheng
VLSI implementation of rake receiver for IS-95 CDMA Testbed using FPGA. 3-4 - Chi-Ying Tsui
VLSI implementation of a switch fabric for mixed ATM and IP traffic. 5-6 - J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W. Lee, Y.-C. Kim, S.-J. Jeong:
Design of digital neural cell scheduler for intelligent IB-ATM switch. 7-8 - Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Masataka Yamane, Hajime Ueno:
Genetic algorithm accelerator GAA-II. 9-10 - Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu
A programmable built-in self-test core for embedded memories. 11-12 - Fan Mo, Yihua Zhang, Jun Yu, Qianling Zhang:
An algorithm for VLSI implementation of highly efficient cubic-polynomial evaluation. 13-14 - Tin-Y. Tang, Chiu-sing Choy, Pui-Lam Siu, Cheong-Fat Chan:
Design of self-timed asynchronous Booth's multiplier. 15-16 - Seung-Min Lee, Jin-Hong Chung, Hying-S. Yoon, Mike Myung-Ok Lee:
High speed and ultra-low power 16×16 MAC deisgn using TG techniques for web-based multimedia system. 17-18 - Noriaki Takeda, Mitsuru Homma, Makoto Nagata
A smart imager for the vision processing front-END. 19-20 - Tomohiro Nezuka, Takafumi Fujita, Makoto Ikeda, Kunihiro Asada:
A binary image sensor with flexible motion vector detection using block matching method. 21-22 - Kenichi Murakoshi, Takashi Morie, Makoto Nagata
An arbitrary chaos generator core curcuit using PWM/PPM signals. 23-24 - Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe:
An application specific Java processor with reconfigurabilities. 25-26 - Hiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka, Nobuyoshi Shoji, Hiroaki Kobayashi, Tadao Nakamura:
Reconfigurable synchronized dataflow processor. 27-28 - Naoki Nishimura, Takahiro Sasaki, Tetsuo Hironaka:
Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor system. 29-30 - Takahiro Kawaguchi, Takayuki Suzuki, Hideharu Amano:
A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system. 31-32 - Hirofumi Sakamoto, Ken'ichiro Uda, Bu-Yeol Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda:
A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL. 33-34 - Joonho Lim, Dong-Gyu Kim, Sang-Chul Kang, Soo-Ik Chae:
An 8×8 nRERL serial multiplier for ultra-low-power aplications. 35-36 - Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud:
Embedded tutorial: essential issues for IP reuse. 37-42 - Nong Fan, Viraphol Chaiyakul, Daniel Gajski:
Usage-based characterization of complex functional blocks for reuse in behavioral synthesis. 43-48 - Rainer Dömer, Daniel Gajski:
Reuse and protection of intellectual property in the SpecC system. 49-54 - Gang Qu, Jennifer L. Wong, Miodrag Potkonjak:
Fair watermarking techniques. 55-60 - Riccardo Forth, Paul Molitor
An efficient heuristic for state encoding minimizing the BDD representations of the transistion relations of finite state machines. 61-66 - Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita:
Automatic partitioning for efficient combinatorial verification. 67-72 - Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura, Atsumu Iseno:
A hardware simulation engine based on decision diagrams (short paper). 73-76 - Subir K. Roy
Formal verification based on assume and guarantee approach - a case study (short paper). 77-80 - Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe:
Multi-clock path analysis using propositional satisfiability. 81-86 - Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani:
Self-reforming routing for stochastic search in VLSI interconnection layout. 87-92 - Naofumi Tsujii, Katsutoshi Baba, Shuji Tsukiyama:
An interconnect topology optimization by a tree transformation. 93-98 - Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi:
Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. 99-104 - Yan Zhang, Baohua Wang, Yici Cai, Xianlong Hong:
Area routing oriented hierarchical corner stitching with partial bin. 105-110 - Stephen S. Brown, Jeet Asher, William H. Mangione-Smith:
Offline program re-mapping to improve branch prediction efficiency in embedded systems. 111-116 - Dinesh Ramanathan, Ravindra Jejurikar, Rajesh K. Gupta:
Timing driven co-design of networked embedded systems. 117-122 - Kimiyoshi Usami, Mutsunori Igarashi:
Low-power design methodology and applications utilizing dual supply voltages. 123-128 - Yuan Xie, Wayne H. Wolf:
Co-synthesis with custom ASICs. 129-134 - Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou:
A new method for constructing IP level power model based on power sensitivity. 135-140 - Tony Givargis, Frank Vahid, Jörg Henkel:
A hybrid approach for core-based system-level power modeling. 141-146 - Allan Rae, Sri Parameswaran
Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation. 147-152 - Vijay Sundararajan, Keshab K. Parhi
Synthesis of low power folded programmable coefficient FIR digital filters (short paper). 153-156 - Jason Cong, Songjie Xu:
Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs. 157-162 - Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array. 163-168 - Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi:
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs. 169-174 - Toshihiko Takahashi:
A new encoding scheme for rectangle packing problem. 175-178 - Andrew A. Kennings, Igor L. Markov:
Analytical minimization of half-perimeter wirelength. 179-184 - Maogang Wang, Majid Sarrafzadeh:
Modeling and minimization of routing congestion. 185-190 - King L. Tai:
System-in-package (SIP): challenges and opportunities. 191-196 - Albert Lin:
Taiwan foundry for system-in-package (SIP). 197-204 - Michael X. Wang, Katsuharu Suzuki, Wayne Wei-Ming Dai, Yee L. Low, Kevin J. O'Conner, King L. Tai:
Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology. 205-210 - Minqing Liu, Wayne Wei-Ming Dai:
Modeling and analysis of integrated spiral inductors for RF system-in-package. 211-216 - Youngsoo Shin, Kiyoung Choi:
Narrow bus encoding for low power systems. 217-220 - Vijay Sundararajan, Keshab K. Parhi
Data transmission over a bus with peak-limited transition activity. 221-224 - Jinn-Shyan Wang, Po-Hui Yang:
Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier. 225-228 - Ing-Jer Huang, Dao-Zhen Chen:
A new approach to assembly software retargeting for microcontrollers. 229-234 - Rainer Leupers:
Register allocation for common subexpressions in DSP data paths. 235-240 - Johnson S. Kin, Chunho Lee, William H. Mangione-Smith, Miodrag Potkonjak:
A technique for QoS-based system partitioning. 241-246 - Debatosh Debnath, Tsutomu Sasao:
Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions. 247-252 - Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya:
An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation. 253-258 - Tsutomu Sasao, Ken-ichi Kurimoto:
Three parameters to find functional decompositions. 259-264 - Jun Kikuchi, Tetsuo Sasaki, Tohru Hashimoto, Kazuhisa Miyamoto:
Delay-optimal wiring plan for the microprocessor of high performance computing machines. 265-270 - Hong Yu, Xianlong Hong, Yici Cai:
MMP: a novel placement algorithm for combined macro block and standard cell layout design. 271-276 - Jason Cong, Tianming Kong, Faming Liang, Jun S. Liu, Wing Hung Wong, Dongmin Xu:
Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application. 277-282 - Xiang-Dong Tan, Chuanjin Richard Shi:
Symbolic circuit-noise analysis and modeling with determinant decision diagrams. 283-288 - Yoshiyuki Kawakami, Jingkun Fang, Hirokazu Yonezawa, Nobufusa Iwanishi, Lifeng Wu, Alvin I-Hsien Chen, Norio Koike, Ping Chen, Chune-Sin Yeh, Zhihong Liu:
Gate-level aged timing simulation methodology for hot-carrier reliability assurance. 289-294 - Tsuneo Terasawa:
Embedded tutorial: subwavelength lithography. 295-300 - Rajesh Gupta:
Embedded tutorial: IC design technology for building system-on-a-chip. 301-302 - Mizuki Takahashi, Nagisa Ishiura, Akihisa Yamada, Takashi Kambe:
Thread partitioning method for hardware compiler bach. 303-308 - Nozomu Togawa, Masayuki Ienaga, Masao Yanagisawa, Tatsuo Ohtsuki:
An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper). 309-312 - Taewhan Kim, Junhyung Um:
A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper). 313-316 - Norbert Imlig, Ryusuke Konishi, Tsunemichi Shiozawa, Kiyoshi Oguri, Kouichi Nagami, Hideyuki Ito, Minoru Inamori, Hiroshi Nakada:
Communicating logic: an alternative embedded stream processing paradigm. 317-322 - Kazuhito Ito:
A scheduling and allocation method to reduce data transfer time by dynamic reconfiguration. 323-328 - Masakazu Yamashina, Masato Motomura
Reconfigurable computing: its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI: invited talk. 329-332 - Chunhong Chen, Majid Sarrafzadeh:
Power reduction by simultaneous voltage scaling and gate sizing. 333-338 - Massoud Pedram, Xunwei Wu:
Analysis of power-clocked CMOS with application to the design of energy-recovery circuits. 339-344 - Xunwei Wu, Jian Wei, Massoud Pedram, Qing Wu:
Low-power design of sequential circuits using a quasi-synchronous derived clock. 345-350 - José C. Monteiro
FSM decomposition by direct circuit manipulation applied to low power design. 351-358 - Raul Camposano, Olivier Coudert, Patrick Groeneveld, Leon Stok, Ralph H. J. M. Otten:
Timing closure: the solution and its problems. 359-364 - Masayasu Tanaka, N. Tokida, T. Okagaki, Mitiko Miura-Mattausch, Walter Hansch, Hans Jürgen Mattausch:
High performance of short-channel MOSFETs due to an elevated central-channel doping. 365-370 - Mikako Miyama, Shiro Kamohara:
Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters. 371-374 - Andrzej J. Strojwas:
Design for manufacturability: a path from system level to high yielding chips: embedded tutorial. 375-376 - Jan M. Rabaey:
Low-power silicon architecture for wireless communications: embedded tutorial. 377-380 - Seongsoo Lee, Takayasu Sakurai:
Run-time power control scheme using software feedback loop for low-power real-time application. 381-386 - Qing Wu, Qinru Qiu, Massoud Pedram:
An interleaved dual-battery power supply for battery-operated electronics. 387-390 - Rolf Ernst, Ahmed Amine Jerraya:
embedded system design with multiple languages: embedded tutorial. 391-396 - Inki Hong, Darko Kirovski, Miodrag Potkonjak, Marios C. Papaefthymiou:
Symbolic debugging of globally optimized behavioral specifications. 397-400 - Sang-Joon Nam, Jun-Hee Lee, Byoung-Woon Kim, Yeon-Ho Im, Young-Su Kwon, Kyong-Gu Kang, Chong-Min Kyung:
Fast development of source-level debugging system using hardware emulation (short paper). 401-404 - Luc Séméria, Abhijit Ghosh:
Methodology for hardware/software co-verification in C/C++ (short paper). 405-408 - Tzu-Chieh Tien, Youn-Long Lin:
Performance-optimal clustering with retiming for sequential circuits. 409-414 - Wangning Long, Yu-Liang Wu, Jinian Bian:
IBAW: an implication-tree based alternative-wiring logic transformation algorithm. 415-422 - Ramamurti Chandramouli, Vamsi K. Srikantam:
On mixture density and maximum likelihood power estimation via expectation-maximization. 423-428 - Jason Cong, Sung Kyu Lim
Edge separability based circuit clustering with application to circuit partitioning. 429-434 - Hsun-Cheng Lee, Ting-Chi Wang:
Feasible two-way circuit partitioning with complex resource constraints. 435-440 - Jason Cong, Sung Kyu Lim
Performance driven multiway partitioning. 441-446 - Jiangchun Gu, Zeyi Wang, Xianlong Hong:
Hierarchical computation of 3-D interconnect capacitance using direct boundary element method. 447-452 - Shuzhou Fang, Xiaobo Tang, Zeyi Wang, Xianlong Hong:
A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section. 453-456 - W. K. Kal, S. Y. Kim:
An analytic calculation method for delay time of RC-class interconnects. 457-462 - Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng:
A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation. 463-468 - Koichi Nose, Takayasu Sakurai:
Optimization of VDD and VTH for low-power and high speed applications. 469-474 - Nguyen Minh Duc, Takayasu Sakurai:
Compact yet high performance (CyHP) library for short time-to-market with new technologies. 475-480 - Yuan-Bao Hsu, Kao-Shing Hwang
A new CMAC neural network architecture and its ASIC realization. 481-484 - Naji Ghazal, A. Richard Newton, Jan M. Rabaey:
Retargetable estimation scheme for DSP architecture selection. 485-490 - Hyunok Oh, Soonhoi Ha:
Data memory minimization by sharing large size buffers. 491-496 - Hong-Kai Chang, Youn-Long Lin:
Array allocation taking into account SDRAM characteristics. 497-502 - Nina Saxena, Jacob A. Abraham, Avijit Saha:
Causality based generation of directed test cases. 503-508 - Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Fault models and test generation for IDDQ testing: embedded tutorial. 509-514 - Takashi Aikyo:
Issues on SOC testing in DSM area: embedded tutorial. 515-516 - Kazuhisa Okada, Takayuki Yamanouchi, Takashi Kambe:
A cell synthesis method for salicide process. 517-522 - Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky
Monte-Carlo algorithms for layout density control. 523-528 - Makoto Furuie, Bao-Yu Song, Yukihiro Yoshida, Takao Onoye, Isao Shirakawa:
Layout generation of array cell for NMOS 4-phase dynamic logic (short paper). 529-532 - Chieh Lin, Domine M. W. Leenaerts:
A new efficient method for substrate-aware device-level placement (short paper). 533-536 - Mark M. Gourary, Sergey G. Rusakov
The enchancing of efficiency of the harmonic balance analysis by adaptation of preconditioner to circuit nonlinearity. 537-540 - Tao Pi, Chuanjin Richard Shi:
Analog-testability analysis by determinant-decision-diagrams based symbolic analysis. 541-546 - Tomohiro Fujita, Ken-ichi Okada, Hiroaki Fujita, Hidetoshi Onodera, Keikichi Tamaru:
A method for linking process-level variability to system performances. 547-552 - Takayasu Sakurai:
Design challenges for 0.1um and beyond: embedded tutorial. 553-558 - Young-Su Kwon, In-Cheol Park
A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics. 559-564 - Jin-Hua Hong, Cheng-Wen Wu
Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem. 565-570 - Steven E. Schultz:
An introduction to SLDL and Rosetta. 571-572 - Guido Arnout:
SystemC standard. 573-578 - Tommy Kuhn, Wolfgang Rosenstiel:
Java based object oriented hardware specification and synthesis. 579-582 - Peter Flake, Simon J. Davidmann:
Superlog, a unified design language for system-on-chip. 583-586 - Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng
Performance sensitivity analysis using statistical method and its applications to delay. 587-592 - Huan-Chih Tsai, Kwang-Ting Cheng
A testability metric for path delay faults and its application. 593-598 - Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara:
A non-scan DFT method at register-transfer level to achieve complete fault efficiency. 599-604 - Jiun-Lang Huang, Kwang-Ting Cheng
A sigma-delta modulation based BIST scheme for mixed-signal circuits. 605-612 - Young-Deuk Jeon, Byeong-Lyeol Jeon, Seung-Chul Lee, Sang-Min Yoo, Seung-Hoon Lee:
A 12b 50 MHz 3.3V CMOS acquisition time minimized A/D converter. 613-616 - Edoardo Charbon, Luís Miguel Silveira
A benchmark suite for substrate analysis. 617-622 - Makoto Nagata
Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial. 623-630 - Haruyuki Tago, Kazuhiro Hashimoto, Nobuyuki Ikumi, Masato Nagamatsu, Masakazu Suzuoki, Yasuyuki Yamamoto:
Importance of CAD tools and methodology in high speed CPU design: invited talk. 631-634 - Takayuki Kamei, Hideaki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin'ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato
300MHz design methodology of VU for emotion synthesis. 635-640 - Norman Kojima, Yukiko Parameswar, Christian Klingner, Yukio Ohtaguro, Masataka Matsui, Shigeaki Iwasa, Tatsuo Teruyama, Takayoshi Shimazawa, Hideki Takeda, Kouji Hashizume, Haruyuki Tago, Masaaki Yamada:
Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor. 641-646 - Fujio Ishihara, Christian Klinger, Ken-ichi Agawa:
Clock design of 300MHz 128-bit 2-way superscalar microprocessor. 647-652 - Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura
One language or more?: how can we design an SoC at a system level? 653-654 - Yu-Liang Wu, Xiao-Long Yuan, David Ihsin Cheng:
Circuit partitioning with coupled logic restructuring techniques. 655-660 - Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Improved algorithms for hypergraph bipartitioning. 661-666 - Maogang Wang, Sung Kyu Lim, Jason Cong, Majid Sarrafzadeh:
Multi-way partitioning using bi-partition heuristics. 667-672
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